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Wishbone slave generator
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Wishbone slave generator
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c6850dc6
Commit
c6850dc6
authored
Jun 26, 2012
by
Tomasz Wlostowski
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wbgen_rams.lua: fixed clock net name
parent
bb962cb4
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wbgen_rams.lua
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wbgen_rams.lua
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c6850dc6
...
...
@@ -90,8 +90,8 @@ function gen_code_ram(ram)
ram
.
reset_code_main
=
{};
-- wire the obligartory signals - address busses and clocks
table_join
(
ram
.
maps
,
{
vpm
(
"clk_a_i"
,
"
bus_clock_int
"
);
vpm
(
"clk_b_i"
,
csel
(
ram
.
clock
~=
nil
,
ram
.
clock
,
"
bus_clock_int
"
));
table_join
(
ram
.
maps
,
{
vpm
(
"clk_a_i"
,
"
clk_sys_i
"
);
vpm
(
"clk_b_i"
,
csel
(
ram
.
clock
~=
nil
,
ram
.
clock
,
"
clk_sys_i
"
));
vpm
(
"addr_b_i"
,
prefix
..
"_addr_i"
);
vpm
(
"addr_a_i"
,
vi
(
"rwaddr_reg"
,
log2up
(
ram
.
size
)
-
1
,
0
));
});
...
...
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