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Wishbone slave generator
Commit a4515fff authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing… 

cgen_vhdl: fixed f_x_to_zero() function in generated VHDL package causing synthesis error on Mentor Precision
parent 09fa8c89
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Showing with 12 additions and 12 deletions
cgen_vhdl.lua
View file @ a4515fff
......@@ -102,12 +102,12 @@ function cgen_vhdl_package()
emit("package body "..pkg_name.." is");
emit("function f_x_to_zero (x:std_logic) return std_logic is");
emit("begin");
emit("if(x = 'X' or x = 'U') then");
emit("return '0';");
emit("else");
emit("return x;");
emit("end if; ");
emit("begin")
emit("if x = '1' then")
emit("return '1';")
emit("else")
emit("return '0';")
emit("end if;")
emit("end function;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
......
wbgen2
View file @ a4515fff
......@@ -882,12 +882,12 @@ emit("end package;");
emit("");
emit("package body "..t.." is");
emit("function f_x_to_zero (x:std_logic) return std_logic is");
emit("begin");
emit("if(x = 'X' or x = 'U') then");
emit("return '0';");
emit("else");
emit("return x;");
emit("end if; ");
emit("begin")
emit("if x = '1' then")
emit("return '1';")
emit("else")
emit("return '0';")
emit("end if;")
emit("end function;");
emit("function f_x_to_zero (x:std_logic_vector) return std_logic_vector is");
emit("variable tmp: std_logic_vector(x'length-1 downto 0);");
......
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