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VME64x core
Commit dcc45631 authored by dpedrett's avatar dpedrett
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vfc top level, ucf and testbench files updated 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@192 665b4545-5c6b-4c24-801b-41150b02b44b
parent 10dfcdb0
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hdl/boards/vfc/SFpga.ucf
View file @ dcc45631
......@@ -241,7 +241,7 @@ NET "clk_i" LOC = B14;
NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 40 ns HIGH 50%;
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug
NET "leds[0]" LOC = P5;
NET "leds[1]" LOC = R4;
......
hdl/boards/vfc/rtl/IRQ_Generator_Top.vhd
View file @ dcc45631
......@@ -40,8 +40,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -64,8 +64,8 @@
-- Entity declaration
--===========================================================================
entity IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port ( -- IRQ_Generator
clk_i : in std_logic;
......@@ -75,15 +75,15 @@ generic(g_width : integer := c_width;
-- wb slave side
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector (g_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0)
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0)
);
end IRQ_Generator_Top;
--===========================================================================
......@@ -99,7 +99,7 @@ signal s_Int_Count_o : std_logic_vector(31 downto 0);
signal s_Read_IntCount : std_logic;
signal s_data : std_logic_vector(31 downto 0);
signal s_data_f : std_logic_vector(31 downto 0);
signal s_data_o : std_logic_vector(g_width - 1 downto 0);
signal s_data_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal s_IntCount_sel : std_logic;
signal s_Freq_sel : std_logic;
signal s_wea : std_logic;
......@@ -141,7 +141,7 @@ s_en_Freq <= '1' when (s_Freq_sel = '1' and s_wea = '1') else '0';
-- the WB data bus is 32 or 64 bit width, so the following processes have been
-- added:
gen64 : if (g_width = 64) generate
gen64 : if (g_wb_data_width = 64) generate
s_data <= dat_i(63 downto 32);
s_data_f <= dat_i(31 downto 0);
s_data_o <= s_INT_COUNT & s_FREQ;
......@@ -151,7 +151,7 @@ gen64 : if (g_width = 64) generate
'0';
end generate gen64;
gen32 : if (g_width = 32) generate
gen32 : if (g_wb_data_width = 32) generate
s_data <= dat_i;
s_data_f <= dat_i;
s_data_o <= s_INT_COUNT when s_IntCount_sel = '1' else
......
hdl/boards/vfc/rtl/IRQ_generator.vhd
View file @ dcc45631
......@@ -57,8 +57,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ dcc45631
......@@ -60,8 +60,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -77,26 +77,33 @@
---------------------------------------------------------------------------------------
-- uncomment to use the PLL
--Library UNISIM;
--use UNISIM.vcomponents.all;
Library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
use work.genram_pkg.all;
use work.VME_CR_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity TOP_LEVEL is
generic(--WB data width:
g_width : integer := 64; --c_width;
generic(
g_clock : integer := 10;
--WB data width:
g_wb_data_width : integer := 64; --c_width;
-- WB addr width:
g_addr_width : integer := 11; --c_addr_width;
g_wb_addr_width : integer := 11; --c_addr_width;
--CRAM size in the CR/CSR space (bytes):
g_CRAM_SIZE : integer := 1024; --c_CRAM_SIZE;
g_cram_size : integer := 1024; --c_CRAM_SIZE;
--My WB slave memory:
g_WB_memory_size : integer := 1024 -- c_SIZE
g_WB_memory_size : integer := 1024; -- c_SIZE
g_BoardID : integer := 408; -- 0x00000198
g_ManufacturerID : integer := 524336; -- 0x080030
g_RevisionID : integer := 1; -- 0x00000001
g_ProgramID : integer := 90 -- 0x0000005a
);
port(
clk_i : in std_logic;
......@@ -136,9 +143,15 @@ end TOP_LEVEL;
architecture Behavioral of TOP_LEVEL is
component VME64xCore_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
generic(
g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
port(
-- VME signals:
......@@ -169,15 +182,15 @@ component VME64xCore_Top is
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
-- IRQ Generator
......@@ -205,8 +218,9 @@ component xwb_ram is
end component xwb_ram;
component WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
......@@ -214,50 +228,50 @@ generic(g_width : integer := c_width;
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector(g_width - 1 downto 0);
m_dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0);
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector(g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
m_adr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic
);
end component WB_Bridge;
signal WbDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_addr_width - 1 downto 0);
signal WbDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbSel_o : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal WbMemDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_addr_width - 1 downto 0);
signal WbMemDat_i : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemDat_o : std_logic_vector(g_wb_data_width - 1 downto 0);
signal WbMemAdr_i : std_logic_vector(g_wb_addr_width - 1 downto 0);
signal WbMemCyc_i : std_logic;
signal WbMemErr_o : std_logic;
signal WbMemRty_o : std_logic;
signal WbMemSel_i : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbMemSel_i : std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
signal WbMemStb_i : std_logic;
signal WbMemAck_o : std_logic;
signal WbMemWe_i : std_logic;
......@@ -284,8 +298,14 @@ begin
Inst_VME64xCore_Top: VME64xCore_Top
generic map(
g_width => g_width,
g_addr_width => g_addr_width
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size,
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
)
port map(
-- VME
......@@ -360,8 +380,8 @@ Inst_xwb_ram: xwb_ram
Inst_WB_Bridge: WB_Bridge
generic map(
g_width => g_width,
g_addr_width => g_addr_width
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_in,
......@@ -404,63 +424,63 @@ port map(
VME_DATA_DIR_o <= s_VME_DATA_DIR;
---------------------------------------------------------------------------------
-- PLL_BASE_inst : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 4,
-- CLKOUT1_DIVIDE => 1,
-- CLKOUT2_DIVIDE => 1,
-- CLKOUT3_DIVIDE => 1,
-- CLKOUT4_DIVIDE => 1,
-- CLKOUT5_DIVIDE => 1,
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- -- Duty cycle for CLKOUT# clock output (0.01-0.99).
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DUTY_CYCLE => 0.500,
-- CLKOUT4_DUTY_CYCLE => 0.500,
-- CLKOUT5_DUTY_CYCLE => 0.500,
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- -- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT4_PHASE => 0.000,
-- CLKOUT5_PHASE => 0.000,
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "SYSTEM_SYNCHRONOUS",
-- DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
-- REF_JITTER => 0.016,-- Reference Clock Jitter in UI (0.000-0.999).
-- RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
-- )
-- port map (
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-- CLKOUT0 => clk_in_buf, --clk 100 MHz
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- CLKIN => clk_i, -- 1-bit input: Clock input
-- RST => '0' -- 1-bit input: Reset input
-- );
--cmp_clk_dmtd_buf : BUFG
-- port map
-- (O => clk_in,
-- I => clk_in_buf);
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016,-- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_in,
I => clk_in_buf);
-- comment the next line if the PLL is used:
clk_in <= clk_i;
-- clk_in <= clk_i;
end Behavioral;
--===========================================================================
-- Architecture end
......
hdl/boards/vfc/rtl/WB_Bridge.vhd
View file @ dcc45631
......@@ -20,8 +20,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -45,8 +45,8 @@ use work.vme64x_pack.all;
-- Entity declaration
--===========================================================================
entity WB_Bridge is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
Port ( clk_i : in std_logic;
rst_i : in std_logic;
......@@ -54,26 +54,26 @@ generic(g_width : integer := c_width;
Int_Req_o : out std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector (g_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector (g_wb_addr_width - 1 downto 0);
dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0);
sel_i : in std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector (g_width - 1 downto 0);
dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_cyc_o : out std_logic;
m_stb_o : out std_logic;
m_adr_o : out std_logic_vector (g_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_width) - 1 downto 0);
m_adr_o : out std_logic_vector (g_wb_addr_width - 1 downto 0);
m_dat_o : out std_logic_vector (g_wb_data_width - 1 downto 0);
m_sel_o : out std_logic_vector (f_div8(g_wb_data_width) - 1 downto 0);
m_we_o : out std_logic;
m_ack_i : in std_logic;
m_err_i : in std_logic;
m_stall_i : in std_logic;
m_rty_i : in std_logic;
m_dat_i : in std_logic_vector (g_width - 1 downto 0));
m_dat_i : in std_logic_vector (g_wb_data_width - 1 downto 0));
end WB_Bridge;
--===========================================================================
-- Architecture declaration
......@@ -89,11 +89,11 @@ signal s_ack_gen : std_logic;
signal s_err_gen : std_logic;
signal s_rty_gen : std_logic;
signal s_stall_gen : std_logic;
signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
signal s_data_o_gen : std_logic_vector(g_wb_data_width - 1 downto 0);
component IRQ_Generator_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
clk_i : in std_logic;
......@@ -101,16 +101,16 @@ signal s_data_o_gen : std_logic_vector(g_width - 1 downto 0);
Int_Ack_i : in std_logic;
cyc_i : in std_logic;
stb_i : in std_logic;
adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
adr_i : in std_logic_vector(g_wb_addr_width - 1 downto 0);
sel_i : in std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
we_i : in std_logic;
dat_i : in std_logic_vector(g_width - 1 downto 0);
dat_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
Int_Req_o : out std_logic;
ack_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
stall_o : out std_logic;
dat_o : out std_logic_vector(g_width - 1 downto 0)
dat_o : out std_logic_vector(g_wb_data_width - 1 downto 0)
);
end component IRQ_Generator_Top;
--===========================================================================
......@@ -121,11 +121,11 @@ begin
-- check if the IRQ Generator is addressed (0x00 or 0x04).
-- if not s_WbAppl is '1' and the component work as a bridge
-- between the vme64x core and the Wb Application
genIRQGen64 : if (g_width = 64) generate
genIRQGen64 : if (g_wb_data_width = 64) generate
s_IRQGen <= '1' when (unsigned(adr_i) = 0) else '0';
end generate genIRQGen64;
genIRQGen32 : if (g_width = 32) generate
genIRQGen32 : if (g_wb_data_width = 32) generate
s_IRQGen <= '1' when unsigned(adr_i) = 0 or
unsigned(adr_i) = 1 else '0';
end generate genIRQGen32;
......@@ -154,8 +154,8 @@ m_sel_o <= sel_i;
m_we_o <= we_i;
----------------------------------------------------------------------
Inst_IRQ_Generator_Top: IRQ_Generator_Top
generic map(g_width => g_width,
g_addr_width => g_addr_width
generic map(g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
clk_i => clk_i,
......
hdl/boards/vfc/rtl/ram_8bits.vhd
View file @ dcc45631
......@@ -9,8 +9,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/vfc/rtl/spram.vhd
View file @ dcc45631
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/vfc/rtl/xwb_ram.vhd
View file @ dcc45631
......@@ -38,8 +38,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/boards/vfc/sim/testbench/VME64x_SIM_Package.vhd
View file @ dcc45631
......@@ -9,7 +9,7 @@
--
-- Company : CERN
--
-- Description : VME64x procedures for test the VME64x Slave
-- Description : VME64x procedures for test the VME64x core
library IEEE;
library std;
......@@ -236,7 +236,7 @@ begin
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
-- assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
--assert (VME64xBus_In.Vme64xDATA = s_dataToReceive)report "Error Received Wrong Data" severity failure;
--wait for 10 ns;
......@@ -465,7 +465,7 @@ DataType : out std_logic_vector (3 downto 0)) is
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
-- assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
end if;
......@@ -529,7 +529,7 @@ DataType : out std_logic_vector (3 downto 0)) is
exit;
else
v_dataToReceiveOut := VME64xBus_In.Vme64xDATA;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
-- assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
end if;
VME64xBus_Out.Vme64xDs0N <= '1';
......@@ -739,7 +739,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
--assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x
VME64xBus_Out.Vme64xDs0N <= '1';
VME64xBus_Out.Vme64xDs1N <= '1';
......@@ -971,7 +971,7 @@ DataType : out std_logic_vector (3 downto 0)) is
assert(VME64xBus_In.Vme64xBerrN /= '1') report "THE SLAVE ASSERTED THE Berr LINE" severity error;
else
ShiftData(write_n => '1', s_dataTransferType => s_dataTransferType, s_dataToShift => VME64xBus_In.Vme64xDATA, v_dataToShiftOut => v_dataToReceiveOut);
assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut /= s_dataToReceive)report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_dataToReceive)report "RECEIVED WRONG DATA!!!" severity failure;
end if;
VME64xBus_Out.Vme64xLWORDN <= '1';
......@@ -1112,7 +1112,7 @@ DataType : out std_logic_vector (3 downto 0)) is
exit;
else
v_dataToReceiveOut := VME64xBus_In.Vme64xDATA;
assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut /= s_Buffer_BLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_BLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
end if;
VME64xBus_Out.Vme64xDs0N <= '1';
......@@ -1265,7 +1265,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR;
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x
VME64xBus_Out.Vme64xDs0N <= '1';
......@@ -1458,7 +1458,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_dataToReceiveOut(63 downto 33) := VME64xBus_In.Vme64xADDR;
v_dataToReceiveOut(31 downto 0) := VME64xBus_In.Vme64xDATA;
v_dataToReceiveOut(32) := VME64xBus_In.Vme64xLWORDN;
assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
--assert (v_dataToReceiveOut /= s_Buffer_MBLT(n))report "CORRECT DATA!!!" severity error;
assert (v_dataToReceiveOut = s_Buffer_MBLT(n))report "RECEIVED WRONG DATA!!!" severity failure;
--NB start to read from the first location written otherwise use n + x
n := n + 1;
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ dcc45631
......@@ -24,34 +24,35 @@ ARCHITECTURE behavior OF VME64x_TB IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT TOP_LEVEL
PORT(
clk_i : IN std_logic;
VME_AS_n_i : IN std_logic;
VME_RST_n_i : IN std_logic;
VME_WRITE_n_i : IN std_logic;
VME_AM_i : IN std_logic_vector(5 downto 0);
VME_DS_n_i : IN std_logic_vector(1 downto 0);
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_BERR_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic;
VME_RETRY_n_o : OUT std_logic;
VME_RETRY_OE_o : OUT std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACK_n_i : IN std_logic;
VME_IACKIN_n_i : IN std_logic;
VME_IACKOUT_n_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_DIR_o : OUT std_logic;
VME_DATA_OE_N_o : OUT std_logic;
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
Reset : IN std_logic
);
END COMPONENT;
COMPONENT TOP_LEVEL
PORT(
clk_i : IN std_logic;
Reset : IN std_logic;
VME_AS_n_i : IN std_logic;
VME_RST_n_i : IN std_logic;
VME_WRITE_n_i : IN std_logic;
VME_AM_i : IN std_logic_vector(5 downto 0);
VME_DS_n_i : IN std_logic_vector(1 downto 0);
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_IACKIN_n_i : IN std_logic;
VME_IACK_n_i : IN std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
VME_BERR_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic;
VME_RETRY_n_o : OUT std_logic;
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : OUT std_logic;
VME_RETRY_OE_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_DIR_o : OUT std_logic;
VME_DATA_OE_N_o : OUT std_logic;
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
leds : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
......@@ -111,34 +112,35 @@ ARCHITECTURE behavior OF VME64x_TB IS
constant clk_i_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: TOP_LEVEL PORT MAP(
clk_i => clk_i,
Reset => Reset,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
leds => open
);
-- Instantiate the Unit Under Test (UUT)
uut: TOP_LEVEL PORT MAP (
clk_i => clk_i,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => VME_RST_n_i,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
Reset => Reset
);
VME_IACKIN_n_i <= VME64xBus_out.Vme64xIACKIN;
VME_IACK_n_i <= VME64xBus_out.Vme64xIACK;
......@@ -722,11 +724,11 @@ BEGIN
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- s_dataToReceive <= x"00000000";
-- s_dataToReceive <= x"00000001";
-- ReadCR_CSR(c_address => c_WB32or64, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- Module Enabled:
s_dataTransferType <= D08Byte3;
......@@ -1250,27 +1252,18 @@ BEGIN
s_dataTransferType <= D32; --only D32 is possible with BLT transfer
s_AddressingType <= A32_BLT;
s_address <= x"0000000000000010";
s_num <= "000000011"; --Number of access; (max 64)
s_num <= "100000001"; --Number of access; (max 64)
Blt_write(v_address => s_address, s_Buffer_BLT => s_Buffer_BLT,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType,
num => s_num, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 10 ns;
s_address <= x"0000000000000010"; -- use n+1 inside the function if I start to read from the second D32 word written
s_num <= "000000011";
Blt_Read(v_address => s_address, s_Buffer_BLT => s_Buffer_BLT,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType,
num => s_num, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 10 ns;
s_address <= x"0000000000000010"; -- use n+1 inside the function if I start to read from the second D32 word written
s_num <= "000000001";
s_num <= "000000100";
Blt_Read(v_address => s_address, s_Buffer_BLT => s_Buffer_BLT,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType,
num => s_num, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
-- Check error condition:
wait for 10 ns;
s_dataTransferType <= D08Byte3; --only D32 is possible with BLT transfer
......@@ -1340,120 +1333,120 @@ BEGIN
s_Buffer_MBLT(5) <= x"56789ABCDEF01234";
s_Buffer_MBLT(6) <= x"6789ABCDEF012345";
s_Buffer_MBLT(7) <= x"789ABCDEF0123456";
-- uncomment if WB bus is 64 bit
--
-- s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
-- s_AddressingType <= A32_MBLT;
-- s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
-- s_num <= "000001000"; -- max 256;
--
-- Mblt_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
-- s_dataToReceive <= x"00000040";
-- ReadCR_CSR(c_address => c_BYTES0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
-- s_AddressingType <= A32_MBLT;
-- s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
-- s_num <= "000000011"; -- max 256;
--
-- Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
--
-- for i in 1 downto 0 loop
-- Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
-- end loop;
--
--
--
--
--
-- -- Test Error condition: The Master can't access with s_AddressingType <= MBLT and Data transfer type /= D32
-- wait for 20 ns;
--
-- s_dataTransferType <= D16Byte01; -- Data transfer type is D32 also if the data width is 64!!
-- s_AddressingType <= A32_MBLT;
-- s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
-- s_num <= "000000100"; -- max 256;
--
-- Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
-- -- The master can't access at more than 256 locations (2048 Bytes)
-- wait for 20 ns;
--
-- s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
-- s_AddressingType <= A32_MBLT;
-- s_address <= x"0000000000000000"; --Put here a multiple of 8!!!
-- s_num <= "100000001"; -- max 256;
--
-- Mblt_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
--
-- --A24 MBLT
-- --the master write the ADER 0:
-- wait for 20 ns;
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER0_A24_MBLT(31 downto 24);
-- WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER0_A24_MBLT(23 downto 16);
-- WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER0_A24_MBLT(15 downto 8);
-- WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER0_A24_MBLT(7 downto 0);
-- WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
-- -- ADER0 written
--
-- s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
-- s_AddressingType <= A24_MBLT;
-- s_address <= x"0000000000000008"; --Put here a multiple of 8!!!
-- s_num <= "000000100"; -- max 256;
--
-- Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
-- s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
-- VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A32_MBLT;
s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
s_num <= "000001000"; -- max 256;
Mblt_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToReceive <= x"00000040";
ReadCR_CSR(c_address => c_BYTES0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A32_MBLT;
s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
s_num <= "000000011"; -- max 256;
Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
for i in 1 downto 0 loop
Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
end loop;
-- Test Error condition: The Master can't access with s_AddressingType <= MBLT and Data transfer type /= D32
wait for 20 ns;
s_dataTransferType <= D16Byte01; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A32_MBLT;
s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
s_num <= "000000100"; -- max 256;
Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
-- The master can't access at more than 256 locations (2048 Bytes)
wait for 20 ns;
s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A32_MBLT;
s_address <= x"0000000000000000"; --Put here a multiple of 8!!!
s_num <= "100000001"; -- max 256;
Mblt_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
--A24 MBLT
--the master write the ADER 0:
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(31 downto 24);
WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(23 downto 16);
WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(15 downto 8);
WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(7 downto 0);
WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
-- ADER0 written
s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A24_MBLT;
s_address <= x"0000000000000008"; --Put here a multiple of 8!!!
s_num <= "000000100"; -- max 256;
Mblt_Read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT, -- this procedure is for A16, A24, A32 address type
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType, num => s_num,
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
report "Start Test Interrupter";
......
hdl/boards/vfc/syn/VME64xTest.xise
View file @ dcc45631
......@@ -15,10 +15,6 @@
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
<file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
......@@ -132,6 +128,10 @@
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="26"/>
<association xil_pn:name="Implementation" xil_pn:seqID="24"/>
</file>
</files>
<autoManagedFiles>
......@@ -255,7 +255,7 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -295,8 +295,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
......@@ -392,8 +392,9 @@
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......
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