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VME64x core
Commit d4659ea1 authored by dpedrett's avatar dpedrett
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SVEC pts firmware uploaded 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@169 665b4545-5c6b-4c24-801b-41150b02b44b
parent 27015106
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hdl/boards/svec_pts/SVEC.ucf 0 → 100644
View file @ d4659ea1
NET "Reset" LOC = P24;
NET "VME_ADDR_DIR_o" LOC = N5;
NET "VME_ADDR_OE_N_o" LOC = N4;
NET "VME_AM_i[0]" LOC = AK2;
NET "VME_AM_i[1]" LOC = AE4;
NET "VME_AM_i[2]" LOC = AF4;
NET "VME_AM_i[3]" LOC = AF3;
NET "VME_AM_i[4]" LOC = AG3;
NET "VME_AM_i[5]" LOC = V8;
NET "VME_DATA_b[0]" LOC = AA10;
NET "VME_DATA_b[1]" LOC = AA9;
NET "VME_DATA_b[2]" LOC = AD7;
NET "VME_DATA_b[3]" LOC = AE7;
NET "VME_DATA_b[4]" LOC = Y9;
NET "VME_DATA_b[5]" LOC = Y8;
NET "VME_DATA_b[6]" LOC = AE6;
NET "VME_DATA_b[7]" LOC = AF6;
NET "VME_DATA_b[8]" LOC = W11;
NET "VME_DATA_b[9]" LOC = Y11;
NET "VME_DATA_b[10]" LOC = AE5;
NET "VME_DATA_b[11]" LOC = AG5;
NET "VME_DATA_b[12]" LOC = T7;
NET "VME_DATA_b[13]" LOC = T6;
NET "VME_DATA_b[14]" LOC = AA7;
NET "VME_DATA_b[15]" LOC = AA6;
NET "VME_DATA_b[16]" LOC = AC6;
NET "VME_DATA_b[17]" LOC = AD6;
NET "VME_DATA_b[18]" LOC = AH5;
NET "VME_DATA_b[19]" LOC = AK5;
NET "VME_DATA_b[20]" LOC = W10;
NET "VME_DATA_b[21]" LOC = W9;
NET "VME_DATA_b[22]" LOC = AB7;
NET "VME_DATA_b[23]" LOC = AB6;
NET "VME_DATA_b[24]" LOC = W7;
NET "VME_DATA_b[25]" LOC = W6;
NET "VME_DATA_b[26]" LOC = AJ4;
NET "VME_DATA_b[27]" LOC = AK4;
NET "VME_DATA_b[28]" LOC = T9;
NET "VME_DATA_b[29]" LOC = T8;
NET "VME_DATA_b[30]" LOC = AH3;
NET "VME_DATA_b[31]" LOC = AK3;
NET "VME_IACK_n_i" LOC = N1;
NET "VME_RETRY_OE_o" LOC = R4;
NET "VME_RETRY_n_o" LOC = AB2;
NET "VME_RST_n_i" LOC = P4;
#NET "VmeTck_i" LOC = D22;
#NET "VmeTdi_i" LOC = C21;
#NET "VmeTdo_o" LOC = B21;
#NET "VmeTms_i" LOC = D21;
NET "VME_WRITE_n_i" LOC = R1;
#NET "FpLed_onb8_5" LOC = U3;
#NET "FpLed_onb8_6" LOC = U4;
NET "VME_AS_n_i" LOC = P6;
NET "VME_BERR_o" LOC = R3;
#NET "VmeDDirVfcToVdme_o" LOC = L9;
NET "VME_DATA_DIR_o" LOC = P2;
NET "VME_IACKIN_n_i" LOC = P7;
NET "VME_IACKOUT_n_o" LOC = N3;
NET "VME_IRQ_n_o[0]" LOC = AG4;
NET "VME_IRQ_n_o[3]" LOC = N9;
NET "VME_IRQ_n_o[4]" LOC = AF2;
NET "VME_IRQ_n_o[5]" LOC = AH2;
NET "VME_IRQ_n_o[6]" LOC = R7;
#NET "VmeP0LvdsBunchClkIn_i" LOC = AE15;
#NET "VmeP0LvdsBunchClkOut_o" LOC = AF15;
#NET "VmeSysClk_ik" LOC = L8;
NET "VME_ADDR_b[1]" LOC = AE3;
NET "VME_ADDR_b[2]" LOC = AE1;
NET "VME_ADDR_b[3]" LOC = N8;
NET "VME_ADDR_b[4]" LOC = N7;
NET "VME_ADDR_b[5]" LOC = AC5;
NET "VME_ADDR_b[6]" LOC = AC4;
NET "VME_ADDR_b[7]" LOC = AD4;
NET "VME_ADDR_b[8]" LOC = AD3;
NET "VME_ADDR_b[9]" LOC = AB4;
NET "VME_ADDR_b[10]" LOC = AB3;
NET "VME_ADDR_b[11]" LOC = AD2;
NET "VME_ADDR_b[12]" LOC = AD1;
NET "VME_ADDR_b[13]" LOC = AC3;
NET "VME_ADDR_b[14]" LOC = AC1;
NET "VME_ADDR_b[15]" LOC = Y4;
NET "VME_ADDR_b[16]" LOC = Y3;
NET "VME_ADDR_b[17]" LOC = Y2;
NET "VME_ADDR_b[18]" LOC = Y1;
NET "VME_ADDR_b[19]" LOC = AA5;
NET "VME_ADDR_b[20]" LOC = AA4;
NET "VME_ADDR_b[21]" LOC = W3;
NET "VME_ADDR_b[22]" LOC = W1;
NET "VME_ADDR_b[23]" LOC = V2;
NET "VME_ADDR_b[24]" LOC = V1;
NET "VME_ADDR_b[25]" LOC = U5;
NET "VME_ADDR_b[26]" LOC = U4;
NET "VME_ADDR_b[27]" LOC = U3;
NET "VME_ADDR_b[28]" LOC = U1;
NET "VME_ADDR_b[29]" LOC = T4;
NET "VME_ADDR_b[30]" LOC = T3;
NET "VME_ADDR_b[31]" LOC = T2;
NET "VME_DATA_OE_N_o" LOC = P1;
NET "VME_DS_n_i[0]" LOC = Y7;
NET "VME_DS_n_i[1]" LOC = Y6;
NET "VME_DTACK_OE_o" LOC = T1;
NET "VME_DTACK_n_o" LOC = R5;
NET "VME_GA_i[5]" LOC = M6;
NET "VME_GA_i[0]" LOC = V7;
NET "VME_GA_i[1]" LOC = AH1;
NET "VME_GA_i[2]" LOC = AJ1;
NET "VME_GA_i[3]" LOC = V10;
NET "VME_GA_i[4]" LOC = V9;
NET "VME_IRQ_n_o[1]" LOC = AH4;
NET "VME_IRQ_n_o[2]" LOC = N10;
NET "VME_LWORD_n_b" LOC = M7;
NET "clk_i" LOC = V26;
# PlanAhead Generated IO constraints
#NET "FpLed_onb8_6" IOSTANDARD = LVCMOS33;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/02/21
NET "clk_i" TNM_NET = "clk_i_group";
#TIMESPEC TS_clk_i = PERIOD "clk_i" 50 ns HIGH 50%;
#Created by Constraints Editor (xc6slx150t-fgg676-3) - 2011/06/30
TIMESPEC "TS_clk_i" = PERIOD "clk_i_group" 50 ns HIGH 50%;
# Add by Davide for debug
NET "leds[0]" LOC = AD27;
NET "leds[1]" LOC = AD26;
NET "leds[2]" LOC = AC28;
NET "leds[3]" LOC = AC27;
NET "leds[4]" LOC = AE27;
NET "leds[5]" LOC = AE30;
NET "leds[6]" LOC = AF28;
NET "leds[7]" LOC = AE28;
hdl/boards/svec_pts/rtl/TOP_LEVEL.vhd 0 → 100644
View file @ d4659ea1
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- Description:
-- This file would be an example of a WB slave application.
-- It implements a ram memory (1 KB) and some registers to handle the
-- interrupt service request lines called irq_i
--
-- TOP_LEVEL's block diagram
-- _____________________________________________________________________________
-- ___ | _____________________ _____________________________________ |
-- | B | | | | | wishbone_port_slave component | |
-- | A | | | VME TO WB | | __________________ | |
-- | C | | | INTERFACE | | | idr register | loc. 0x000 | |
-- | K | | | (VME64xCore_Top.vhd)| | |------------------| | |
-- | P |_____|__| | |__| | ier register | loc. 0x001 | |
-- | L |_____|__| | |__| |------------------| | |
-- | A | | | VME | WB | | | isr regiser | loc. 0x002 | |
-- | N | | | SLAVE | MASTER | | |------------------| | |
-- | E | | | | | | | imr register | loc. 0x003 | |
-- | | | | | | | |------------------| | |
-- | | | | | | | |int_count register| loc. 0x004 | |
-- | | | | | | | |------------------| | |
-- | | | | | | | |int_rate register | loc. 0x005 | |
-- | | | | | | | |------------------| | |
-- | | | | | | | | RAM | ___________ | |
-- | | | | | | | | from loc. 0x100 | | irq || |
-- | | | | | | | | to loc. 0x1ff | | controller||<---- irq_0|
-- | | | | | | | |__________________| | ||<---- irq_1|
-- | | | | | | | |___________|| |
-- |___| | |_____________________| |_____________________________________| |
-- |_____________________________________________________________________________|
--
--
-- Please note that the addresses indicated in the block diagram are the wb bus addresses.
-- To access these locations the VME Master should left shift these addresses of two or three
-- bits according with the wb data bus width which can be 32 or 64 bits.
-- for example: we want write 1 in the ier register (irq_0 enabled):
-- if g_width = 32 --> A32_S access to the VME address 0x04
-- if g_width = 64 --> A32_S access to the VME address 0x0c
-- g_width refers to the wb data bus width and to the memory and registers width.
-- See also the "Data organization in VME and WB bus" section of the vme64x_user_manual
-- The irq lines are drived by two counters.
-- The irq_0 line is active on the rising edge and the irq_1 on the falling edge.
-- Two pulse generator are used to generate a pulse on the rising/falling edges of the
-- irq_0/irq_1. These pulses increment the interrupt counter register (loc. 0x004).
-- The software can enable/disenable these irq lines setting the corresponding bits in the
-- ier/idr register.
-- ier register = interrupt enable mask register
-- idr register = interrupt disenable mask register
-- The software can check which interrupt request lines are enabled by readind the interrupt
-- mask register (imr register); the imr register is a read only register.
-- A read operation on the idr/ier register returns 0
-- The software can check which peripheral needs service reading the interrupt source register.
-- If two or more WB applications are requesting service at the same time, two or more bits are
-- asserted in the isr register.
-- When the VME Master accesses the isr register in a read operation, this register is
-- cleared by the hardware. To avoid to miss interrupts during this read and clear operation,
-- what the hw does is to overwrite the isr register with the current interrupt request pending
-- vector input.
--______________________________________________________________________________
-- Author:
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 30/10/2012
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- Copyright (c) 2009 - 2011 CERN
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
Library UNISIM;
use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity TOP_LEVEL is
generic(--WB data width:
g_width : integer := 32; -- 32 or 64
-- WB addr width:
g_addr_width : integer := 9; -- 64 or less
--CRAM size in the CR/CSR space (bytes):
g_CRAM_SIZE : integer := 1024
);
port(
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic;
-- VME buffers
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
end TOP_LEVEL;
--===========================================================================
-- Architecture declaration
--===========================================================================
architecture Behavioral of TOP_LEVEL is
component VME64xCore_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
);
port(
-- VME signals:
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
VME_LWORD_n_o : out std_logic;
VME_ADDR_i : in std_logic_vector(31 downto 1);
VME_ADDR_o : out std_logic_vector(31 downto 1);
VME_DATA_i : in std_logic_vector(31 downto 0);
VME_DATA_o : out std_logic_vector(31 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_IRQ_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
DAT_i : in std_logic_vector(g_width - 1 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
-- IRQ Generator
IRQ_i : in std_logic;
INT_ack_o : out std_logic;
reset_o : out std_logic;
-- for debug:
debug : out std_logic_vector(7 downto 0)
);
end component VME64xCore_Top;
component wishbone_port_slave
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_num_irq : integer := 2
);
port(
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
wb_dat_i : in std_logic_vector(g_width - 1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wbslave_reg_int_count_i : in std_logic_vector(g_width - 1 downto 0);
wbslave_ram_addr_i : in std_logic_vector(g_addr_width - 2 downto 0);
wbslave_ram_rd_i : in std_logic;
wbslave_ram_data_i : in std_logic_vector(g_width - 1 downto 0);
wbslave_ram_wr_i : in std_logic;
irq_irq0_i : in std_logic;
irq_irq1_i : in std_logic;
wb_dat_o : out std_logic_vector(g_width - 1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
wbslave_reg_int_rate_o : out std_logic_vector(g_width - 1 downto 0);
wbslave_ram_data_o : out std_logic_vector(g_width - 1 downto 0)
);
end component;
signal WbDat_i : std_logic_vector(g_width - 1 downto 0);
signal WbDat_o : std_logic_vector(g_width - 1 downto 0);
signal WbAdr_o : std_logic_vector(g_addr_width - 1 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_in_buf : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst : std_logic;
signal s_rst_n : std_logic;
signal s_counter0 : unsigned(25 downto 0);
signal s_counter1 : unsigned(25 downto 0);
signal s_1 : std_logic;
signal s_ris_edge : std_logic;
signal s_2 : std_logic;
signal s_fal_edge : std_logic;
signal s_int_counter : unsigned(25 downto 0);
signal s_int_counter_slv : std_logic_vector(g_width - 1 downto 0);
--mux
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_VME_DATA_DIR : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_VME_ADDR_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
Inst_VME64xCore_Top: VME64xCore_Top
generic map(
g_width => g_width,
g_addr_width => g_addr_width,
g_CRAM_SIZE => g_CRAM_SIZE
)
port map(
-- VME
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_LWORD_n_i => VME_LWORD_n_b,
VME_LWORD_n_o => s_VME_LWORD_n_b_o,
VME_ADDR_i => VME_ADDR_b,
VME_ADDR_o => s_VME_ADDR_b_o,
VME_DATA_i => VME_DATA_b,
VME_DATA_o => s_VME_DATA_b_o,
VME_IRQ_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
-- buffer
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
--WB
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
CYC_o => WbCyc_o,
ERR_i => WbErr_i,
RTY_i => WbRty_i,
SEL_o => WbSel_o,
STB_o => WbStb_o,
ACK_i => WbAck_i,
WE_o => WbWe_o,
STALL_i => WbStall_i,
--IRQ Generator
IRQ_i => WbIrq_i,
INT_ack_o => s_INT_ack,
reset_o => s_rst, --asserted when '1'
-- Add by Davide for debug:
debug => leds
);
Inst_wishbone_port_slave: wishbone_port_slave
generic map(
g_width => g_width,
g_addr_width => g_addr_width,
g_num_irq => 2
)
port map(
rst_n_i => s_rst_n,
clk_sys_i => clk_in,
wb_adr_i => WbAdr_o,
wb_dat_i => WbDat_o,
wb_dat_o => WbDat_i,
wb_cyc_i => WbCyc_o,
wb_sel_i => WbSel_o,
wb_stb_i => WbStb_o,
wb_we_i => WbWe_o,
wb_ack_o => WbAck_i,
wb_stall_o => WbStall_i,
wb_int_o => WbIrq_i,
wbslave_reg_int_count_i => s_int_counter_slv,
wbslave_reg_int_rate_o => open,
wbslave_ram_addr_i => (others => '0'),
wbslave_ram_data_o => open,
wbslave_ram_rd_i => '0',
wbslave_ram_data_i => (others => '0'),
wbslave_ram_wr_i => '0',
irq_irq0_i => s_counter0(23),
irq_irq1_i => s_counter0(23)
);
s_int_counter_slv <= std_logic_vector(resize(s_int_counter,s_int_counter_slv'length));
---------------------------------------------------------------------------------
process(clk_i)
begin
if rising_edge(clk_i) then
if Rst = '0' or s_rst_n = '0' then
s_counter0 <= (others => '0');
else
s_counter0 <= s_counter0 + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
process(clk_i)
begin
if rising_edge(clk_i) then
if Rst = '0' or s_rst_n = '0' then
s_counter1 <= (others => '0');
else
s_counter1 <= s_counter1 + 1;
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- rising edge detection
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= s_counter0(23);
if s_1 = '0' and s_counter0(23) = '1' then
s_ris_edge <= '1';
else
s_ris_edge <= '0';
end if;
end if;
end process;
----------------------------------------------------------------------------------
-- falling edge detection
process(clk_i)
begin
if rising_edge(clk_i) then
s_2 <= s_counter0(23);
if s_2 = '1' and s_counter0(23) = '0' then
s_fal_edge <= '1';
else
s_fal_edge <= '0';
end if;
end if;
end process;
--------------------------------------------------------------------------------
-- interrupt counter
process(clk_i)
begin
if rising_edge(clk_i) then
if Rst = '0' then
s_int_counter <= (others => '0');
else
if (s_ris_edge = '1' or s_fal_edge = '1') then
s_int_counter <= s_int_counter + 1;
end if;
end if;
end if;
end process;
----------------------------------------------------------------------------------
Rst <= VME_RST_n_i and Reset;
s_rst_n <= not s_rst;
---------------------------------------------------------------------------------
-- buffers
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
---------------------------------------------------------------------------------
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
-----------------------------------------------------------------------------------
--
PLL_BASE_inst : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
CLKFBOUT_MULT => 20, -- Multiply value for all CLKOUT clock outputs (1-64)
CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- (0.0-360.0).
CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- MHz).
-- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
CLKOUT0_DIVIDE => 4,
CLKOUT1_DIVIDE => 1,
CLKOUT2_DIVIDE => 1,
CLKOUT3_DIVIDE => 1,
CLKOUT4_DIVIDE => 1,
CLKOUT5_DIVIDE => 1,
-- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- Duty cycle for CLKOUT# clock output (0.01-0.99).
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKOUT3_DUTY_CYCLE => 0.500,
CLKOUT4_DUTY_CYCLE => 0.500,
CLKOUT5_DUTY_CYCLE => 0.500,
-- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
CLKOUT0_PHASE => 0.000,
CLKOUT1_PHASE => 0.000,
CLKOUT2_PHASE => 0.000,
CLKOUT3_PHASE => 0.000,
CLKOUT4_PHASE => 0.000,
CLKOUT5_PHASE => 0.000,
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "SYSTEM_SYNCHRONOUS",
DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
REF_JITTER => 0.016,-- Reference Clock Jitter in UI (0.000-0.999).
RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
)
port map (
CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
CLKOUT0 => clk_in_buf, --clk 100 MHz
CLKOUT1 => open,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
CLKIN => clk_i, -- 1-bit input: Clock input
RST => '0' -- 1-bit input: Reset input
);
cmp_clk_dmtd_buf : BUFG
port map
(O => clk_in,
I => clk_in_buf);
-- comment the next line if the PLL is used:
-- clk_in <= clk_i;
end Behavioral;
--===========================================================================
-- Architecture end
--===========================================================================
hdl/boards/svec_pts/rtl/WB_slave.vhd 0 → 100644
View file @ d4659ea1
---------------------------------------------------------------------------------------
-- Title : Wishbone slave core for Wishbone Slave port
---------------------------------------------------------------------------------------
-- File : WB_slave.vhd
-- Author : auto-generated by wbgen2 from WB_slave.wb
-- Created : Thu Aug 30 15:04:36 2012
-- Revisioned by : Davide Pedretti
-- Revision date : 30/10/2012
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE WB_slave.wb
-- and it was hand-edit since the original file was not working fine.
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wishbone_port_slave is
generic(g_width : integer := 32;
g_addr_width : integer := 9;
g_num_irq : integer := 2
);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(g_addr_width - 1 downto 0);
wb_dat_i : in std_logic_vector(g_width - 1 downto 0);
wb_dat_o : out std_logic_vector(g_width - 1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(f_div8(g_width) - 1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
wb_int_o : out std_logic;
-- Ports for RAM: Memory
wbslave_ram_addr_i : in std_logic_vector(g_addr_width - 2 downto 0);
-- Read data output
wbslave_ram_data_o : out std_logic_vector(g_width - 1 downto 0);
-- Read strobe input (active high)
wbslave_ram_rd_i : in std_logic;
-- Write data input
wbslave_ram_data_i : in std_logic_vector(g_width - 1 downto 0);
-- Write strobe (active high)
wbslave_ram_wr_i : in std_logic;
-- Port for std_logic_vector field: 'INT_COUNT' in reg: 'INT_COUNT'
wbslave_reg_int_count_i : in std_logic_vector(g_width - 1 downto 0);
-- Port for std_logic_vector field: 'INT_RATE' in reg: 'INT_RATE'
wbslave_reg_int_rate_o : out std_logic_vector(g_width - 1 downto 0);
irq_irq0_i : in std_logic;
irq_irq1_i : in std_logic
);
end wishbone_port_slave;
architecture rtl of wishbone_port_slave is
signal wbslave_ram_rddata_int : std_logic_vector(g_width - 1 downto 0);
signal wbslave_ram_rd_int : std_logic;
signal wbslave_ram_wr_int : std_logic;
signal wbslave_reg_int_rate_int : std_logic_vector(g_width - 1 downto 0);
signal wbslave_reg_int_count_int : std_logic_vector(g_width - 1 downto 0);
signal eic_idr_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_idr_write_int : std_logic;
signal eic_ier_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_ier_write_int : std_logic;
signal eic_imr_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_imr_reg_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_isr_status_reg_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_isr_clear_int : std_logic;
signal eic_isr_status_int : std_logic_vector(g_num_irq - 1 downto 0);
signal eic_isr_write_int : std_logic;
signal irq_inputs_vector_int : std_logic_vector(g_num_irq - 1 downto 0);
signal ack_sreg : std_logic_vector(9 downto 0);
signal rddata_reg : std_logic_vector(g_width - 1 downto 0);
signal wrdata_reg : std_logic_vector(g_width - 1 downto 0);
signal bwsel_reg : std_logic_vector(f_div8(g_width) - 1 downto 0);
signal rwaddr_reg : std_logic_vector(g_addr_width - 1 downto 0);
signal ack_in_progress : std_logic;
signal wr_int : std_logic;
signal rd_int : std_logic;
signal allones : std_logic_vector(g_width - 1 downto 0);
--signal allzeros : std_logic_vector(31 downto 0);
begin
-- Some internal signals assignments. For (foreseen) compatibility with other bus standards.
wrdata_reg <= wb_dat_i;
bwsel_reg <= wb_sel_i;
rd_int <= wb_cyc_i and (wb_stb_i and (not wb_we_i));
wr_int <= wb_cyc_i and (wb_stb_i and wb_we_i);
allones <= (others => '1');
-- allzeros <= (others => '0');
--
-- Main register bank access process.
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
ack_sreg(8 downto 0) <= ack_sreg(9 downto 1);
ack_sreg(9) <= '0';
if (rst_n_i = '0') then
ack_sreg <= "0000000000";
ack_in_progress <= '0';
elsif(ack_in_progress = '1') then
ack_in_progress <= not ack_sreg(0);
else
ack_in_progress <= wb_cyc_i and wb_stb_i;
ack_sreg(0) <= wb_cyc_i and wb_stb_i;
end if;
end if;
end process;
-- access bus = read only
-- access dev = write only
-- prefix = int_count
-- size = 32/64
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
wbslave_reg_int_count_int <= (others => '0');
else
wbslave_reg_int_count_int <= wbslave_reg_int_count_i;
end if;
end if;
end process;
-- access bus = read/write
-- access dev = read only
-- prefix = int_rate
-- size = 32/64
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
wbslave_reg_int_rate_int <= (others => '0');
elsif rwaddr_reg = "000000101" and wb_we_i = '1' and
(wb_cyc_i = '1') and (wb_stb_i = '1') then
wbslave_reg_int_rate_int <= wrdata_reg;
end if;
end if;
end process;
-- ier register
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
eic_ier_write_int <= '0';
eic_ier_int <= (others => '0');
elsif rwaddr_reg = "000000001" and wb_we_i = '1' and
(wb_cyc_i = '1') and (wb_stb_i = '1') then
eic_ier_write_int <= '1';
eic_ier_int <= wrdata_reg(g_num_irq - 1 downto 0);
else
eic_ier_write_int <= '0';
eic_ier_int <= (others => '0');
end if;
end if;
end process;
-- idr register
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
eic_idr_write_int <= '1';
eic_idr_int <= (others => '1');
elsif rwaddr_reg = "000000000" and wb_we_i = '1' and
(wb_cyc_i = '1') and (wb_stb_i = '1') then
eic_idr_write_int <= '1';
eic_idr_int <= wrdata_reg(g_num_irq - 1 downto 0);
else
eic_idr_write_int <= '0';
eic_idr_int <= (others => '0');
end if;
end if;
end process;
--interrupt source register
process (clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if (rst_n_i = '0') then
eic_isr_write_int <= '0';
elsif rwaddr_reg = "000000010" and wb_we_i = '0' and
(wb_cyc_i = '1') and (wb_stb_i = '1') then
eic_isr_write_int <= '1';
else
eic_isr_write_int <= '0';
end if;
end if;
end process;
process (rwaddr_reg, wbslave_reg_int_count_int, wbslave_reg_int_rate_int, eic_idr_int,
eic_ier_int, eic_imr_reg_int, eic_isr_status_reg_int, wbslave_ram_rddata_int)
begin
case rwaddr_reg(g_addr_width - 1) is
when '0' =>
case rwaddr_reg(3 downto 0) is
when "0100" =>
rddata_reg <= wbslave_reg_int_count_int;
when "0101" =>
rddata_reg <= wbslave_reg_int_rate_int;
when "0000" =>
rddata_reg <= std_logic_vector(resize(unsigned(eic_idr_int),rddata_reg'length));
when "0001" =>
rddata_reg <= std_logic_vector(resize(unsigned(eic_ier_int),rddata_reg'length));
when "0011" =>
rddata_reg <= std_logic_vector(resize(unsigned(eic_imr_int),rddata_reg'length));
when "0010" => -- irq status
rddata_reg <= std_logic_vector(resize(unsigned(eic_isr_status_int),rddata_reg'length));
when others => null;
end case;
when '1' =>
rddata_reg <= wbslave_ram_rddata_int;
when others => null;
end case;
end process;
wb_dat_o <= rddata_reg;
-- Read & write lines decoder for RAMs
process (wb_adr_i, rd_int, wr_int)
begin
if (wb_adr_i(g_addr_width - 1) = '1') then
wbslave_ram_rd_int <= rd_int;
wbslave_ram_wr_int <= wr_int;
else
wbslave_ram_wr_int <= '0';
wbslave_ram_rd_int <= '0';
end if;
end process;
-- extra code for reg/fifo/mem: Memory
-- RAM block instantiation for memory: Memory
wbslave_ram_raminst : wbgen2_dpssram
generic map (
g_data_width => g_width,
g_size => 256,
g_addr_width => g_addr_width - 1,
g_dual_clock => false,
g_use_bwsel => true
)
port map (
clk_a_i => clk_sys_i,
clk_b_i => clk_sys_i,
addr_b_i => wbslave_ram_addr_i,
addr_a_i => rwaddr_reg(g_addr_width - 2 downto 0),
data_b_o => wbslave_ram_data_o,
rd_b_i => wbslave_ram_rd_i,
data_b_i => wbslave_ram_data_i,
wr_b_i => wbslave_ram_wr_i,
bwsel_b_i => bwsel_reg,-- allones(f_div8(g_width) - 1 downto 0),
data_a_o => wbslave_ram_rddata_int,
rd_a_i => wbslave_ram_rd_int,
data_a_i => wrdata_reg,
wr_a_i => wbslave_ram_wr_int,
bwsel_a_i => wb_sel_i
);
-- INT_COUNT
-- INT_RATE
wbslave_reg_int_rate_o <= wbslave_reg_int_rate_int;
eic_irq_controller_inst : wbgen2_eic
generic map (
g_num_interrupts => g_num_irq,
g_irq00_mode => 0,
g_irq01_mode => 1,
g_irq02_mode => 0,
g_irq03_mode => 0,
g_irq04_mode => 0,
g_irq05_mode => 0,
g_irq06_mode => 0,
g_irq07_mode => 0,
g_irq08_mode => 0,
g_irq09_mode => 0,
g_irq0a_mode => 0,
g_irq0b_mode => 0,
g_irq0c_mode => 0,
g_irq0d_mode => 0,
g_irq0e_mode => 0,
g_irq0f_mode => 0,
g_irq10_mode => 0,
g_irq11_mode => 0,
g_irq12_mode => 0,
g_irq13_mode => 0,
g_irq14_mode => 0,
g_irq15_mode => 0,
g_irq16_mode => 0,
g_irq17_mode => 0,
g_irq18_mode => 0,
g_irq19_mode => 0,
g_irq1a_mode => 0,
g_irq1b_mode => 0,
g_irq1c_mode => 0,
g_irq1d_mode => 0,
g_irq1e_mode => 0,
g_irq1f_mode => 0
)
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
irq_i => irq_inputs_vector_int,
-- irq_ack_o => eic_irq_ack_int,
reg_imr_o => eic_imr_int,
reg_ier_i => eic_ier_int,
reg_ier_wr_stb_i => eic_ier_write_int,
reg_idr_i => eic_idr_int,
reg_idr_wr_stb_i => eic_idr_write_int,
reg_isr_o => eic_isr_status_int,
--reg_isr_i => eic_isr_clear_int,
reg_isr_wr_stb_i => eic_isr_clear_int,
wb_irq_o => wb_int_o
);
irq_inputs_vector_int(0) <= irq_irq0_i;
irq_inputs_vector_int(1) <= irq_irq1_i;
rwaddr_reg <= wb_adr_i;
wb_stall_o <= (not ack_sreg(0)) and (wb_stb_i and wb_cyc_i);
-- ACK signal generation. Just pass the LSB of ACK counter.
eic_isr_clear_int <= ack_sreg(0) and eic_isr_write_int;
wb_ack_o <= ack_sreg(0);
end rtl;
hdl/boards/svec_pts/rtl/generic_dpram.vhd 0 → 100644
View file @ d4659ea1
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-16
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-- 2012-03-13 1.1 wterpstra Added initial value as array
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 1024;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram;
architecture syn of generic_dpram is
component generic_dpram_sameclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram_dualclock
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string;
g_init_file : string;
g_init_value : t_generic_ram_init;
g_fail_if_file_not_found : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
gen_single_clk : if(g_dual_clock = false) generate
U_RAM_SC: generic_dpram_sameclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clk_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_single_clk;
gen_dual_clk : if(g_dual_clock = true) generate
U_RAM_DC: generic_dpram_dualclock
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_with_byte_enable,
g_addr_conflict_resolution => g_addr_conflict_resolution,
g_init_file => g_init_file,
g_init_value => g_init_value,
g_fail_if_file_not_found => g_fail_if_file_not_found)
port map (
rst_n_i => rst_n_i,
clka_i => clka_i,
bwea_i => bwea_i,
wea_i => wea_i,
aa_i => aa_i,
da_i => da_i,
qa_o => qa_o,
clkb_i => clkb_i,
bweb_i => bweb_i,
web_i => web_i,
ab_i => ab_i,
db_i => db_i,
qb_o => qb_o);
end generate gen_dual_clk;
end syn;
hdl/boards/svec_pts/rtl/generic_dpram_dualclock.vhd 0 → 100644
View file @ d4659ea1
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_dualclock is
generic (
-- standard parameters
g_data_width : natural := 32;
g_size : natural := 16384;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_fail_if_file_not_found : boolean := true
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_dualclock;
architecture syn of generic_dpram_dualclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
if g_init_value'length > 0 then
return g_init_value;
else
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end if;
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal clka_int : std_logic;
signal clkb_int : std_logic;
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
process (clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
process (clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_b(i) = '1' then
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8)
:= db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
process(clka_i)
begin
if rising_edge(clka_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
qb_o <= ram(to_integer(unsigned(ab_i)));
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clka_i)
begin
if rising_edge(clka_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
end if;
end process;
process(clkb_i)
begin
if rising_edge(clkb_i) then
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
hdl/boards/svec_pts/rtl/generic_dpram_sameclock.vhd 0 → 100644
View file @ d4659ea1
-------------------------------------------------------------------------------
-- Title : Parametrizable dual-port synchronous RAM (Xilinx version)
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : generic_dpram_sameclock.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-03-28
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: True dual-port synchronous RAM for Xilinx FPGAs with:
-- - configurable address and data bus width
-- - byte-addressing mode (data bus width restricted to multiple of 8 bits)
-- Todo:
-- - loading initial contents from file
-- - add support for read-first/write-first address conflict resulution (only
-- supported by Xilinx in VHDL templates)
-------------------------------------------------------------------------------
-- Copyright (c) 2011 CERN
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;
library work;
use work.genram_pkg.all;
use work.memory_loader_pkg.all;
entity generic_dpram_sameclock is
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_fail_if_file_not_found : boolean
);
port (
rst_n_i : in std_logic := '1'; -- synchronous reset, active LO
-- Port A
clk_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
-- Port B
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0)
);
end generic_dpram_sameclock;
architecture syn of generic_dpram_sameclock is
constant c_num_bytes : integer := (g_data_width+7)/8;
type t_ram_type is array(0 to g_size-1) of std_logic_vector(g_data_width-1 downto 0);
function f_memarray_to_ramtype(arr : t_meminit_array) return t_ram_type is
variable tmp : t_ram_type;
variable n, pos : integer;
begin
pos := 0;
while(pos < g_size)loop
n := 0;
-- avoid ISE loop iteration limit
while (pos < g_size and n < 4096) loop
for i in 0 to g_data_width-1 loop
tmp(pos)(i) := arr(pos, i);
end loop; -- i
n := n+1;
pos := pos + 1;
end loop;
end loop;
return tmp;
end f_memarray_to_ramtype;
function f_file_contents return t_meminit_array is
begin
if g_init_value'length > 0 then
return g_init_value;
else
return f_load_mem_from_file(g_init_file, g_size, g_data_width, g_fail_if_file_not_found);
end if;
end f_file_contents;
shared variable ram : t_ram_type := f_memarray_to_ramtype(f_file_contents);
signal s_we_a : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_a : std_logic_vector(g_data_width-1 downto 0);
signal s_we_b : std_logic_vector(c_num_bytes-1 downto 0);
signal s_ram_in_b : std_logic_vector(g_data_width-1 downto 0);
signal wea_rep, web_rep : std_logic_vector(c_num_bytes-1 downto 0);
begin
wea_rep <= (others => wea_i);
web_rep <= (others => web_i);
s_we_a <= bwea_i and wea_rep;
s_we_b <= bweb_i and web_rep;
gen_with_byte_enable_readfirst : if(g_with_byte_enable = true and g_addr_conflict_resolution = "read_first") generate
process (clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
qb_o <= ram(to_integer(unsigned(ab_i)));
for i in 0 to c_num_bytes-1 loop
if s_we_a(i) = '1' then
ram(to_integer(unsigned(aa_i)))((i+1)*8-1 downto i*8) := da_i((i+1)*8-1 downto i*8);
end if;
if(s_we_b(i) = '1') then
ram(to_integer(unsigned(ab_i)))((i+1)*8-1 downto i*8) := db_i((i+1)*8-1 downto i*8);
end if;
end loop;
end if;
end process;
end generate gen_with_byte_enable_readfirst;
gen_without_byte_enable_readfirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "read_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
qa_o <= ram(to_integer(unsigned(aa_i)));
qb_o <= ram(to_integer(unsigned(ab_i)));
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
end if;
end if;
end process;
end generate gen_without_byte_enable_readfirst;
gen_without_byte_enable_writefirst : if(g_with_byte_enable = false and g_addr_conflict_resolution = "write_first") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
qa_o <= da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
qb_o <= db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_writefirst;
gen_without_byte_enable_nochange : if(g_with_byte_enable = false and g_addr_conflict_resolution = "no_change") generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(wea_i = '1') then
ram(to_integer(unsigned(aa_i))) := da_i;
else
qa_o <= ram(to_integer(unsigned(aa_i)));
end if;
if(web_i = '1') then
ram(to_integer(unsigned(ab_i))) := db_i;
else
qb_o <= ram(to_integer(unsigned(ab_i)));
end if;
end if;
end process;
end generate gen_without_byte_enable_nochange;
end syn;
hdl/boards/svec_pts/rtl/genram_pkg.vhd 0 → 100644
View file @ d4659ea1
-------------------------------------------------------------------------------
-- Title : Main package file
-- Project : Generics RAMs and FIFOs collection
-------------------------------------------------------------------------------
-- File : genram_pkg.vhd
-- Author : Tomasz Wlostowski
-- Company : CERN BE-CO-HT
-- Created : 2011-01-25
-- Last update: 2012-01-24
-- Platform :
-- Standard : VHDL'93
-------------------------------------------------------------------------------
--
-- Copyright (c) 2011 CERN
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
-- Revisions :
-- Date Version Author Description
-- 2011-01-25 1.0 twlostow Created
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
package genram_pkg is
function f_log2_size (A : natural) return natural;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector;
type t_generic_ram_init is array (integer range <>, integer range <>) of std_logic;
-- Generic RAM initialized with nothing.
constant c_generic_ram_nothing : t_generic_ram_init(-1 downto 0, -1 downto 0) :=
(others => (others => '0'));
-- Single-port synchronous RAM
component generic_spram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_init_file : string := "";
g_addr_conflict_resolution : string := "read_first") ;
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
bwe_i : in std_logic_vector((g_data_width+7)/8-1 downto 0):= f_gen_dummy_vec('1', (g_data_width+7)/8);
we_i : in std_logic;
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
d_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
q_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean := false;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_init_value : t_generic_ram_init := c_generic_ram_nothing;
g_dual_clock : boolean := true);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
wea_i : in std_logic := '0';
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector((g_data_width+7)/8-1 downto 0) := f_gen_dummy_vec('1', (g_data_width+7)/8);
web_i : in std_logic := '0';
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0) := f_gen_dummy_vec('0', g_data_width);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
component generic_async_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_rd_empty : boolean := true;
g_with_rd_full : boolean := false;
g_with_rd_almost_empty : boolean := false;
g_with_rd_almost_full : boolean := false;
g_with_rd_count : boolean := false;
g_with_wr_empty : boolean := false;
g_with_wr_full : boolean := true;
g_with_wr_almost_empty : boolean := false;
g_with_wr_almost_full : boolean := false;
g_with_wr_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_wr_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_almost_empty_o : out std_logic;
wr_almost_full_o : out std_logic;
wr_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0);
clk_rd_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_almost_empty_o : out std_logic;
rd_almost_full_o : out std_logic;
rd_count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_sync_fifo
generic (
g_data_width : natural;
g_size : natural;
g_show_ahead : boolean := false;
g_with_empty : boolean := true;
g_with_full : boolean := true;
g_with_almost_empty : boolean := false;
g_with_almost_full : boolean := false;
g_with_count : boolean := false;
g_almost_empty_threshold : integer := 0;
g_almost_full_threshold : integer := 0);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
empty_o : out std_logic;
full_o : out std_logic;
almost_empty_o : out std_logic;
almost_full_o : out std_logic;
count_o : out std_logic_vector(f_log2_size(g_size)-1 downto 0));
end component;
component generic_shiftreg_fifo
generic (
g_data_width : integer;
g_size : integer);
port (
rst_n_i : in std_logic := '1';
clk_i : in std_logic;
d_i : in std_logic_vector(g_data_width-1 downto 0);
we_i : in std_logic;
q_o : out std_logic_vector(g_data_width-1 downto 0);
rd_i : in std_logic;
full_o : out std_logic;
almost_full_o : out std_logic;
q_valid_o : out std_logic
);
end component;
end genram_pkg;
package body genram_pkg is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I >= A) then
return(I);
end if;
end loop;
return(63);
end function f_log2_size;
function f_gen_dummy_vec (val : std_logic; size : natural) return std_logic_vector is
variable tmp : std_logic_vector(size-1 downto 0);
begin
for i in 0 to size-1 loop
tmp(i) := val;
end loop; -- i
return tmp;
end f_gen_dummy_vec;
end genram_pkg;
hdl/boards/svec_pts/rtl/memory_loader_pkg.vhd 0 → 100644
View file @ d4659ea1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library std;
use std.textio.all;
library work;
use work.genram_pkg.all;
package memory_loader_pkg is
subtype t_meminit_array is t_generic_ram_init;
function f_hexchar_to_slv (c : character) return std_logic_vector;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector;
function f_get_token(s : string; n : integer) return string;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array;
end memory_loader_pkg;
package body memory_loader_pkg is
function f_hexchar_to_slv (c : character) return std_logic_vector is
variable t : std_logic_vector(3 downto 0);
begin
case c is
when '0' => t := x"0";
when '1' => t := x"1";
when '2' => t := x"2";
when '3' => t := x"3";
when '4' => t := x"4";
when '5' => t := x"5";
when '6' => t := x"6";
when '7' => t := x"7";
when '8' => t := x"8";
when '9' => t := x"9";
when 'a' => t := x"a";
when 'A' => t := x"a";
when 'b' => t := x"b";
when 'B' => t := x"b";
when 'c' => t := x"c";
when 'C' => t := x"c";
when 'd' => t := x"d";
when 'D' => t := x"d";
when 'e' => t := x"e";
when 'E' => t := x"e";
when 'f' => t := x"f";
when 'F' => t := x"f";
when others =>
report "f_hexchar_to_slv(): unrecognized character '" &c&" in hex text string" severity failure;
end case;
return t;
end f_hexchar_to_slv;
function f_hexstring_to_slv (s : string; n_digits : integer) return std_logic_vector is
variable tmp : std_logic_vector(255 downto 0) := (others => '0');
begin
if s'length > tmp'length then
report "f_hexstring_to_slv(): string length exceeds the limit" severity failure;
end if;
for i in 0 to s'length-1 loop
tmp(4 * (s'length - i) - 1 downto 4 * (s'length - 1 - i)) := f_hexchar_to_slv(s(i+1));
end loop; -- i
return tmp(n_digits * 4 - 1 downto 0);
end f_hexstring_to_slv;
function f_get_token(s : string; n : integer) return string is
variable cur_pos : integer;
variable tmp : string (1 to 128);
variable cur_token : integer;
variable tmp_pos : integer;
begin
cur_pos := 1;
cur_token := 1;
tmp_pos := 1;
loop
if(cur_pos >= s'length) then
return "";
end if;
while cur_pos <= s'length and (s(cur_pos) = ' ' or s(cur_pos) = character'val(9) or s(cur_pos) = character'val(0)) loop
cur_pos := cur_pos + 1;
end loop;
if(cur_pos >= s'length) then
return "";
end if;
while(cur_pos <= s'length and s(cur_pos) /= ' ' and s(cur_pos) /= character'val(9) and s(cur_pos) /= character'val(0)) loop
if(cur_token = n) then
tmp(tmp_pos) := s(cur_pos);
tmp_pos := tmp_pos + 1;
end if;
cur_pos := cur_pos + 1;
end loop;
if(cur_token = n) then
return tmp(1 to tmp_pos-1);
end if;
cur_token := cur_token + 1;
if(cur_pos >= s'length) then
return "";
end if;
end loop;
return "";
end f_get_token;
function f_load_mem_from_file
(file_name : string;
mem_size : integer;
mem_width : integer;
fail_if_notfound : boolean)
return t_meminit_array is
file f_in : text;
variable l : line;
variable ls : string(1 to 128);
variable cmd : string(1 to 128);
variable line_len : integer;
variable status : file_open_status;
variable mem : t_meminit_array(0 to mem_size-1, mem_width-1 downto 0);
variable i : integer;
variable c : character;
variable good : boolean;
variable addr : integer;
variable data_tmp : unsigned(mem_width-1 downto 0);
variable data_int : integer;
begin
if(file_name = "") then
mem := (others => (others => '0'));
return mem;
end if;
file_open(status, f_in, file_name, read_mode);
if(status /= open_ok) then
if(fail_if_notfound) then
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity failure;
else
report "f_load_mem_from_file(): can't open file '"&file_name&"'" severity warning;
end if;
end if;
while true loop
i := 0;
while (i < 4096) loop
-- stupid ISE restricts the loop length
readline(f_in, l);
line_len := 0;
loop
read(l, ls(line_len+1), good);
exit when good = false;
line_len := line_len + 1;
end loop;
if(line_len /= 0 and f_get_token(ls, 1) = "write") then
addr := to_integer(unsigned(f_hexstring_to_slv(f_get_token(ls, 2), 8)));
data_tmp := resize(unsigned(f_hexstring_to_slv(f_get_token(ls, 3), 8)), mem_width);
data_int := to_integer(data_tmp);
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
for i in 0 to mem_width-1 loop
mem(addr, i) := std_logic(data_tmp(i));
end loop; -- i in 0 to mem_width-1
-- report "addr: " & integer'image(addr) & " data: " & integer'image(data_int);
end if;
if endfile(f_in) then
file_close(f_in);
return mem;
end if;
i := i+1;
end loop;
end loop;
return mem;
end f_load_mem_from_file;
end memory_loader_pkg;
hdl/boards/svec_pts/rtl/wbgen2_dpssram.vhd 0 → 100644
View file @ d4659ea1
library ieee;
use ieee.std_logic_1164.all;
--use work.genram_pkg.all;
--use work.common_components.all;
--library wbgen2;
use work.wbgen2_pkg.all;
entity wbgen2_dpssram is
generic (
g_data_width : natural := 32;
g_size : natural := 1024;
g_addr_width : natural := 10;
g_dual_clock : boolean := false;
g_use_bwsel : boolean := true);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic
);
end wbgen2_dpssram;
architecture syn of wbgen2_dpssram is
function f_log2_size (A : natural) return natural is
begin
for I in 1 to 64 loop -- Works for up to 64 bits
if (2**I > A) then
return(I-1);
end if;
end loop;
return(63);
end function f_log2_size;
component generic_dpram
generic (
g_data_width : natural;
g_size : natural;
g_with_byte_enable : boolean;
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := "";
g_dual_clock : boolean);
port (
rst_n_i : in std_logic := '1';
clka_i : in std_logic;
bwea_i : in std_logic_vector(g_data_width/8-1 downto 0);
wea_i : in std_logic;
aa_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
da_i : in std_logic_vector(g_data_width-1 downto 0);
qa_o : out std_logic_vector(g_data_width-1 downto 0);
clkb_i : in std_logic;
bweb_i : in std_logic_vector(g_data_width/8-1 downto 0);
web_i : in std_logic;
ab_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
db_i : in std_logic_vector(g_data_width-1 downto 0);
qb_o : out std_logic_vector(g_data_width-1 downto 0));
end component;
begin
wrapped_dpram: generic_dpram
generic map (
g_data_width => g_data_width,
g_size => g_size,
g_with_byte_enable => g_use_bwsel,
g_dual_clock => g_dual_clock)
port map (
rst_n_i => '1',
clka_i => clk_a_i,
bwea_i => bwsel_a_i,
wea_i => wr_a_i,
aa_i => addr_a_i,
da_i => data_a_i,
qa_o => data_a_o,
clkb_i => clk_b_i,
bweb_i => bwsel_b_i,
web_i => wr_b_i,
ab_i => addr_b_i,
db_i => data_b_i,
qb_o => data_b_o);
end syn;
hdl/boards/svec_pts/rtl/wbgen2_eic.vhd 0 → 100644
View file @ d4659ea1
---------------------------------------------------------------------------------------
-- Title : Interrupt request controller
---------------------------------------------------------------------------------------
-- File : wbgen2_eic.vhd
-- Author : auto-generated by wbgen2 from WB_slave.wb
-- Created : Thu Aug 30 15:04:36 2012
-- Revisioned by : Davide Pedretti
-- Revision date : 30/10/2012
---------------------------------------------------------------------------------------
-- THIS FILE WAS GENERATED BY wbgen2 FROM SOURCE FILE WB_slave.wb
-- and it was hand-edit since the original file was not working fine.
---------------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wbgen2_pkg.all;
entity wbgen2_eic is
generic (
g_num_interrupts : natural := 1;
g_irq00_mode : integer := 0;
g_irq01_mode : integer := 0;
g_irq02_mode : integer := 0;
g_irq03_mode : integer := 0;
g_irq04_mode : integer := 0;
g_irq05_mode : integer := 0;
g_irq06_mode : integer := 0;
g_irq07_mode : integer := 0;
g_irq08_mode : integer := 0;
g_irq09_mode : integer := 0;
g_irq0a_mode : integer := 0;
g_irq0b_mode : integer := 0;
g_irq0c_mode : integer := 0;
g_irq0d_mode : integer := 0;
g_irq0e_mode : integer := 0;
g_irq0f_mode : integer := 0;
g_irq10_mode : integer := 0;
g_irq11_mode : integer := 0;
g_irq12_mode : integer := 0;
g_irq13_mode : integer := 0;
g_irq14_mode : integer := 0;
g_irq15_mode : integer := 0;
g_irq16_mode : integer := 0;
g_irq17_mode : integer := 0;
g_irq18_mode : integer := 0;
g_irq19_mode : integer := 0;
g_irq1a_mode : integer := 0;
g_irq1b_mode : integer := 0;
g_irq1c_mode : integer := 0;
g_irq1d_mode : integer := 0;
g_irq1e_mode : integer := 0;
g_irq1f_mode : integer := 0
);
port(
rst_n_i : in std_logic; -- reset & system clock, as always :)
clk_i : in std_logic;
-- raw interrupt inputs
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt acknowledge signal, used for level-active interrupts to
-- indicate that the interrupt has been handled
-- irq_ack_o: out std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt mask regsiter (slv/bus read-only)
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
-- interrupt enable/disable registers (slv/bus pass-through)
reg_ier_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_wr_stb_i : in std_logic;
reg_idr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_idr_wr_stb_i : in std_logic;
-- interrupt status register (slv/bus write with LOAD_EXT)
reg_isr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
--reg_isr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_wr_stb_i : in std_logic;
-- multiplexed wishbone irq output
wb_irq_o : out std_logic
);
end wbgen2_eic;
architecture syn of wbgen2_eic is
subtype t_irq_mode is integer;
type t_irq_mode_vec is array (0 to 31) of t_irq_mode;
constant c_IRQ_MODE_RISING_EDGE : t_irq_mode := 0;
constant c_IRQ_MODE_FALLING_EDGE : t_irq_mode := 1;
constant c_IRQ_MODE_LEVEL_0 : t_irq_mode := 2;
constant c_IRQ_MODE_LEVEL_1 : t_irq_mode := 3;
signal irq_mode : t_irq_mode_vec;
signal irq_mask : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_mask_en : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_mask_de : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_status_en : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_pending : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_pending_o : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d0 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d1 : std_logic_vector(g_num_interrupts-1 downto 0);
signal irq_i_d2 : std_logic_vector(g_num_interrupts-1 downto 0);
begin -- syn
irq_mode(0) <= g_irq00_mode;
irq_mode(1) <= g_irq01_mode;
irq_mode(2) <= g_irq02_mode;
irq_mode(3) <= g_irq03_mode;
irq_mode(4) <= g_irq04_mode;
irq_mode(5) <= g_irq05_mode;
irq_mode(6) <= g_irq06_mode;
irq_mode(7) <= g_irq07_mode;
irq_mode(8) <= g_irq08_mode;
irq_mode(9) <= g_irq09_mode;
irq_mode(10) <= g_irq0a_mode;
irq_mode(11) <= g_irq0b_mode;
irq_mode(12) <= g_irq0c_mode;
irq_mode(13) <= g_irq0d_mode;
irq_mode(14) <= g_irq0e_mode;
irq_mode(15) <= g_irq0f_mode;
irq_mode(16) <= g_irq10_mode;
irq_mode(17) <= g_irq11_mode;
irq_mode(18) <= g_irq12_mode;
irq_mode(19) <= g_irq13_mode;
irq_mode(20) <= g_irq14_mode;
irq_mode(21) <= g_irq15_mode;
irq_mode(22) <= g_irq16_mode;
irq_mode(23) <= g_irq17_mode;
irq_mode(24) <= g_irq18_mode;
irq_mode(25) <= g_irq19_mode;
irq_mode(26) <= g_irq1a_mode;
irq_mode(27) <= g_irq1b_mode;
irq_mode(28) <= g_irq1c_mode;
irq_mode(29) <= g_irq1d_mode;
irq_mode(30) <= g_irq1e_mode;
irq_mode(31) <= g_irq1f_mode;
genirq : for i in 0 to g_num_interrupts-1 generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
irq_i_d0(i) <= '0';
irq_i_d1(i) <= '0';
irq_i_d2(i) <= '0';
else
irq_i_d0(i) <= irq_i(i);
irq_i_d1(i) <= irq_i_d0(i);
irq_i_d2(i) <= irq_i_d1(i);
end if;
end if;
end process;
end generate;
genirq_pending : for i in 0 to g_num_interrupts-1 generate
process(irq_mode,irq_i_d1,irq_i_d2)
begin
case irq_mode(i) is
when c_IRQ_MODE_LEVEL_0 => irq_pending(i) <= not irq_i_d2(i) and (irq_mask(i));
when c_IRQ_MODE_LEVEL_1 => irq_pending(i) <= irq_i_d2(i) and (irq_mask(i));
when c_IRQ_MODE_RISING_EDGE => irq_pending(i) <= (not irq_i_d2(i)) and irq_i_d1(i) and (irq_mask(i));
when c_IRQ_MODE_FALLING_EDGE => irq_pending(i) <= (not irq_i_d1(i)) and irq_i_d2(i) and (irq_mask(i));
when others => null;
end case;
end process;
end generate;
genirq_pending_o : for i in 0 to g_num_interrupts-1 generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
irq_pending_o(i) <= '0';
elsif irq_status_en(i) = '1' then
irq_pending_o(i) <= irq_pending(i);
end if;
end if;
end process;
end generate;
genier : for i in 0 to g_num_interrupts-1 generate
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0') then
irq_mask(i) <= '0';
elsif(irq_mask_en(i) = '1') then
irq_mask(i) <= '1';
elsif(irq_mask_de(i) = '1') then
irq_mask(i) <= '0';
end if;
end if;
end process;
end generate;
gen1 : for i in 0 to g_num_interrupts-1 generate
irq_mask_en(i) <= reg_ier_wr_stb_i and reg_ier_i(i);
end generate;
gen2 : for i in 0 to g_num_interrupts-1 generate
irq_mask_de(i) <= reg_idr_wr_stb_i and reg_idr_i(i);
end generate;
gen3 : for i in 0 to g_num_interrupts-1 generate
irq_status_en(i) <= reg_isr_wr_stb_i or irq_pending(i);
end generate;
-- generation of wb_irq_o
-- no new interrupt request until the VME Master reads the source;
-- it will work like a RORA
process(clk_i)
begin
if rising_edge(clk_i) then
if(rst_n_i = '0' or reg_isr_wr_stb_i = '1') then
wb_irq_o <= '0';
elsif(irq_pending_o = std_logic_vector(to_unsigned(0, g_num_interrupts))) then
wb_irq_o <= '0';
else
wb_irq_o <= '1';
end if;
end if;
end process;
reg_imr_o <= irq_mask;
reg_isr_o <= irq_pending_o;
end syn;
hdl/boards/svec_pts/rtl/wbgen2_pkg.vhd 0 → 100644
View file @ d4659ea1
library ieee;
use ieee.std_logic_1164.all;
package wbgen2_pkg is
function f_div8 (width : integer) return integer;
component wbgen2_dpssram
generic (
g_data_width : natural;
g_size : natural;
g_addr_width : natural;
g_dual_clock : boolean;
g_use_bwsel : boolean);
port (
clk_a_i : in std_logic;
clk_b_i : in std_logic;
addr_a_i : in std_logic_vector(g_addr_width-1 downto 0);
addr_b_i : in std_logic_vector(g_addr_width-1 downto 0);
data_a_i : in std_logic_vector(g_data_width-1 downto 0);
data_b_i : in std_logic_vector(g_data_width-1 downto 0);
data_a_o : out std_logic_vector(g_data_width-1 downto 0);
data_b_o : out std_logic_vector(g_data_width-1 downto 0);
bwsel_a_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
bwsel_b_i : in std_logic_vector((g_data_width+7)/8-1 downto 0);
rd_a_i : in std_logic;
rd_b_i : in std_logic;
wr_a_i : in std_logic;
wr_b_i : in std_logic);
end component;
component wbgen2_eic
generic (
g_num_interrupts : natural;
g_irq00_mode : integer;
g_irq01_mode : integer;
g_irq02_mode : integer;
g_irq03_mode : integer;
g_irq04_mode : integer;
g_irq05_mode : integer;
g_irq06_mode : integer;
g_irq07_mode : integer;
g_irq08_mode : integer;
g_irq09_mode : integer;
g_irq0a_mode : integer;
g_irq0b_mode : integer;
g_irq0c_mode : integer;
g_irq0d_mode : integer;
g_irq0e_mode : integer;
g_irq0f_mode : integer;
g_irq10_mode : integer;
g_irq11_mode : integer;
g_irq12_mode : integer;
g_irq13_mode : integer;
g_irq14_mode : integer;
g_irq15_mode : integer;
g_irq16_mode : integer;
g_irq17_mode : integer;
g_irq18_mode : integer;
g_irq19_mode : integer;
g_irq1a_mode : integer;
g_irq1b_mode : integer;
g_irq1c_mode : integer;
g_irq1d_mode : integer;
g_irq1e_mode : integer;
g_irq1f_mode : integer);
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
irq_i : in std_logic_vector(g_num_interrupts-1 downto 0);
-- irq_ack_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_imr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_ier_wr_stb_i : in std_logic;
reg_idr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_idr_wr_stb_i : in std_logic;
reg_isr_o : out std_logic_vector(g_num_interrupts-1 downto 0);
--reg_isr_i : in std_logic_vector(g_num_interrupts-1 downto 0);
reg_isr_wr_stb_i : in std_logic;
wb_irq_o : out std_logic);
end component;
component wbgen2_fifo_async
generic (
g_size : integer;
g_width : integer;
g_usedw_size : integer);
port (
rd_clk_i : in std_logic;
rd_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
wr_clk_i : in std_logic;
wr_req_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
end component;
component wbgen2_fifo_sync
generic (
g_width : integer;
g_size : integer;
g_usedw_size : integer);
port (
clk_i : in std_logic;
wr_data_i : in std_logic_vector(g_width-1 downto 0);
wr_req_i : in std_logic;
rd_data_o : out std_logic_vector(g_width-1 downto 0);
rd_req_i : in std_logic;
wr_empty_o : out std_logic;
wr_full_o : out std_logic;
wr_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0);
rd_empty_o : out std_logic;
rd_full_o : out std_logic;
rd_usedw_o : out std_logic_vector(g_usedw_size -1 downto 0));
end component;
end wbgen2_pkg;
package body wbgen2_pkg is
function f_div8 (width : integer) return integer is
begin
for I in 1 to 8 loop
if (8*I >= width) then
return(I);
end if;
end loop;
end function f_div8;
end wbgen2_pkg;
hdl/boards/svec_pts/rtl/wishbone_pkg.vhd 0 → 100755
View file @ d4659ea1
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
library work;
package wishbone_pkg is
constant c_wishbone_address_width : integer := 64;
constant c_wishbone_data_width : integer := 32;
subtype t_wishbone_address is
std_logic_vector(c_wishbone_address_width-1 downto 0);
subtype t_wishbone_data is
std_logic_vector(c_wishbone_data_width-1 downto 0);
subtype t_wishbone_byte_select is
std_logic_vector((c_wishbone_data_width/8)-1 downto 0);
subtype t_wishbone_cycle_type is
std_logic_vector(2 downto 0);
subtype t_wishbone_burst_type is
std_logic_vector(1 downto 0);
type t_wishbone_interface_mode is (CLASSIC, PIPELINED);
type t_wishbone_address_granularity is (BYTE, WORD);
type t_wishbone_master_out is record
cyc : std_logic;
stb : std_logic;
adr : t_wishbone_address;
sel : t_wishbone_byte_select;
we : std_logic;
dat : t_wishbone_data;
end record t_wishbone_master_out;
subtype t_wishbone_slave_in is t_wishbone_master_out;
type t_wishbone_slave_out is record
ack : std_logic;
err : std_logic;
rty : std_logic;
stall : std_logic;
dat : t_wishbone_data;
end record t_wishbone_slave_out;
subtype t_wishbone_master_in is t_wishbone_slave_out;
subtype t_wishbone_device_descriptor is std_logic_vector(255 downto 0);
type t_wishbone_address_array is array(integer range <>) of t_wishbone_address;
type t_wishbone_master_out_array is array (natural range <>) of t_wishbone_master_out;
type t_wishbone_slave_out_array is array (natural range <>) of t_wishbone_slave_out;
type t_wishbone_master_in_array is array (natural range <>) of t_wishbone_master_in;
type t_wishbone_slave_in_array is array (natural range <>) of t_wishbone_slave_in;
constant cc_dummy_address : std_logic_vector(c_wishbone_address_width-1 downto 0):=
(others => 'X');
constant cc_dummy_data : std_logic_vector(c_wishbone_data_width-1 downto 0) :=
(others => 'X');
constant cc_dummy_sel : std_logic_vector(c_wishbone_data_width/8-1 downto 0) :=
(others => 'X');
constant cc_dummy_slave_in : t_wishbone_slave_in :=
('X', 'X', cc_dummy_address, cc_dummy_sel, 'X', cc_dummy_data);
constant cc_dummy_slave_out : t_wishbone_slave_out :=
('X', 'X', 'X', 'X', cc_dummy_data);
------------------------------------------------------------------------------
-- Components declaration
-------------------------------------------------------------------------------
component wb_slave_adapter
generic (
g_master_use_struct : boolean;
g_master_mode : t_wishbone_interface_mode;
g_master_granularity : t_wishbone_address_granularity;
g_slave_use_struct : boolean;
g_slave_mode : t_wishbone_interface_mode;
g_slave_granularity : t_wishbone_address_granularity);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
sl_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0) := cc_dummy_address;
sl_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
sl_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0) := cc_dummy_sel;
sl_cyc_i : in std_logic := '0';
sl_stb_i : in std_logic := '0';
sl_we_i : in std_logic := '0';
sl_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
sl_err_o : out std_logic;
sl_rty_o : out std_logic;
sl_ack_o : out std_logic;
sl_stall_o : out std_logic;
sl_int_o : out std_logic;
slave_i : in t_wishbone_slave_in := cc_dummy_slave_in;
slave_o : out t_wishbone_slave_out;
ma_adr_o : out std_logic_vector(c_wishbone_address_width-1 downto 0);
ma_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
ma_sel_o : out std_logic_vector(c_wishbone_data_width/8-1 downto 0);
ma_cyc_o : out std_logic;
ma_stb_o : out std_logic;
ma_we_o : out std_logic;
ma_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0) := cc_dummy_data;
ma_err_i : in std_logic := '0';
ma_rty_i : in std_logic := '0';
ma_ack_i : in std_logic := '0';
ma_stall_i : in std_logic := '0';
ma_int_i : in std_logic := '0';
master_i : in t_wishbone_master_in := cc_dummy_slave_out;
master_o : out t_wishbone_master_out);
end component;
component wb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
wb_adr_o : out std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_stb_o : out std_logic;
wb_we_o : out std_logic;
wb_sel_o : out std_logic_vector(3 downto 0);
wb_cyc_o : out std_logic;
wb_dat_i : in std_logic_vector (c_wishbone_data_width-1 downto 0);
wb_ack_i : in std_logic;
wb_stall_i : in std_logic := '0');
end component;
component xwb_async_bridge
generic (
g_simulation : integer;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_cpu_address_width : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
cpu_cs_n_i : in std_logic;
cpu_wr_n_i : in std_logic;
cpu_rd_n_i : in std_logic;
cpu_bs_n_i : in std_logic_vector(3 downto 0);
cpu_addr_i : in std_logic_vector(g_cpu_address_width-1 downto 0);
cpu_data_b : inout std_logic_vector(31 downto 0);
cpu_nwait_o : out std_logic;
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in);
end component;
component xwb_bus_fanout
generic (
g_num_outputs : natural;
g_bits_per_slave : integer;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_slave_interface_mode : t_wishbone_interface_mode := CLASSIC);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
master_i : in t_wishbone_master_in_array(0 to g_num_outputs-1);
master_o : out t_wishbone_master_out_array(0 to g_num_outputs-1));
end component;
component xwb_crossbar
generic (
g_num_masters : integer;
g_num_slaves : integer;
g_registered : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in_array(g_num_masters-1 downto 0);
slave_o : out t_wishbone_slave_out_array(g_num_masters-1 downto 0);
master_i : in t_wishbone_master_in_array(g_num_slaves-1 downto 0);
master_o : out t_wishbone_master_out_array(g_num_slaves-1 downto 0);
cfg_address_i : in t_wishbone_address_array(g_num_slaves-1 downto 0);
cfg_mask_i : in t_wishbone_address_array(g_num_slaves-1 downto 0));
end component;
component xwb_dpram
generic (
g_size : natural;
g_init_file : string := "";
g_must_have_init_file : boolean := true;
g_slave1_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave2_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_slave1_granularity : t_wishbone_address_granularity := WORD;
g_slave2_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out;
slave2_i : in t_wishbone_slave_in;
slave2_o : out t_wishbone_slave_out);
end component;
component wb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean := false);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(7 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component xwb_gpio_port
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_pins : natural range 1 to 256;
g_with_builtin_tristates : boolean);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
gpio_b : inout std_logic_vector(g_num_pins-1 downto 0);
gpio_out_o : out std_logic_vector(g_num_pins-1 downto 0);
gpio_in_i : in std_logic_vector(g_num_pins-1 downto 0);
gpio_oen_o : out std_logic_vector(g_num_pins-1 downto 0));
end component;
component wb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_i2c_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
scl_pad_i : in std_logic;
scl_pad_o : out std_logic;
scl_padoen_o : out std_logic;
sda_pad_i : in std_logic;
sda_pad_o : out std_logic;
sda_padoen_o : out std_logic);
end component;
component xwb_lm32
generic (
g_profile : string);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
irq_i : in std_logic_vector(31 downto 0);
dwb_o : out t_wishbone_master_out;
dwb_i : in t_wishbone_master_in;
iwb_o : out t_wishbone_master_out;
iwb_i : in t_wishbone_master_in);
end component;
component wb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "1.0";
g_ow_btp_overdrive : string := "5.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(2 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component xwb_onewire_master
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_num_ports : integer;
g_ow_btp_normal : string := "5.0";
g_ow_btp_overdrive : string := "1.0");
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
owr_pwren_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_en_o : out std_logic_vector(g_num_ports -1 downto 0);
owr_i : in std_logic_vector(g_num_ports -1 downto 0));
end component;
component wb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_cyc_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_err_o : out std_logic;
wb_int_o : out std_logic;
wb_stall_o : out std_logic;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component xwb_spi
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
pad_cs_o : out std_logic_vector(7 downto 0);
pad_sclk_o : out std_logic;
pad_mosi_o : out std_logic;
pad_miso_i : in std_logic);
end component;
component wb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(4 downto 0);
wb_dat_i : in std_logic_vector(31 downto 0);
wb_dat_o : out std_logic_vector(31 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(3 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component xwb_simple_uart
generic (
g_with_virtual_uart : boolean := false;
g_with_physical_uart : boolean := true;
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor;
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic);
end component;
component wb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
rst_n_i : in std_logic;
clk_sys_i : in std_logic;
wb_adr_i : in std_logic_vector(3 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic);
end component;
component xwb_tics
generic (
g_interface_mode : t_wishbone_interface_mode := CLASSIC;
g_address_granularity : t_wishbone_address_granularity := WORD;
g_period : integer);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
desc_o : out t_wishbone_device_descriptor);
end component;
component wb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width-1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_cyc_i : in std_logic;
wb_sel_i : in std_logic_vector(c_wishbone_data_width/8-1 downto 0);
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
component xwb_vic
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_num_interrupts : natural);
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
irqs_i : in std_logic_vector(g_num_interrupts-1 downto 0);
irq_master_o : out std_logic);
end component;
end wishbone_pkg;
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