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VME64x core
Commit a90f3280 authored by Tristan Gingold's avatar Tristan Gingold
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remove DFS, XAM, FAF, EFM. Address width is always 32.

parent abcf3e01
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ a90f3280
......@@ -155,49 +155,41 @@ entity VME64xCore_Top is
-- Function 0
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 1
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 2
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 3
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 4
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 5
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 6
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
-- Function 7
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
......@@ -269,24 +261,6 @@ entity VME64xCore_Top is
-- Functions
function_o : out std_logic_vector( 3 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
-- IRQ Generator
irq_ack_o : out std_logic; -- when the IRQ controller acknowledges the
-- Interrupt cycle it sends a pulse to the
......@@ -335,13 +309,12 @@ architecture RTL of VME64xCore_Top is
signal s_user_csr_we : std_logic;
-- Function decoders
signal s_addr_decoder_i : std_logic_vector(63 downto 0);
signal s_addr_decoder_o : std_logic_vector(63 downto 0);
signal s_addr_decoder_i : std_logic_vector(31 downto 0);
signal s_addr_decoder_o : std_logic_vector(31 downto 0);
signal s_decode : std_logic;
signal s_sel : std_logic;
signal s_function : std_logic_vector( 2 downto 0);
signal s_am : std_logic_vector( 5 downto 0);
signal s_xam : std_logic_vector( 7 downto 0);
-- Oversampled input signals
signal s_VME_RST_n : std_logic_vector(2 downto 0);
......@@ -362,25 +335,11 @@ architecture RTL of VME64xCore_Top is
g_F0_AMCAP, g_F1_AMCAP, g_F2_AMCAP, g_F3_AMCAP,
g_F4_AMCAP, g_F5_AMCAP, g_F6_AMCAP, g_F7_AMCAP
);
constant c_XAMCAP : t_xamcap_array(0 to 7) := (
g_F0_XAMCAP, g_F1_XAMCAP, g_F2_XAMCAP, g_F3_XAMCAP,
g_F4_XAMCAP, g_F5_XAMCAP, g_F6_XAMCAP, g_F7_XAMCAP
);
constant c_DAWPR : t_dawpr_array(0 to 7) := (
g_F0_DAWPR, g_F1_DAWPR, g_F2_DAWPR, g_F3_DAWPR,
g_F4_DAWPR, g_F5_DAWPR, g_F6_DAWPR, g_F7_DAWPR
);
signal s_faf_ader : t_ader_array(0 to 7);
signal s_dfs_adem : t_adem_array(0 to 7);
begin
s_faf_ader <= (f0_faf_ader_i, f1_faf_ader_i, f2_faf_ader_i, f3_faf_ader_i,
f4_faf_ader_i, f5_faf_ader_i, f6_faf_ader_i, f7_faf_ader_i);
s_dfs_adem <= (f0_dfs_adem_i, f1_dfs_adem_i, f2_dfs_adem_i, f3_dfs_adem_i,
f4_dfs_adem_i, f5_dfs_adem_i, f6_dfs_adem_i, f7_dfs_adem_i);
------------------------------------------------------------------------------
-- Metastability
------------------------------------------------------------------------------
......@@ -453,7 +412,6 @@ begin
addr_decoder_o => s_addr_decoder_i,
decode_o => s_decode,
am_o => s_am,
xam_o => s_xam,
sel_i => s_sel,
-- CR/CSR signals
......@@ -476,8 +434,7 @@ begin
Inst_VME_Funct_Match : VME_Funct_Match
generic map (
g_ADEM => c_ADEM,
g_AMCAP => c_AMCAP,
g_XAMCAP => c_XAMCAP
g_AMCAP => c_AMCAP
)
port map (
clk_i => clk_i,
......@@ -487,11 +444,7 @@ begin
addr_o => s_addr_decoder_o,
decode_i => s_decode,
am_i => s_am,
xam_i => s_xam,
ader_i => s_ader,
dfs_adem_i => s_dfs_adem,
sel_o => s_sel,
function_o => s_function
);
......@@ -568,7 +521,6 @@ begin
g_END_SN => g_END_SN,
g_ADEM => c_ADEM,
g_AMCAP => c_AMCAP,
g_XAMCAP => c_XAMCAP,
g_DAWPR => c_DAWPR
)
port map (
......@@ -596,9 +548,7 @@ begin
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
ader_o => s_ader,
faf_ader_i => s_faf_ader,
dfs_adem_i => s_dfs_adem
ader_o => s_ader
);
-- User CSR space
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ a90f3280
......@@ -124,7 +124,6 @@ entity VME_CR_CSR_Space is
g_END_SN : std_logic_vector(23 downto 0);
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7);
g_DAWPR : t_dawpr_array(0 to 7)
);
port (
......@@ -152,9 +151,7 @@ entity VME_CR_CSR_Space is
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader_o : out t_ader_array(0 to 7);
faf_ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7)
ader_o : out t_ader_array(0 to 7)
);
end VME_CR_CSR_Space;
......@@ -167,7 +164,6 @@ architecture rtl of VME_CR_CSR_Space is
signal s_reg_cram_owner : std_logic_vector(7 downto 0);
signal s_reg_usr_bit_reg : std_logic_vector(7 downto 0);
signal s_reg_ader : t_ader_array(0 to 7);
signal s_ader : t_ader_array(0 to 7);
-- CR/CSR
signal s_cr_access : std_logic;
......@@ -282,7 +278,6 @@ architecture rtl of VME_CR_CSR_Space is
for i in 0 to 7 loop
cr(16#040#+i) := g_DAWPR(i); -- Function X DAWPR
cr(16#048#+i*8 to 16#04f#+i*8) := f_cr_vec(g_AMCAP(i)); -- Function X AMCAP
cr(16#088#+i*32 to 16#0a7#+i*32) := f_cr_vec(g_XAMCAP(i)); -- Function X XAMCAP
cr(16#188#+i*4 to 16#18b#+i*4) := f_cr_vec(g_ADEM(i)); -- Function X ADEM
end loop;
for i in 1 to cr'length-1 loop
......@@ -396,49 +391,7 @@ begin
module_enable_o <= s_reg_bit_reg(c_ENABLE_BIT);
vme_sysfail_ena_o <= s_reg_bit_reg(c_SYSFAIL_EN_BIT);
module_reset_o <= s_reg_bit_reg(c_RESET_BIT);
-- Handle DFS and FAF
process (s_reg_ader, faf_ader_i, dfs_adem_i)
variable v_ader_b0 : std_logic_vector(7 downto 0);
begin
for i in 0 to 7 loop
-- When FAF function or upper bits of previous FAF function, readback
-- and output ADER given at the FAF inputs.
if (i /= 0 and
g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_FAF) = '1') or
((i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0') and
g_ADEM( i )(c_ADEM_FAF) = '1')
then
s_ader(i) <= faf_ader_i(i);
ader_o(i) <= faf_ader_i(i);
-- When upper bits of previous DFS function and DFSR enabled, readback
-- the ADEM value and output zero.
elsif i /= 0 and
g_ADEM(i-1)(c_ADEM_EFM) = '1' and g_ADEM(i-1)(c_ADEM_DFS) = '1' and
s_reg_ader(i-1)(c_ADER_DFSR) = '1'
then
s_ader(i) <= dfs_adem_i(i);
ader_o(i) <= (others => '0');
-- When a DFS function and DFSR enabled, readback the ADEM and output
-- zero.
elsif (i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0') and
g_ADEM(i)(c_ADEM_DFS) = '1' and
s_reg_ader(i)(c_ADER_DFSR) = '1'
then
v_ader_b0 := (c_ADER_DFSR => s_reg_ader(i)(c_ADER_DFSR),
others => '0');
s_ader(i) <= dfs_adem_i(i)(c_ADEM_M) & v_ader_b0;
ader_o(i) <= (others => '0');
-- In all other cases, readback and output the ADER register value.
else
s_ader(i) <= s_reg_ader(i);
ader_o(i) <= s_reg_ader(i);
end if;
end loop;
end process;
ader_o <= s_reg_ader;
-- Read
process (clk_i)
......@@ -473,7 +426,7 @@ begin
v_addr := s_addr(18 downto 2) - to_unsigned(c_ADER_REG_BEG, 17);
v_index := to_integer(v_addr(6 downto 4));
v_byte := 3-to_integer(v_addr(3 downto 2));
s_csr_data <= s_ader(v_index)(8*v_byte+7 downto 8*v_byte);
s_csr_data <= s_reg_ader(v_index)(8*v_byte+7 downto 8*v_byte);
when others =>
s_csr_data <= c_UNUSED;
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ a90f3280
......@@ -39,22 +39,19 @@ use work.vme64x_pack.all;
entity VME_Funct_Match is
generic (
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7)
g_AMCAP : t_amcap_array(0 to 7)
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(63 downto 0);
addr_i : in std_logic_vector(31 downto 0);
-- Sub-address of the function (the part not masked by adem).
addr_o : out std_logic_vector(63 downto 0);
addr_o : out std_logic_vector(31 downto 0);
decode_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0);
xam_i : in std_logic_vector( 7 downto 0);
ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7);
-- Set when a function is selected (ie function_o is valid).
sel_o : out std_logic;
......@@ -65,86 +62,48 @@ end VME_Funct_Match;
architecture rtl of VME_Funct_Match is
type t_addr_array is array (0 to 7) of std_logic_vector(63 downto 0);
signal s_ader : t_addr_array;
signal s_adem : t_addr_array;
-- AM matches ADER AM bits for each function
signal s_am_match : std_logic_vector( 7 downto 0);
-- AM/XAM in AMCAP/XAMCAP for each function
signal s_am_valid : std_logic_vector( 8 downto 0);
signal s_xam_valid : std_logic_vector( 7 downto 0);
-- AM in AMCAP for each function
signal s_am_valid : std_logic_vector( 7 downto 0);
-- Function index and ADEM from priority encoder
signal s_function_sel : std_logic_vector( 7 downto 0);
signal s_adem_sel : std_logic_vector(63 downto 0);
signal s_adem_sel : std_logic_vector(31 downto 0);
-- Selected function
signal s_function : std_logic_vector( 7 downto 0);
signal s_function_ena : std_logic_vector( 7 downto 0);
constant c_AMCAP_ALLOWED : std_logic_vector(63 downto 0) :=
(16#38# to 16#3f# => '1', -- A24
16#2f# => '1', -- CR/CSR
16#2d# | 16#29# => '1', -- A16
16#08# to 16#0f# => '1', -- A32
others => '0');
------------------------------------------------------------------------------
-- Generate AM lookup table
------------------------------------------------------------------------------
-- There are 64 positions in the LUT corresponding to each AM. Each position
-- is a vector whose bit N indicate whether function N accepts this AM.
-- For example if s_am_lut(9) = "00001010", this means that functions 1 & 3
-- accept AM=9. The lookup table has an extra bit (8) which is set only for
-- the 2eVME AMs (0x20 & 0x21) to indicate that these are valid in XAM mode.
type t_am_lut is array (0 to 63) of std_logic_vector(8 downto 0);
-- accept AM=9.
type t_am_lut is array (0 to 63) of std_logic_vector(7 downto 0);
function f_gen_am_lut return t_am_lut is
variable lut : t_am_lut := (others => "000000000");
variable lut : t_am_lut := (others => "00000000");
begin
for i in 0 to 63 loop
for j in 0 to 7 loop
lut(i)(j) := g_AMCAP(j)(i);
end loop;
end loop;
lut(to_integer(unsigned(c_AM_2EVME_6U)))(8) := '1';
lut(to_integer(unsigned(c_AM_2EVME_3U)))(8) := '1';
return lut;
end function;
signal s_am_lut : t_am_lut := f_gen_am_lut;
------------------------------------------------------------------------------
-- Generate XAM lookup table
------------------------------------------------------------------------------
-- Same purpose as the AM lookup table, with 256 positions for each XAM.
type t_xam_lut is array (0 to 255) of std_logic_vector(7 downto 0);
function f_gen_xam_lut return t_xam_lut is
variable lut : t_xam_lut;
begin
for i in 0 to 255 loop
for j in 0 to 7 loop
lut(i)(j) := g_XAMCAP(j)(i);
end loop;
end loop;
return lut;
end function;
signal s_xam_lut : t_xam_lut := f_gen_xam_lut;
------------------------------------------------------------------------------
-- Generate XAM enabled flag
------------------------------------------------------------------------------
-- c_XAM_ENA is true when any XAMCAP /= 0 to conditionally enable the
-- generation of the XAM lookup table.
function f_xam_ena return boolean is
begin
for i in 0 to 7 loop
if g_XAMCAP(i) /= (255 downto 0 => '0') then
return true;
end if;
end loop;
return false;
end function;
constant c_XAM_ENA : boolean := f_xam_ena;
constant c_am_lut : t_am_lut := f_gen_am_lut;
------------------------------------------------------------------------------
-- Generate function enabled vector
......@@ -153,9 +112,7 @@ architecture rtl of VME_Funct_Match is
variable ena : std_logic_vector(7 downto 0) := (others => '0');
begin
for i in 0 to 7 loop
if g_AMCAP(i) /= (63 downto 0 => '0')
and (i = 0 or g_ADEM(i-1)(c_ADEM_EFM) = '0')
then
if g_AMCAP(i) /= (63 downto 0 => '0') then
ena(i) := '1';
end if;
end loop;
......@@ -166,24 +123,6 @@ architecture rtl of VME_Funct_Match is
-- function does not have the EFM bit set.
constant c_ENABLED : std_logic_vector(7 downto 0) := f_function_ena;
------------------------------------------------------------------------------
-- Generate function EFM/EFD enabled vector
------------------------------------------------------------------------------
function f_efm_efd (v : integer) return std_logic_vector is
variable e : std_logic_vector(7 downto 0) := (others => '0');
begin
-- EFM and EFD are not meaningful for function 7 (as there is no next
-- function).
for i in 0 to 6 loop
e(i) := g_ADEM(i)(v);
end loop;
return e;
end function;
constant c_EFM : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFM);
constant c_EFD : std_logic_vector(7 downto 0) := f_efm_efd(c_ADEM_EFD);
constant c_EFD_ENA : boolean := c_EFD /= x"00";
------------------------------------------------------------------------------
-- Generate EFD lookup table
------------------------------------------------------------------------------
......@@ -208,93 +147,28 @@ architecture rtl of VME_Funct_Match is
constant c_EFD_LUT : t_efd_lut := f_gen_efd_lut;
begin
------------------------------------------------------------------------------
-- AM lookup table
------------------------------------------------------------------------------
process (clk_i) begin
if rising_edge(clk_i) then
s_am_valid <= s_am_lut(to_integer(unsigned(am_i)));
end if;
end process;
------------------------------------------------------------------------------
-- XAM lookup table
------------------------------------------------------------------------------
gen_xam_ena : if c_XAM_ENA = true generate
process (clk_i) begin
if rising_edge(clk_i) then
s_xam_valid <= s_xam_lut(to_integer(unsigned(xam_i)));
end if;
end process;
-- Check for invalid bits in ADEM/AMCAP
gen_gchecks: for i in 7 downto 0 generate
assert g_ADEM(i)(c_ADEM_FAF) = '0' report "FAF bit set in ADEM"
severity error;
assert g_ADEM(i)(c_ADEM_DFS) = '0' report "DFS bit set in ADEM"
severity error;
assert g_ADEM(i)(c_ADEM_EFM) = '0' report "EFM bit set in ADEM"
severity error;
assert (g_AMCAP(i) and c_AMCAP_ALLOWED) /= (63 downto 0 => '0')
report "bit set in AMCAP for not supported AM"
severity error;
end generate;
gen_xam_dis : if c_XAM_ENA = false generate
s_xam_valid <= x"00";
end generate;
------------------------------------------------------------------------------
-- Function match
------------------------------------------------------------------------------
gen_match_loop : for i in 0 to 7 generate
gen_ena_function: if c_ENABLED(i) = '1' generate
-- Create 64-bit ADEM/ADER based on EFM and DFS setting
gen_efm_ena: if c_EFM(i) = '1' generate
-- Extra mask
gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate
s_adem(i) <= dfs_adem_i(i+1) & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
gen_dfs_dis: if g_ADEM(i)(c_ADEM_DFS) = '0' generate
s_adem(i) <= g_ADEM(i+1) & g_ADEM(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
s_ader(i)(63 downto 32) <= ader_i(i+1);
end generate;
gen_efm_dis: if c_EFM(i) = '0' generate
gen_dfs_ena: if g_ADEM(i)(c_ADEM_DFS) = '1' generate
s_adem(i) <= x"ffff_ffff" & dfs_adem_i(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
gen_dfs_dis: if g_ADEM(i)(c_ADEM_DFS) = '0' generate
s_adem(i) <= x"ffff_ffff" & g_ADEM(i)(c_ADEM_M) & c_ADEM_M_PAD;
end generate;
s_ader(i)(63 downto 32) <= x"0000_0000";
end generate;
process (ader_i(i), am_i, xam_i) begin
if ader_i(i)(c_ADER_XAM_MODE) = '1' then
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_XAM) & c_ADER_C_XAM_PAD;
if ader_i(i)(c_ADER_XAM) = xam_i then
s_am_match(i) <= '1';
else
s_am_match(i) <= '0';
end if;
else
s_ader(i)(31 downto 0) <= ader_i(i)(c_ADER_C_AM) & c_ADER_C_AM_PAD;
if ader_i(i)(c_ADER_AM) = am_i then
s_am_match(i) <= '1';
else
s_am_match(i) <= '0';
end if;
end if;
end process;
s_function(i) <= '1' when (addr_i and s_adem(i)) = s_ader(i) and
s_am_match(i) = '1'
else '0';
end generate;
gen_dis_function: if c_ENABLED(i) = '0' generate
s_adem(i) <= (others => '0');
s_ader(i) <= (others => '0');
s_am_match(i) <= '0';
s_function(i) <= '0';
end generate;
s_function(i) <=
'1' when (((addr_i(c_ADEM_M) and g_ADEM(i)(c_ADEM_M))
= ader_i(i)(c_ADEM_M))
and (am_i = ader_i(i)(c_ADER_AM)))
else '0';
end generate;
------------------------------------------------------------------------------
......@@ -306,49 +180,32 @@ begin
s_function_sel <= (others => '0');
s_adem_sel <= (others => '0');
else
if s_function(0) = '1' then
s_function_sel <= "00000001";
s_adem_sel <= s_adem(0);
elsif s_function(1) = '1' then
s_function_sel <= "00000010";
s_adem_sel <= s_adem(1);
elsif s_function(2) = '1' then
s_function_sel <= "00000100";
s_adem_sel <= s_adem(2);
elsif s_function(3) = '1' then
s_function_sel <= "00001000";
s_adem_sel <= s_adem(3);
elsif s_function(4) = '1' then
s_function_sel <= "00010000";
s_adem_sel <= s_adem(4);
elsif s_function(5) = '1' then
s_function_sel <= "00100000";
s_adem_sel <= s_adem(5);
elsif s_function(6) = '1' then
s_function_sel <= "01000000";
s_adem_sel <= s_adem(6);
elsif s_function(7) = '1' then
s_function_sel <= "10000000";
s_adem_sel <= s_adem(7);
end if;
s_function_sel <= (others => '0');
s_adem_sel <= (others => '0');
for i in 0 to 7 loop
if s_function(i) = '1' then
s_function_sel(i) <= '1';
s_adem_sel (c_ADEM_M) <= g_adem(i)(c_ADEM_M);
exit;
end if;
end loop;
end if;
end if;
end process;
------------------------------------------------------------------------------
-- Check of AM/XAM against AMCAP/XAMCAP
------------------------------------------------------------------------------
process (s_ader, s_am_valid, s_xam_valid, s_function_sel) begin
for i in 0 to 7 loop
if s_ader(i)(c_ADER_XAM_MODE) = '1' then
s_function_ena(i) <= s_function_sel(i) and s_am_valid(i) and
s_xam_valid(i) and s_am_valid(8);
else
s_function_ena(i) <= s_function_sel(i) and s_am_valid(i);
end if;
end loop;
-----------------------------------------------------------------------------
-- AM lookup table
-----------------------------------------------------------------------------
process (clk_i) begin
if rising_edge(clk_i) then
s_am_valid <= c_am_lut(to_integer(unsigned(am_i)));
end if;
end process;
-- Check of AM against AMCAP
s_function_ena <= s_function_sel and s_am_valid;
------------------------------------------------------------------------------
-- Address output latch
------------------------------------------------------------------------------
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ a90f3280
......@@ -85,7 +85,7 @@ entity VME_Wb_master is
sel_i : in std_logic_vector(7 downto 0);
locDataInSwap_i : in std_logic_vector(63 downto 0);
locDataOut_o : out std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(31 downto 0);
memAckWb_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
......@@ -157,7 +157,8 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_WB_ADDR_WIDTH));
locAddr_o (63 downto 29) <= (others => '0');
locAddr_o (28 downto 0) <= rel_locAddr_i (31 downto 3);
end if;
end process;
......@@ -230,7 +231,8 @@ begin
process (clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2, g_WB_ADDR_WIDTH));
locAddr_o (31 downto 30) <= (others => '0');
locAddr_o (29 downto 0) <= rel_locAddr_i (31 downto 2);
end if;
end process;
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ a90f3280
......@@ -114,8 +114,8 @@ entity VME_bus is
stall_i : in std_logic;
-- Function decoder
addr_decoder_i : in std_logic_vector(63 downto 0);
addr_decoder_o : out std_logic_vector(63 downto 0);
addr_decoder_i : in std_logic_vector(31 downto 0);
addr_decoder_o : out std_logic_vector(31 downto 0);
decode_o : out std_logic;
am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0);
......@@ -144,14 +144,14 @@ architecture RTL of VME_bus is
-- Local data & address
signal s_locDataIn : std_logic_vector(63 downto 0);
signal s_locDataOut : std_logic_vector(63 downto 0); -- Local data
signal s_locAddr : std_logic_vector(63 downto 0); -- Local address
signal s_locAddr : std_logic_vector(31 downto 0); -- Local address
signal s_DataShift : std_logic;
signal s_locDataOutSwap : std_logic_vector(63 downto 0);
signal s_locDataInSwap : std_logic_vector(63 downto 0);
signal s_locDataOutWb : std_logic_vector(63 downto 0);
-- VME latched signals
signal s_ADDRlatched : std_logic_vector(63 downto 1);
signal s_ADDRlatched : std_logic_vector(31 downto 1);
signal s_LWORDlatched : std_logic;
signal s_DSlatched : std_logic_vector(1 downto 0);
signal s_AMlatched : std_logic_vector(5 downto 0);
......@@ -408,7 +408,7 @@ begin
s_mainFSMstate <= REFORMAT_ADDRESS;
-- Store ADDR, AM and LWORD
s_ADDRlatched <= VME_DATA_i & VME_ADDR_i;
s_ADDRlatched <= VME_ADDR_i;
s_LWORDlatched <= VME_LWORD_n_i;
s_AMlatched <= VME_AM_i;
......@@ -420,13 +420,11 @@ begin
-- Reformat address according to the mode (A16, A24, A32 or A64)
case s_addrWidth is
when "00" =>
s_ADDRlatched (63 downto 16) <= (others => '0'); -- A16
s_ADDRlatched (31 downto 16) <= (others => '0'); -- A16
when "01" =>
s_ADDRlatched (63 downto 24) <= (others => '0'); -- A24
when "10" =>
s_ADDRlatched (63 downto 32) <= (others => '0'); -- A32
when others =>
null; -- A64
s_ADDRlatched (31 downto 24) <= (others => '0'); -- A24
when others => -- A32
null;
end case;
s_mainFSMstate <= DECODE_ACCESS_0;
......@@ -451,7 +449,7 @@ begin
-- card_sel = '1' it means WB application addressed
s_mainFSMstate <= WAIT_FOR_DS;
-- Keep only the local part of the address
s_ADDRlatched <= addr_decoder_i (63 downto 1);
s_ADDRlatched <= addr_decoder_i (31 downto 1);
else
-- another board will answer; wait here the rising edge on
-- VME_AS_i (done by top if).
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ a90f3280
......@@ -110,7 +110,6 @@ package vme64x_pack is
type t_adem_array is array (integer range <>) of std_logic_vector( 31 downto 0);
type t_ader_array is array (integer range <>) of std_logic_vector( 31 downto 0);
type t_amcap_array is array (integer range <>) of std_logic_vector( 63 downto 0);
type t_xamcap_array is array (integer range <>) of std_logic_vector(255 downto 0);
type t_dawpr_array is array (integer range <>) of std_logic_vector( 7 downto 0);
------------------------------------------------------------------------------
......@@ -138,35 +137,27 @@ package vme64x_pack is
g_END_SN : std_logic_vector(23 downto 0) := x"000000";
g_F0_ADEM : std_logic_vector( 31 downto 0) := x"ff000000";
g_F0_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_0000bb00";
g_F0_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F0_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F1_ADEM : std_logic_vector( 31 downto 0) := x"fff80000";
g_F1_AMCAP : std_logic_vector( 63 downto 0) := x"bb000000_00000000";
g_F1_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F1_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F2_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F2_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F2_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F2_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F3_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F3_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F3_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F3_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F4_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F4_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F4_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F4_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F5_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F5_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F5_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F5_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F6_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F6_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F6_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F6_DAWPR : std_logic_vector( 7 downto 0) := x"84";
g_F7_ADEM : std_logic_vector( 31 downto 0) := x"00000000";
g_F7_AMCAP : std_logic_vector( 63 downto 0) := x"00000000_00000000";
g_F7_XAMCAP : std_logic_vector(255 downto 0) := x"00000000_00000000_00000000_00000000_00000000_00000000_00000000_00000000";
g_F7_DAWPR : std_logic_vector( 7 downto 0) := x"84"
);
port (
......@@ -219,22 +210,6 @@ package vme64x_pack is
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0) := (others => '0');
function_o : out std_logic_vector( 3 downto 0);
f0_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_faf_ader_i : in std_logic_vector(31 downto 0) := (others => '0');
f0_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f1_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f2_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f3_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f4_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f5_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f6_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
f7_dfs_adem_i : in std_logic_vector(31 downto 0) := (others => '0');
irq_ack_o : out std_logic;
irq_i : in std_logic
);
......@@ -280,11 +255,10 @@ package vme64x_pack is
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
addr_decoder_i : in std_logic_vector(63 downto 0);
addr_decoder_o : out std_logic_vector(63 downto 0);
addr_decoder_i : in std_logic_vector(31 downto 0);
addr_decoder_o : out std_logic_vector(31 downto 0);
decode_o : out std_logic;
am_o : out std_logic_vector( 5 downto 0);
xam_o : out std_logic_vector( 7 downto 0);
sel_i : in std_logic;
cr_csr_addr_o : out std_logic_vector(18 downto 2);
cr_csr_data_i : in std_logic_vector( 7 downto 0);
......@@ -299,19 +273,16 @@ package vme64x_pack is
component VME_Funct_Match is
generic (
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7)
g_AMCAP : t_amcap_array(0 to 7)
);
port (
clk_i : in std_logic;
rst_n_i : in std_logic;
addr_i : in std_logic_vector(63 downto 0);
addr_o : out std_logic_vector(63 downto 0);
addr_i : in std_logic_vector(31 downto 0);
addr_o : out std_logic_vector(31 downto 0);
decode_i : in std_logic;
am_i : in std_logic_vector( 5 downto 0);
xam_i : in std_logic_vector( 7 downto 0);
ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7);
sel_o : out std_logic;
function_o : out std_logic_vector( 2 downto 0)
);
......@@ -334,7 +305,6 @@ package vme64x_pack is
g_END_SN : std_logic_vector(23 downto 0);
g_ADEM : t_adem_array(0 to 7);
g_AMCAP : t_amcap_array(0 to 7);
g_XAMCAP : t_xamcap_array(0 to 7);
g_DAWPR : t_dawpr_array(0 to 7)
);
port (
......@@ -357,9 +327,7 @@ package vme64x_pack is
user_csr_we_o : out std_logic;
user_cr_addr_o : out std_logic_vector(18 downto 2);
user_cr_data_i : in std_logic_vector( 7 downto 0);
ader_o : out t_ader_array(0 to 7);
faf_ader_i : in t_ader_array(0 to 7);
dfs_adem_i : in t_adem_array(0 to 7)
ader_o : out t_ader_array(0 to 7)
);
end component VME_CR_CSR_Space;
......@@ -395,7 +363,7 @@ package vme64x_pack is
BERRcondition_i : in std_logic;
sel_i : in std_logic_vector(7 downto 0);
locDataInSwap_i : in std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(31 downto 0);
RW_i : in std_logic;
stall_i : in std_logic;
rty_i : in std_logic;
......
hdl/vme64x-core/sim/simple_tb/top_tb.vhd
View file @ a90f3280
......@@ -219,22 +219,6 @@ architecture behaviour of top_tb is
signal user_cr_addr_o : std_logic_vector(18 downto 2);
signal user_cr_data_i : std_logic_vector( 7 downto 0) := (others => '0');
signal function_o : std_logic_vector( 3 downto 0);
signal f0_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f1_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f2_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f3_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f4_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f5_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f6_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f7_faf_ader_i : std_logic_vector(31 downto 0) := (others => '0');
signal f0_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f1_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f2_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f3_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f4_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f5_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f6_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal f7_dfs_adem_i : std_logic_vector(31 downto 0) := (others => '0');
signal irq_ack_o : std_logic;
signal irq_i : std_logic;
......@@ -303,22 +287,6 @@ begin
user_cr_addr_o => user_cr_addr_o,
user_cr_data_i => user_cr_data_i,
function_o => function_o,
f0_faf_ader_i => f0_faf_ader_i,
f1_faf_ader_i => f1_faf_ader_i,
f2_faf_ader_i => f2_faf_ader_i,
f3_faf_ader_i => f3_faf_ader_i,
f4_faf_ader_i => f4_faf_ader_i,
f5_faf_ader_i => f5_faf_ader_i,
f6_faf_ader_i => f6_faf_ader_i,
f7_faf_ader_i => f7_faf_ader_i,
f0_dfs_adem_i => f0_dfs_adem_i,
f1_dfs_adem_i => f1_dfs_adem_i,
f2_dfs_adem_i => f2_dfs_adem_i,
f3_dfs_adem_i => f3_dfs_adem_i,
f4_dfs_adem_i => f4_dfs_adem_i,
f5_dfs_adem_i => f5_dfs_adem_i,
f6_dfs_adem_i => f6_dfs_adem_i,
f7_dfs_adem_i => f7_dfs_adem_i,
irq_ack_o => irq_ack_o,
irq_i => irq_i);
......
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