Modify reset

Create a port (rst_n_o) on the top level component which is the combination of the HW resets (rst_n_i and VME_RST_n_i) and the SW reset bit coming from the CR/CSR. Signed-off-by: Tom Levens <tom.levens@cern.ch>

Modify reset
Create a port (rst_n_o) on the top level component which is the combination of the HW resets (rst_n_i and VME_RST_n_i) and the SW reset bit coming from the CR/CSR. Signed-off-by: Tom Levens <tom.levens@cern.ch>
a293bef9 · Tom Levens · 78cb0c4a · a293bef9 · a293bef9 · a293bef9
Commit a293bef9 authored Jan 13, 2017 by Tom Levens
7 changed files
--- a/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
+++ b/hdl/vme64x-core/rtl/VME64xCore_Top.vhd
@@ -203,6 +203,7 @@ entity VME64xCore_Top is
  port (
    clk_i           : in  std_logic;
    rst_n_i         : in  std_logic;
+    rst_n_o         : out std_logic;
    -- VME
    VME_AS_n_i      : in  std_logic;
@@ -383,11 +384,9 @@ begin
    )
    port map (
      clk_i           => clk_i,
-      rst_n_i         => rst_n_i,
+      rst_i           => s_reset,
-      reset_o         => s_reset,       -- asserted when '1'
      -- VME
-      VME_RST_n_i     => s_VME_RST_n(2),
      VME_AS_n_i      => s_VME_AS_n(2),
      VME_LWORD_n_o   => VME_LWORD_n_o,
      VME_LWORD_n_i   => VME_LWORD_n_i,
@@ -438,11 +437,12 @@ begin
      ader7_i         => s_ader7,
      endian_i        => endian_i,
      module_enable_i => s_module_enable,
-      module_reset_i  => s_module_reset,
      bar_i           => s_bar
    );
+  s_reset    <= (not rst_n_i) or (not s_VME_RST_n(2));
  s_reset_n  <= not s_reset;
+  rst_n_o    <= not (s_reset or s_module_reset);
  VME_BERR_o <= not s_vme_berr_n; -- The VME_BERR is asserted when '1' because
                                  -- the buffers on the board invert the logic.
@@ -526,7 +526,7 @@ begin
    )
    port map (
      clk_i               => clk_i,
-      reset_i             => s_reset,
+      rst_n_i             => s_reset_n,
      vme_ga_i            => VME_GA_i,
      vme_berr_n_i        => s_vme_berr_n,

--- a/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
+++ b/hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
@@ -119,7 +119,7 @@ entity VME_CR_CSR_Space is
  );
  port (
    clk_i               : in  std_logic;
-    reset_i             : in  std_logic;
+    rst_n_i             : in  std_logic;
    vme_ga_i            : in  std_logic_vector(5 downto 0);
    vme_berr_n_i        : in  std_logic;
@@ -222,7 +222,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if reset_i = '1' then
+      if rst_n_i = '0' then
        if s_ga_parity = '1' then
          s_reg_bar       <= (not vme_ga_i(4 downto 0)) & "000";
        else
@@ -339,7 +339,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if reset_i = '1' then
+      if rst_n_i = '0' then
        s_csr_data <= x"ff";
      else
        case s_addr is

--- a/hdl/vme64x-core/rtl/VME_User_CSR.vhd
+++ b/hdl/vme64x-core/rtl/VME_User_CSR.vhd
@@ -74,7 +74,7 @@ entity VME_User_CSR is
  );
  port (
    clk_i               : in  std_logic;
-    reset_i             : in  std_logic;
+    rst_n_i             : in  std_logic;
    addr_i              : in  std_logic_vector(18 downto 2);
    data_i              : in  std_logic_vector( 7 downto 0);
@@ -108,7 +108,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if reset_i = '1' then
+      if rst_n_i = '0' then
        s_reg_irq_vector  <= x"00";
        s_reg_irq_level   <= x"00";
        s_reg_endian      <= x"00";
@@ -133,7 +133,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if reset_i = '1' then
+      if rst_n_i = '0' then
        data_o <= x"00";
      else
        case s_addr is

--- a/hdl/vme64x-core/rtl/VME_bus.vhd
+++ b/hdl/vme64x-core/rtl/VME_bus.vhd
@@ -105,11 +105,9 @@ entity VME_bus is
  );
  port (
    clk_i           : in  std_logic;
-    rst_n_i         : in  std_logic;
+    rst_i           : in  std_logic;
-    reset_o         : out std_logic;  -- to the Interrupt Generator and IRQ
-                                      -- controller
    -- VME signals
-    VME_RST_n_i     : in  std_logic;
    VME_AS_n_i      : in  std_logic;
    VME_LWORD_n_o   : out std_logic := '0';
    VME_LWORD_n_i   : in  std_logic;
@@ -161,14 +159,12 @@ entity VME_bus is
    ader7_i         : in  std_logic_vector(31 downto 0);
    endian_i        : in  std_logic_vector(2 downto 0);
    module_enable_i : in  std_logic;
-    module_reset_i  : in  std_logic;
    bar_i           : in  std_logic_vector(4 downto 0)
  );
 end VME_bus;
 architecture RTL of VME_bus is
-  signal s_reset                    : std_logic;
  signal s_rw                       : std_logic;
  -- Input signals
@@ -292,10 +288,6 @@ begin
  -- Used to drive the VME_ADDR_DIR_o
  s_is_d64      <= '1' when s_sel = "11111111" else '0';
-  -- HW and SW reset
-  s_reset       <= (not rst_n_i) or (not VME_RST_n_i) or s_sw_reset;
-  reset_o       <= s_reset;             -- Asserted when high
  -- These output signals are connected to the buffers on the board
  -- SN74VMEH22501A Function table:
  --   OEn | DIR | OUTPUT                 OEAB   |   OEBYn   |   OUTPUT
@@ -427,7 +419,7 @@ begin
  p_VMEmainFSM : process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' or s_mainFSMreset = '1' then
+      if rst_i = '1' or s_mainFSMreset = '1' then
        -- FSM resetted after power up,
        -- software reset, manually reset,
        -- on rising edge of AS.
@@ -753,7 +745,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' then
+      if rst_i = '1' then
        s_BERRcondition <= '0';
      elsif
        ((s_transferType = error or s_wberr1 = '1') and s_transferActive = '1') or
@@ -783,7 +775,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_mainFSMreset = '1' or s_reset = '1' then
+      if s_mainFSMreset = '1' or rst_i = '1' then
        s_wberr1 <= '0';
      elsif s_err = '1' then
        s_wberr1 <= '1';
@@ -795,7 +787,7 @@ begin
  process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_mainFSMreset = '1' or s_reset = '1' then
+      if s_mainFSMreset = '1' or rst_i = '1' then
        s_rty1 <= '0';
      elsif s_rty = '1' then
        s_rty1 <= '1';
@@ -838,7 +830,7 @@ begin
  p_addrLatching : process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' or s_mainFSMreset = '1' then
+      if rst_i = '1' or s_mainFSMreset = '1' then
        s_VMEaddrLatched <= (others => '0');
        s_LWORDlatched   <= '0';
        s_AMlatched      <= (others => '0');
@@ -893,7 +885,7 @@ begin
  p_addrIncrementing : process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' or s_mainFSMreset = '1' then
+      if rst_i = '1' or s_mainFSMreset = '1' then
        s_addrOffset <= (others => '0');
      elsif s_incrementAddr = '1' then
        if s_addressingType = TWOedge then
@@ -934,7 +926,7 @@ begin
  p_DSlatching : process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' then
+      if rst_i = '1' then
        s_DSlatched <= (others => '0');
      else
        if s_DSlatch = '1' then
@@ -1076,7 +1068,7 @@ begin
  -- This component acts as WB master for single read/write PIPELINED mode.
  -- The data and address lines are shifted inside this component.
-  s_wbMaster_rst <= s_reset or s_mainFSMreset;
+  s_wbMaster_rst <= rst_i or s_mainFSMreset;
  Inst_Wb_master : VME_Wb_master
    generic map (
@@ -1123,7 +1115,7 @@ begin
  Inst_Access_Decode : VME_Access_Decode
    port map (
      clk_i          => clk_i,
-      reset          => s_reset,
+      reset          => rst_i,
      mainFSMreset   => s_mainFSMreset,
      decode         => s_decode,
      ModuleEnable   => module_enable_i,
@@ -1187,7 +1179,7 @@ begin
  p_memAckCSR : process (clk_i)
  begin
    if rising_edge(clk_i) then
-      if s_reset = '1' then
+      if rst_i = '1' then
        s_memAckCSR <= '0';
      else
        if s_memReq = '1' and s_confAccess = '1' then
@@ -1210,23 +1202,6 @@ begin
                            s_RW          = '0'
                            else '0';
-  ------------------------------------------------------------------------------
-  -- Software Reset
-  ------------------------------------------------------------------------------
-  -- The VME Master assert the BIT SET REGISTER's bit 7. The reset will be
-  -- effective the next AS rising edge at the end of the write operation in this
-  -- register.
-  process (clk_i)
-  begin
-    if rising_edge(clk_i) then
-      if s_mainFSMreset = '1' then
-        s_sw_reset <= module_reset_i;
-      else
-        s_sw_reset <= '0';
-      end if;
-    end if;
-  end process;
  ------------------------------------------------------------------------------
  -- Edge Detection and Sampling
  ------------------------------------------------------------------------------

--- a/hdl/vme64x-core/rtl/vme64x_pack.vhd
+++ b/hdl/vme64x-core/rtl/vme64x_pack.vhd
@@ -386,6 +386,7 @@ package vme64x_pack is
    port (
      clk_i           : in  std_logic;
      rst_n_i         : in  std_logic;
+      rst_n_o         : out std_logic;
      VME_AS_n_i      : in  std_logic;
      VME_RST_n_i     : in  std_logic;
      VME_WRITE_n_i   : in  std_logic;
@@ -474,9 +475,7 @@ package vme64x_pack is
    );
    port (
      clk_i           : in  std_logic;
-      rst_n_i         : in  std_logic;
+      rst_i           : in  std_logic;
-      reset_o         : out std_logic;
-      VME_RST_n_i     : in  std_logic;
      VME_AS_n_i      : in  std_logic;
      VME_LWORD_n_o   : out std_logic;
      VME_LWORD_n_i   : in  std_logic;
@@ -523,7 +522,6 @@ package vme64x_pack is
      ader7_i         : in  std_logic_vector(31 downto 0);
      endian_i        : in  std_logic_vector(2 downto 0);
      module_enable_i : in  std_logic;
-      module_reset_i  : in  std_logic;
      bar_i           : in  std_logic_vector(4 downto 0)
    );
  end component VME_bus;
@@ -621,7 +619,7 @@ package vme64x_pack is
    );
    port (
      clk_i               : in  std_logic;
-      reset_i             : in  std_logic;
+      rst_n_i             : in  std_logic;
      vme_ga_i            : in  std_logic_vector(5 downto 0);
      vme_berr_n_i        : in  std_logic;
      bar_o               : out std_logic_vector(4 downto 0);
@@ -693,7 +691,7 @@ package vme64x_pack is
    );
    port (
      clk_i               : in  std_logic;
-      reset_i             : in  std_logic;
+      rst_n_i             : in  std_logic;
      addr_i              : in  std_logic_vector(18 downto 2);
      data_i              : in  std_logic_vector( 7 downto 0);
      data_o              : out std_logic_vector( 7 downto 0);

--- a/hdl/vme64x-core/rtl/xvme64x_core.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core.vhd
@@ -104,6 +104,7 @@ entity xvme64x_core is
  port (
    clk_i           : in  std_logic;
    rst_n_i         : in  std_logic;
+    rst_n_o         : out std_logic;
    VME_AS_n_i      : in  std_logic;
    VME_RST_n_i     : in  std_logic;
@@ -152,12 +153,9 @@ architecture wrapper of xvme64x_core is
  signal user_csr_data_i,
         user_csr_data_o  : std_logic_vector( 7 downto 0);
  signal user_csr_we      : std_logic;
-  signal rst              : std_logic;
 begin  -- wrapper
-  rst <= not rst_n_i;
  U_Wrapped_VME : VME64xCore_Top
    generic map (
      g_clock           => g_clock_period,
@@ -212,6 +210,8 @@ begin  -- wrapper
    port map (
      clk_i           => clk_i,
      rst_n_i         => rst_n_i,
+      rst_n_o         => rst_n_o,
      VME_AS_n_i      => VME_AS_n_i,
      VME_RST_n_i     => VME_RST_n_i,
      VME_WRITE_n_i   => VME_WRITE_n_i,
@@ -276,7 +276,7 @@ begin  -- wrapper
    )
    port map (
      clk_i           => clk_i,
-      reset_i         => rst,
+      rst_n_i         => rst_n_i,
      addr_i          => user_csr_addr,
      data_i          => user_csr_data_i,
      data_o          => user_csr_data_o,

--- a/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
+++ b/hdl/vme64x-core/rtl/xvme64x_core_pkg.vhd
@@ -130,6 +130,7 @@ package xvme64x_core_pkg is
    port (
      clk_i           : in  std_logic;
      rst_n_i         : in  std_logic;
+      rst_n_o         : out std_logic;
      VME_AS_n_i      : in  std_logic;
      VME_RST_n_i     : in  std_logic;