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VME64x core
Commits
98894891
Commit
98894891
authored
Sep 22, 2017
by
Tristan Gingold
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Remove unused rtl files.
parent
3a60c1ba
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VME_Wb_master.vhd
hdl/vme64x-core/rtl/VME_Wb_master.vhd
+0
-173
VME_swapper.vhd
hdl/vme64x-core/rtl/VME_swapper.vhd
+0
-185
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hdl/vme64x-core/rtl/VME_Wb_master.vhd
deleted
100644 → 0
View file @
3a60c1ba
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_Wb_master (VME_Wb_master.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- This component implements the WB master side in the vme64x core.
--
-- Work mode:
-- PIPELINED
-- SINGLE READ/WRITE
--
-- The WB bus can be 64 bit wide or 32 bit wide and the data organization is
-- BIG ENDIAN --> the most significant byte is carried in the lower position
-- of the bus. Eg:
-- _______________________________________________________________________
-- | Byte(0)| Byte(1)| Byte(2)| Byte(3)| Byte(4)| Byte(5)| Byte(6)| Byte(7)|
-- |________|________|________|________|________|________|________|________|
-- D[63:56] D[55:48] D[47:40] D[39:32] D[31:24] D[23:16] D[15:8] D[7:0]
--
-- eg of timing diagram with synchronous WB Slave:
--
-- Clk _____ _____ _____ _____ _____ _____
-- _____| |_____| |_____| |_____| |_____| |_____| |
--
-- cyc_o ____________________________________________________________
-- _____| |_____
--
-- stb_o ________________________________________________
-- _____| |_________________
--
-- __________________________________________
-- stall_i |_____________________________
--
-- ack_i ___________
-- ______________________________________________________| |_____
--
-- The ack_i can be asserted with some Tclk of delay, not immediately.
-- This component implements the correct shift of the data in input/output
-- from/to WB bus
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
use
work
.
vme64x_pack
.
all
;
entity
VME_Wb_master
is
generic
(
g_WB_DATA_WIDTH
:
integer
;
g_WB_ADDR_WIDTH
:
integer
);
port
(
memReq_i
:
in
std_logic
;
clk_i
:
in
std_logic
;
reset_i
:
in
std_logic
;
sel_i
:
in
std_logic_vector
(
3
downto
0
);
locDataInSwap_i
:
in
std_logic_vector
(
31
downto
0
);
locDataOut_o
:
out
std_logic_vector
(
31
downto
0
);
rel_locAddr_i
:
in
std_logic_vector
(
31
downto
0
);
memAckWb_o
:
out
std_logic
;
err_o
:
out
std_logic
;
rty_o
:
out
std_logic
;
RW_i
:
in
std_logic
;
stall_i
:
in
std_logic
;
rty_i
:
in
std_logic
;
err_i
:
in
std_logic
;
cyc_o
:
out
std_logic
;
stb_o
:
out
std_logic
;
WBdata_o
:
out
std_logic_vector
(
g_WB_DATA_WIDTH
-1
downto
0
);
wbData_i
:
in
std_logic_vector
(
g_WB_DATA_WIDTH
-1
downto
0
);
locAddr_o
:
out
std_logic_vector
(
g_WB_ADDR_WIDTH
-1
downto
0
);
ack_i
:
in
std_logic
;
WbSel_o
:
out
std_logic_vector
(
g_WB_DATA_WIDTH
/
8-1
downto
0
);
RW_o
:
out
std_logic
);
end
VME_Wb_master
;
architecture
Behavioral
of
VME_Wb_master
is
signal
s_AckWithError
:
std_logic
;
begin
-- stb handler
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
reset_i
=
'1'
then
stb_o
<=
'0'
;
cyc_o
<=
'0'
;
else
if
memReq_i
=
'1'
then
stb_o
<=
'1'
;
cyc_o
<=
'1'
;
else
-- One pulse for stb_o
stb_o
<=
'0'
;
-- But s_cyc is set for the whole cycle
if
ack_i
=
'1'
or
err_i
=
'1'
then
cyc_o
<=
'0'
;
end
if
;
end
if
;
end
if
;
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
RW_o
<=
RW_i
;
end
if
;
end
process
;
-- shift data and address for WB data bus 32 bits
assert
g_WB_DATA_WIDTH
=
32
severity
failure
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
locAddr_o
(
31
downto
30
)
<=
(
others
=>
'0'
);
locAddr_o
(
29
downto
0
)
<=
rel_locAddr_i
(
31
downto
2
);
end
if
;
end
process
;
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
WBdata_o
<=
locDataInSwap_i
;
WbSel_o
<=
sel_i
;
end
if
;
end
process
;
err_o
<=
err_i
;
rty_o
<=
rty_i
;
-- This process registers the WB data input; this is a warranty that this
-- data will be stable during all the time the VME_bus component needs to
-- transfers its to the VME bus.
process
(
clk_i
)
begin
if
rising_edge
(
clk_i
)
then
if
ack_i
=
'1'
then
locDataOut_o
<=
wbData_i
;
end
if
;
memAckWb_o
<=
ack_i
or
err_i
or
rty_i
;
end
if
;
end
process
;
end
Behavioral
;
hdl/vme64x-core/rtl/VME_swapper.vhd
deleted
100644 → 0
View file @
3a60c1ba
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
--------------------------------------------------------------------------------
--
-- unit name: VME_swapper (VME_swapper.vhd)
--
-- author: Pablo Alvarez Sanchez <pablo.alvarez.sanchez@cern.ch>
-- Davide Pedretti <davide.pedretti@cern.ch>
--
-- description:
--
-- sel = 00 --> No swap
-- sel = 01 --> Swap Byte (eg: 01234567 became 10325476)
-- sel = 10 --> Swap Word (eg: 01234567 became 23016745)
-- sel = 11 --> Swap Word+Swap Byte (eg: 01234567 became 32107654)
--
-- dependencies:
--
--------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: see log.
--------------------------------------------------------------------------------
-- TODO: -
--------------------------------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
VME_swapper
is
port
(
d_i
:
in
std_logic_vector
(
63
downto
0
);
sel
:
in
std_logic_vector
(
2
downto
0
);
d_o
:
out
std_logic_vector
(
63
downto
0
)
);
end
VME_swapper
;
architecture
Behavioral
of
VME_swapper
is
signal
Byte0_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte1_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte2_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte3_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte4_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte5_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte6_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte7_i
:
std_logic_vector
(
7
downto
0
);
signal
Byte0_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte1_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte2_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte3_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte4_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte5_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte6_o
:
std_logic_vector
(
7
downto
0
);
signal
Byte7_o
:
std_logic_vector
(
7
downto
0
);
begin
process
(
sel
,
Byte0_i
,
Byte1_i
,
Byte2_i
,
Byte3_i
,
Byte7_i
)
begin
case
sel
is
when
"000"
=>
Byte0_o
<=
Byte0_i
;
when
"001"
=>
Byte0_o
<=
Byte1_i
;
when
"010"
=>
Byte0_o
<=
Byte2_i
;
when
"011"
=>
Byte0_o
<=
Byte3_i
;
when
"100"
=>
Byte0_o
<=
Byte7_i
;
when
others
=>
Byte0_o
<=
Byte0_i
;
end
case
;
end
process
;
process
(
sel
,
Byte0_i
,
Byte1_i
,
Byte2_i
,
Byte3_i
,
Byte6_i
)
begin
case
sel
is
when
"000"
=>
Byte1_o
<=
Byte1_i
;
when
"001"
=>
Byte1_o
<=
Byte0_i
;
when
"010"
=>
Byte1_o
<=
Byte3_i
;
when
"011"
=>
Byte1_o
<=
Byte2_i
;
when
"100"
=>
Byte1_o
<=
Byte6_i
;
when
others
=>
Byte1_o
<=
Byte1_i
;
end
case
;
end
process
;
process
(
sel
,
Byte0_i
,
Byte1_i
,
Byte2_i
,
Byte3_i
,
Byte5_i
)
begin
case
sel
is
when
"000"
=>
Byte2_o
<=
Byte2_i
;
when
"001"
=>
Byte2_o
<=
Byte3_i
;
when
"010"
=>
Byte2_o
<=
Byte0_i
;
when
"011"
=>
Byte2_o
<=
Byte1_i
;
when
"100"
=>
Byte2_o
<=
Byte5_i
;
when
others
=>
Byte2_o
<=
Byte2_i
;
end
case
;
end
process
;
process
(
sel
,
Byte0_i
,
Byte1_i
,
Byte2_i
,
Byte3_i
,
Byte4_i
)
begin
case
sel
is
when
"000"
=>
Byte3_o
<=
Byte3_i
;
when
"001"
=>
Byte3_o
<=
Byte2_i
;
when
"010"
=>
Byte3_o
<=
Byte1_i
;
when
"011"
=>
Byte3_o
<=
Byte0_i
;
when
"100"
=>
Byte3_o
<=
Byte4_i
;
when
others
=>
Byte3_o
<=
Byte3_i
;
end
case
;
end
process
;
process
(
sel
,
Byte4_i
,
Byte5_i
,
Byte6_i
,
Byte7_i
,
Byte3_i
)
begin
case
sel
is
when
"000"
=>
Byte4_o
<=
Byte4_i
;
when
"001"
=>
Byte4_o
<=
Byte5_i
;
when
"010"
=>
Byte4_o
<=
Byte6_i
;
when
"011"
=>
Byte4_o
<=
Byte7_i
;
when
"100"
=>
Byte4_o
<=
Byte3_i
;
when
others
=>
Byte4_o
<=
Byte4_i
;
end
case
;
end
process
;
process
(
sel
,
Byte4_i
,
Byte5_i
,
Byte6_i
,
Byte7_i
,
Byte2_i
)
begin
case
sel
is
when
"000"
=>
Byte5_o
<=
Byte5_i
;
when
"001"
=>
Byte5_o
<=
Byte4_i
;
when
"010"
=>
Byte5_o
<=
Byte7_i
;
when
"011"
=>
Byte5_o
<=
Byte6_i
;
when
"100"
=>
Byte5_o
<=
Byte2_i
;
when
others
=>
Byte5_o
<=
Byte5_i
;
end
case
;
end
process
;
process
(
sel
,
Byte4_i
,
Byte5_i
,
Byte6_i
,
Byte7_i
,
Byte1_i
)
begin
case
sel
is
when
"000"
=>
Byte6_o
<=
Byte6_i
;
when
"001"
=>
Byte6_o
<=
Byte7_i
;
when
"010"
=>
Byte6_o
<=
Byte4_i
;
when
"011"
=>
Byte6_o
<=
Byte5_i
;
when
"100"
=>
Byte6_o
<=
Byte1_i
;
when
others
=>
Byte6_o
<=
Byte6_i
;
end
case
;
end
process
;
process
(
sel
,
Byte4_i
,
Byte5_i
,
Byte6_i
,
Byte7_i
,
Byte0_i
)
begin
case
sel
is
when
"000"
=>
Byte7_o
<=
Byte7_i
;
when
"001"
=>
Byte7_o
<=
Byte6_i
;
when
"010"
=>
Byte7_o
<=
Byte5_i
;
when
"011"
=>
Byte7_o
<=
Byte4_i
;
when
"100"
=>
Byte7_o
<=
Byte0_i
;
when
others
=>
Byte7_o
<=
Byte7_i
;
end
case
;
end
process
;
Byte0_i
<=
d_i
(
7
downto
0
);
Byte1_i
<=
d_i
(
15
downto
8
);
Byte2_i
<=
d_i
(
23
downto
16
);
Byte3_i
<=
d_i
(
31
downto
24
);
Byte4_i
<=
d_i
(
39
downto
32
);
Byte5_i
<=
d_i
(
47
downto
40
);
Byte6_i
<=
d_i
(
55
downto
48
);
Byte7_i
<=
d_i
(
63
downto
56
);
d_o
(
7
downto
0
)
<=
Byte0_o
;
d_o
(
15
downto
8
)
<=
Byte1_o
;
d_o
(
23
downto
16
)
<=
Byte2_o
;
d_o
(
31
downto
24
)
<=
Byte3_o
;
d_o
(
39
downto
32
)
<=
Byte4_o
;
d_o
(
47
downto
40
)
<=
Byte5_o
;
d_o
(
55
downto
48
)
<=
Byte6_o
;
d_o
(
63
downto
56
)
<=
Byte7_o
;
end
Behavioral
;
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