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VME64x core
Commit 92f0bc34 authored by dpedrett's avatar dpedrett
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vme64x core after the review. Program ID: 0x5a. 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@189 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/vme64x-core/rtl/VME64xCore_Top.vhd
View file @ 92f0bc34
......@@ -77,8 +77,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -97,13 +97,33 @@
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME64xCore_Top is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
generic(
-- clock period (ns)
g_clock : integer := c_clk_period; -- 100 MHz
--WB data width:
g_wb_data_width : integer := c_width; -- must be 32 or 64
--WB address width:
g_wb_addr_width : integer := c_addr_width; -- 64 or less
-- CRAM
g_cram_size : integer := c_CRAM_SIZE;
-- Board ID; each board shall have an unique ID. eg: SVEC_ID = 408.
-- loc: 0x33, 0x37, 0x3B, 0x3F CR space
g_BoardID : integer := c_SVEC_ID; -- 4 bytes: 0x00000198
-- Manufacturer ID: eg the CERN ID is 0x080030
-- loc: 0x27, 0x2B, 0x2F CR space
g_ManufacturerID : integer := c_CERN_ID; -- 3 bytes: 0x080030
-- Revision ID
-- loc: 0x43, 0x47, 0x4B, 0x4F CR space
g_RevisionID : integer := c_RevisionID; -- 4 bytes: 0x00000001
-- Program ID: this is the firmware ID
-- loc: 0x7f CR space
g_ProgramID : integer := 90 -- 1 byte : 0x5a
-- The default values can be found in the vme64x_pack
);
port(
clk_i : in std_logic;
......@@ -141,13 +161,13 @@
VME_RETRY_OE_o : out std_logic;
-- WishBone
DAT_i : in std_logic_vector(g_width - 1 downto 0);
DAT_o : out std_logic_vector(g_width - 1 downto 0);
ADR_o : out std_logic_vector(g_addr_width - 1 downto 0);
DAT_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
DAT_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
ADR_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
SEL_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
......@@ -156,9 +176,10 @@
-- IRQ Generator
INT_ack_o : out std_logic; -- when the IRQ controller acknowledges the Interrupt
-- cycle it sends a pulse to the IRQ Generator
IRQ_i : in std_logic; -- Interrupt request; the IRQ Generator sends a pulse to
-- the IRQ Controller and it asserts one of the IRQ lines.
-- Add by Davide for debug:
IRQ_i : in std_logic; -- Interrupt request; the IRQ Generator/your Wb application
-- sends a pulse to the IRQ Controller which asserts one of
-- the IRQ lines.
-- Added by Davide for debug:
debug : out std_logic_vector(7 downto 0)
);
......@@ -171,7 +192,7 @@
architecture RTL of VME64xCore_Top is
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(g_CRAM_SIZE)-1 downto 0);
signal s_CRAMaddr : std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(11 downto 0);
......@@ -183,7 +204,6 @@
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
signal s_VME_DATA_b : std_logic_vector(31 downto 0);
signal s_DATi_sample : std_logic_vector(g_width - 1 downto 0);
signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
......@@ -211,27 +231,25 @@
signal s_reset_flag : std_logic;
signal s_Sw_Reset : std_logic;
signal s_ModuleEnable : std_logic;
signal s_MBLT_Endian : std_logic_vector(2 downto 0);
signal s_Endian : std_logic_vector(2 downto 0);
signal s_BAR : std_logic_vector(4 downto 0);
signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
signal s_W32 : std_logic;
signal s_IRQ : std_logic;
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
signal VME_AS_n_oversampled1 : std_logic; -- for the IRQ_Controller
signal VME_LWORD_n_oversampled : std_logic;
--signal VME_LWORD_n_oversampled : std_logic;
signal VME_WRITE_n_oversampled : std_logic;
signal VME_DS_n_oversampled : std_logic_vector(1 downto 0);
signal VME_DS_n_oversampled_1 : std_logic_vector(1 downto 0);
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_ADDR_oversampled : std_logic_vector(31 downto 1);
signal VME_DATA_oversampled : std_logic_vector(31 downto 0);
signal VME_AM_oversampled : std_logic_vector(5 downto 0);
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_IACK_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
signal s_reg_1 : std_logic_vector(1 downto 0);
signal s_reg_2 : std_logic_vector(1 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -241,36 +259,6 @@ begin
-- metastability problems. With 3 samples the probability of metastability problem will
-- be very low but of course the transfer rate will be slow down a little.
AMinputSample : RegInputSample
generic map(
width => 6
)
port map(
reg_i => VME_AM_i,
reg_o => VME_AM_oversampled,
clk_i => clk_i
);
DATAinputSample : RegInputSample
generic map(
width => 32
)
port map (
reg_i => VME_DATA_i,
reg_o => VME_DATA_oversampled,
clk_i => clk_i
);
ADDRinputSample : RegInputSample
generic map(
width => 31
)
port map(
reg_i => VME_ADDR_i,
reg_o => VME_ADDR_oversampled,
clk_i => clk_i
);
GAinputSample : RegInputSample
generic map(
width => 6
......@@ -281,47 +269,25 @@ begin
clk_i => clk_i
);
DSinputSample : RegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled,
clk_i => clk_i
);
-- DSinputSample : RegInputSample
RegInputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_reg_1 <= VME_DS_n_i;
s_reg_2 <= s_reg_1;
VME_DS_n_oversampled <= s_reg_2;
end if;
end process;
-- to avoid timing problem during BLT and MBLT accesses
DSinputSample1 : DoubleRegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled_1,
clk_i => clk_i
);
VME_DS_n_oversampled_1 <= s_reg_2;
WRITEinputSample : SigInputSample
port map(
sig_i => VME_WRITE_n_i,
sig_o => VME_WRITE_n_oversampled,
clk_i => clk_i
);
LWORDinputSample : SigInputSample
port map(
sig_i => VME_LWORD_n_i,
sig_o => VME_LWORD_n_oversampled,
clk_i => clk_i
);
ASinputSample1 : DoubleSigInputSample -- for the IRQ_Controller
port map(
sig_i => VME_AS_n_i,
sig_o => VME_AS_n_oversampled1,
clk_i => clk_i
);
ASinputSample : SigInputSample
port map(
......@@ -360,9 +326,10 @@ begin
Inst_VME_bus: VME_bus
generic map(
g_width => g_width,
g_addr_width => g_addr_width,
g_CRAM_SIZE => g_CRAM_SIZE
g_clock => g_clock,
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width,
g_cram_size => g_cram_size
)
port map(
clk_i => clk_i,
......@@ -371,7 +338,7 @@ begin
VME_RST_n_i => VME_RST_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_LWORD_n_o => VME_LWORD_n_o,
VME_LWORD_n_i => VME_LWORD_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => VME_WRITE_n_oversampled,
......@@ -380,21 +347,21 @@ begin
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
VME_ADDR_i => VME_ADDR_oversampled,
VME_ADDR_i => VME_ADDR_i,
VME_ADDR_o => VME_ADDR_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_DATA_i => VME_DATA_oversampled,
VME_DATA_i => VME_DATA_i,
VME_DATA_o => s_VME_DATA_VMEbus,
VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_oversampled,
VME_AM_i => VME_AM_i,
VME_IACK_n_i => VME_IACK_n_oversampled,
-- WB
memReq_o => STB_o,
memAckWB_i => ACK_i,
wbData_o => DAT_o,
wbData_i => s_DATi_sample,
wbData_i => DAT_i,
locAddr_o => ADR_o,
wbSel_o => SEL_o,
RW_o => s_RW,
......@@ -402,15 +369,6 @@ begin
err_i => ERR_i,
rty_i => RTY_i,
stall_i => STALL_i,
-- FIFO signals; the FIFO is not implemented in this
-- base version of the core so the relative signals
-- are "open"
psize_o => open,
VMEtoWB => open,
WBtoVME => open,
FifoMux => open,
transfer_done_i => '1',
transfer_done_o => open,
-- CR/CSR signals
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
......@@ -433,19 +391,18 @@ begin
Ader6 => s_Ader6,
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
MBLT_Endian_i => s_MBLT_Endian,
Endian_i => s_Endian,
Sw_Reset => s_Sw_Reset,
W32 => s_W32,
BAR_i => s_BAR,
numBytes => s_bytes,
transfTime => s_time,
-- debug
leds => debug
);
---------------------------------------------------------------------------------
-- output
VME_IRQ_o <= not s_VME_IRQ_n_o; --The buffers will invert again the logic level
VME_IRQ_o <= not s_VME_IRQ_n_o; --The buffers will invert again the logic level
WE_o <= not s_RW;
reset_o <= s_reset;
INT_ack_o <= s_VME_DTACK_IRQ;
......@@ -463,16 +420,16 @@ begin
-- Interrupter
Inst_VME_IRQ_Controller: VME_IRQ_Controller port map(
clk_i => clk_i,
reset => s_reset_IRQ, -- asserted when low
reset_n_i => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_AS1_n_i => VME_AS_n_oversampled1,
VME_AS1_n_i => VME_AS_n_i,
VME_DS_n_i => VME_DS_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_oversampled,
VME_ADDR_123 => VME_ADDR_oversampled(3 downto 1),
INT_Level => s_INT_Level,
INT_Vector => s_INT_Vector ,
INT_Req => s_IRQ,
VME_LWORD_n_i => VME_LWORD_n_i,
VME_ADDR_123_i => VME_ADDR_i(3 downto 1),
INT_Level_i => s_INT_Level,
INT_Vector_i => s_INT_Vector ,
INT_Req_i => s_IRQ,
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => s_VME_DTACK_IRQ,
......@@ -486,8 +443,13 @@ begin
--CR/CSR space
Inst_VME_CR_CSR_Space: VME_CR_CSR_Space
generic map(
g_CRAM_SIZE => g_CRAM_SIZE,
g_width => g_width
g_cram_size => g_cram_size,
g_wb_data_width => g_wb_data_width,
g_CRspace => c_cr_array,
g_BoardID => g_BoardID,
g_ManufacturerID => g_ManufacturerID,
g_RevisionID => g_RevisionID,
g_ProgramID => g_ProgramID
)
port map(
clk_i => clk_i,
......@@ -515,28 +477,14 @@ begin
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
Sw_Reset => s_Sw_Reset,
W32 => s_W32,
MBLT_Endian_o => s_MBLT_Endian,
Endian_o => s_Endian,
BAR_o => s_BAR,
INT_Level => s_INT_Level,
numBytes => s_bytes,
transfTime => s_time,
INT_Vector => s_INT_Vector
);
------------------------------------------------------------------------
-- This process registers the WB data input; this is a warranty that this
-- data will be stable during all the time the VME_bus component needs to
-- transfers its to the VME bus.
process(clk_i)
begin
if rising_edge(clk_i) then
if ACK_i = '1' then
s_DATi_sample <= DAT_i;
end if;
end if;
end process;
------------------------------------------------------------------------
end RTL;
--===========================================================================
-- Architecture end
......
hdl/vme64x-core/rtl/VME_Access_Decode.vhd
View file @ 92f0bc34
......@@ -5,7 +5,7 @@
--_________________________________________________________________________________
-- File: VME_Access_Decode.vhd
--_________________________________________________________________________________
-- Description: This component check if the board is addressed and if it is, allows
-- Description: This component checks if the board is addressed and if it is, allows
-- the access to CR/CSR space by asserting the Confaccess signal, or allows the access
-- to WB bus by asserting the CardSel signal.
--
......@@ -17,7 +17,7 @@
-- To Access the Wb bus we have 7 functions; only one at time can be selected. If one of
-- these functions is selected the CardSel signal is asserted (this is the responding Slave).
-- To access the Wb bus we need to decode the AM and the address lines; so as shown in
-- the block diagram the main component are two: VME_Funct_Match, VME_Am_Match.
-- the block diagram the main components are two: VME_Funct_Match, VME_Am_Match.
-- ___________________________________________
-- | VME_Access_Decode.vhd |
......@@ -63,12 +63,12 @@
-- This bit is '1' during A64 and 2e access.
-- DFS = Dynamic Function Decoder: a '1' here means this function can be used
-- to decode different address length (eg. A16 or A24 or A32) so the mask bits
-- should be all '1' !!!
-- should be all '1'.
--
-- AMCAP[63:0]
-- 6 AM lines --> 2**6 = 64 different configurations
-- This register is 64 bits wide and each bit rappresents one AM configuration.
-- If the bit is '1' it means that the corrisponding AM is supported by this function.
-- If the bit is '1' it means that the corresponding AM is supported by this function.
-- If the corresponding ADEM's DFS is 0, only the AMCAP's bits with the same address
-- width must be '1'.
-- If the corresponding ADEM's DFS is 1, one or more AMCAP's bits can be '1'
......@@ -80,17 +80,17 @@
-- XAMCAP[255:0]
-- 8 XAM lines --> 2**8 = 256 different configurations
-- This register is 256 bits wide and each bit rappresents one XAM configuration.
-- If the bit is '1' it means that the corrisponding XAM is supported
-- If the bit is '1' it means that the corresponding XAM is supported
-- by this function.
-- This register is used during the decode phase if the XAM bit is asserted (1).
-- Before accessing the board the VME Master must write the ADER registers. Of course for
-- writing properly the ADER the VME Master need to know the corrisponding ADEM and check if
-- writing properly the ADER the VME Master needs to know the corresponding ADEM and check if
-- EFM or DFS bits are asserted. The VME Master can read also
-- the AMCAP and XAMCAP and check the access mode supported by each function.
--
-- eg.1 lets imagine that we want be able to access different storage device; we can assign
-- eg.1 let's imagine that we want to access different storage device; we can assign
-- one base address and one function at each storage.
-- Now the VME Master has to write the base address of each storage in the corrisponding
-- Now the VME Master has to write the base address of each storage in the corresponding
-- ADER's compare bits and after this operation each function decodes the access to
-- the corresponding storage.
-- eg.2 this example is relative to our application; the vme64x interface has to transfer
......@@ -103,7 +103,7 @@
-- function3 and function4 --> A64, A64_BLT, A64_MBLT
-- function5 and function6 --> 2eVME and 2eSST modes
-- Note that if the address is 64 bits wide we need of two ADER and two ADEM to decode the
-- address so we need two functions. (see also EFM bit definition)
-- Of course you can mix these two example and set up one system with more storage devices
-- each with its base address and to assign each storage more than one function to access it
-- with all the access modes.
......@@ -118,8 +118,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--________________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -286,7 +286,7 @@ begin
if s_func_sel(i) = '1' then
CardSel <= '1';
Base_Addr <= s_nx_base_addr;
exit;
-- exit; in this case the exit statement is useless
end if;
end loop;
end if;
......
hdl/vme64x-core/rtl/VME_Am_Match.vhd
View file @ 92f0bc34
......@@ -6,12 +6,13 @@
-- File: VME_Am_Match.vhd
--______________________________________________________________________________________
-- Description: this component checks if the AM match.
-- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but
-- If it is the correspondent AmMatch's bit is asserted. This condition is necessary but
-- not sufficient to select the function and access the board.
-- If DFS = '0' the function supports only access modes with the same address width;
-- 1 function --> only 1 address width;
-- with address width I mean A16, A24, A32 or A64.
-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
-- If DFS = '1' the function supports access modes with different address wide so AmMatch(i)
-- If DFS = '1' the function supports access modes with different address widths so AmMatch(i)
-- is asserted only if ADER[7:2] = AM and s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the
-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal
......@@ -20,8 +21,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -89,7 +90,6 @@ architecture Behavioral of VME_Am_Match is
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
signal debugAm : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -127,32 +127,27 @@ begin
if rising_edge(clk_i) then
if mainFSMreset = '1' or reset = '1' then
AmMatch <= (others => '0');
debugAm <= 0;
elsif decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
debugAm <= 1;
AmMatch(i) <= s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
else
if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 2;
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= '0';
end if;
end if;
else
if s_FUNC_ADER(i)(XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 3;
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
else
AmMatch(i) <= s_amcap_match(i);
debugAm <= 4;
AmMatch(i) <= s_amcap_match(i);
end if;
end if;
end loop;
......
hdl/vme64x-core/rtl/VME_CRAM.vhd
View file @ 92f0bc34
......@@ -10,8 +10,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd
View file @ 92f0bc34
......@@ -6,9 +6,9 @@
-- File: VME_CR_CSR_Space.vhd
--________________________________________________________________________________________________
-- Description:
-- Please note that only every fourth location in the CR/CSR space is used so is possible write
-- Please note that only every fourth location in the CR/CSR space is used so it is possible write
-- the CSR/CRAM selecting the data transfer mode D08_Byte3, D16_Byte23, D32. If other data transfer
-- mode are selected the write operation will not be successful.
-- modes are selected the write operation will not be successful.
-- If the Master access the board for a reading operation with data transfer type different than
-- D08_Byte3, D16_Byte23, D32 the data that will be read is 0.
-- width = 1 byte
......@@ -44,14 +44,14 @@
-- |_________________________________| 0x00
--
-- If the size of the register is bigger than 1 byte, (eg: ADER is 4 bytes) these bytes are
-- storaged in the BIG_ENDIAN ORDER!!
-- stored in the BIG_ENDIAN ORDER.
-- User CR and User CSR are not implemented.
-- In addition to the registers of the table 10-13 in the CSR space you can find:
-- _
-- IRQ_Vector --> 0x7FF5F |--> for the Interrupter
-- IRQ_level --> 0x7FF5B _|
--
-- MBLT_Endian --> 0x7FF53 --> for the swapper
-- Endian --> 0x7FF53 --> for the swapper
--
-- WB32bits --> 0x7FF33 --> if the bit 0 is '1' it means that the WB data bus is 32 bit
-- _
......@@ -96,8 +96,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -123,15 +123,20 @@ use work.VME_CSR_pack.all;
--===========================================================================
entity VME_CR_CSR_Space is
generic(
g_CRAM_SIZE : integer := c_CRAM_SIZE;
g_width : integer := c_width
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array := c_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID; -- 0x00080030
g_RevisionID : integer := c_RevisionID; -- 0x00000001
g_ProgramID : integer := 96 -- 0x00000060
);
Port ( -- VMEbus.vhd signals
clk_i : in std_logic;
reset : in std_logic;
CR_addr : in std_logic_vector (11 downto 0);
CR_data : out std_logic_vector (7 downto 0);
CRAM_addr : in std_logic_vector (f_log2_size(g_CRAM_SIZE)-1 downto 0);
CRAM_addr : in std_logic_vector (f_log2_size(g_cram_size)-1 downto 0);
CRAM_data_o : out std_logic_vector (7 downto 0);
CRAM_data_i : in std_logic_vector (7 downto 0);
CRAM_Wen : in std_logic;
......@@ -155,8 +160,7 @@ entity VME_CR_CSR_Space is
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
MBLT_Endian_o : out std_logic_vector(2 downto 0);
Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
-- IRQ_controller signals
INT_Level : out std_logic_vector(7 downto 0);
......@@ -171,6 +175,7 @@ architecture Behavioral of VME_CR_CSR_Space is
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CR_Space : t_cr_array(2**12 downto 0);
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
......@@ -190,11 +195,12 @@ s_odd_parity <= VME_GA_oversampled(5) xor VME_GA_oversampled(4) xor
-- master accesses its CR/CSR space and we can see a time out error in the VME bus.
s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o(0));
--------------------------------------------------------------------------------
s_CR_Space <= f_set_CR_space(g_BoardID, g_CRspace, g_ManufacturerID, g_RevisionID, g_ProgramID);
-- CR
process(clk_i)
begin
if rising_edge(clk_i) then
CR_data <= c_cr_array(to_integer(unsigned(CR_addr)));
CR_data <= s_CR_Space(to_integer(unsigned(CR_addr))); -- c_cr_array(to_integer(unsigned(CR_addr)));
end if;
end process;
--------------------------------------------------------------------------------
......@@ -270,14 +276,14 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
when to_integer("00" & c_IRQ_level_addr(18 downto 2)) =>
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) =>
s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_Endian_addr(18 downto 2)) =>
s_CSRarray(Endian) <= s_locDataIn(7 downto 0);
when others => null;
end case;
else
if g_width = 32 then
if g_wb_data_width = 32 then
s_CSRarray(WB32bits) <= x"01";
else
s_CSRarray(WB32bits) <= x"00";
......@@ -342,7 +348,7 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
when "00" & c_FUNC0_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_3);
when "00" & c_IRQ_Vector_addr (18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_Vector);
when "00" & c_IRQ_level_addr(18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_level);
when "00" & c_MBLT_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(MBLT_Endian);
when "00" & c_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(Endian);
when "00" & c_TIME0_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME0_ns);
when "00" & c_TIME1_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME1_ns);
when "00" & c_TIME2_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME2_ns);
......@@ -360,13 +366,13 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
INT_Vector <= std_logic_vector(s_CSRarray(IRQ_Vector));
CSRdata <= std_logic_vector(s_CSRdata);
s_CrCsrOffsetAddr <= unsigned(CrCsrOffsetAddr);
-- Generate a vector of 8 array (unsigned 32 bits).
GADER_1 : for i in 0 to 7 generate
GADER_2 : for h in 0 to 3 generate
s_FUNC_ADER(i)(8*(4-h)-1 downto 8*(3-h)) <= s_CSRarray(FUNC0_ADER_3+(h+i*4));
end generate GADER_2;
end generate GADER_1;
-- to the decoder
Ader0 <= std_logic_vector(s_FUNC_ADER(0));
Ader1 <= std_logic_vector(s_FUNC_ADER(1));
Ader2 <= std_logic_vector(s_FUNC_ADER(2));
......@@ -376,16 +382,15 @@ s_BARerror <= not(s_BAR_o(4) or s_BAR_o(3)or s_BAR_o(2) or s_BAR_o(1) or s_BAR_o
Ader6 <= std_logic_vector(s_FUNC_ADER(6));
Ader7 <= std_logic_vector(s_FUNC_ADER(7));
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Endian_o <= std_logic_vector(s_CSRarray(Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
W32 <= s_CSRarray(WB32bits)(0);
BAR_o <= s_BAR_o;
s_BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
---------------------------------------------------------------------------------------------------------------
-- CRAM:
CRAM_1 : VME_CRAM
generic map(dl => 8,
al => f_log2_size(g_CRAM_SIZE)
al => f_log2_size(g_cram_size)
)
port map(clk => clk_i,
we => CRAM_Wen,
......
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 92f0bc34
......@@ -33,7 +33,7 @@ use IEEE.numeric_std.all;
use work.vme64x_pack.all;
package VME_CR_pack is
-- type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
constant c_amcap : std_logic_vector(63 downto 0) :=
"1111111100000000001100100000000000000000000100001111111100001011";
constant c_amcap0 : std_logic_vector(63 downto 0) :=
......@@ -138,26 +138,26 @@ package VME_CR_pack is
16#07# => x"43",
--Ascii "R"
16#08# => x"52",
--Manufacturer's ID
16#09# => x"01",
16#0A# => x"02",
16#0B# => x"03",
--board id
--Manufacturer's ID -- for CERN: 0x080030
16#09# => x"08",
16#0A# => x"00",
16#0B# => x"30",
--board id -- eg: SVEC ID = 0x000198
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
16#0F# => x"03",
--Rev id
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
16#13# => x"03",
16#10# => x"00",
16#11# => x"00",
16#12# => x"00",
16#13# => x"02",
--Point to ascii null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"59",
16#1F# => x"5a",
--Offset to BEG_USER_CR
16#20# => x"00",
16#21# => x"00",
......
hdl/vme64x-core/rtl/VME_Funct_Match.vhd
View file @ 92f0bc34
......@@ -6,11 +6,11 @@
-- File: VME_Funct_Match.vhd
--_________________________________________________________________________________________
-- Description: this component compares the Address with the ADER using the mask bits and
-- if the base address match it asserts the corrisponding bit in the FunctMatch vector and it
-- latches the base address that will be subtract to the Address before accessing the WB bus.
-- if the base address match it asserts the corresponding bit in the FunctMatch vector and it
-- latches the base address that will be subtracted to the Address before accessing the WB bus.
-- FunctMatch /= 0 is necessary but not sufficient to select one function and to access the board,
-- indeed also the AM has to be checked (VME_AM_Match.vhd component).
-- For better understanding how this component works here one example:
-- For better understanding how this component works here is one example:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master writes the ADERi = 0xc0000024
......@@ -26,11 +26,11 @@
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- Now with the same ADEMi the master access with A16 mode:
-- Now with the same ADEMi the master accesses with A16 mode:
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- The Master want access at the location 0x08: Address= 0x0000c008
-- The Master writes the ADERi = 0x0000c0a4
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[15:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -49,7 +49,7 @@
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -66,7 +66,7 @@
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- ADEMi = 0xff000000 --> DFS = '0'
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- The Master wants to access the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEM[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -80,9 +80,9 @@
-- The Master can access!
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- The Master writes the ADERi = 0x0000c0a4
-- ADEMi = 0xff000000 --> DFS = '0' -- The Master can't change the CR space!!
-- The Master want access at the location 0x08: Address= 0x0000c008
-- The Master wants to access the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected:
-- ADEM[15:8] = 0 --> FunctMatch(i) <= '0'
......@@ -97,7 +97,7 @@
-- A VME Master takes the ownership of the VMEbus for accessing another board:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master want access at the location 0x0008: Address= 0xc0000008
-- The Master wants to access the location 0x0008: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
......@@ -144,8 +144,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.01
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -205,7 +205,6 @@ architecture Behavioral of VME_Funct_Match is
signal s_FUNC_ADER_64, s_FUNC_ADEM_64: t_FUNC_64b_array;
signal s_isprev_func64 : std_logic_vector(7 downto 0);
signal s_locAddr : unsigned(63 downto 0);
signal debugfunct : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -218,7 +217,6 @@ begin
if mainFSMreset = '1' or reset = '1' then
FunctMatch <= (others => '0');
Nx_Base_Addr <= (others => '0');
debugfunct <= 0;
elsif decode = '1' then
for i in FunctMatch'range loop
......@@ -228,8 +226,7 @@ begin
(s_FUNC_ADEM_64(i)(63 downto 10) /= 0) then
if (s_FUNC_ADER_64(i)(63 downto 10) and s_FUNC_ADEM_64(i)(63 downto 10)) =
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
debugfunct <= 1;
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
FunctMatch(i) <= '1';
Nx_Base_Addr(63 downto 10) <= std_logic_vector(s_FUNC_ADER_64(i)(63 downto 10));
Nx_Base_Addr(9 downto 0) <= (others => '0');
......@@ -244,8 +241,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(31 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(31 downto 8));
Nx_Base_Addr(63 downto 32) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 2;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......@@ -256,8 +252,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(23 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(23 downto 8));
Nx_Base_Addr(63 downto 24) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 3;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......@@ -268,8 +263,7 @@ begin
FunctMatch(i) <= '1';
Nx_Base_Addr(15 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(15 downto 8));
Nx_Base_Addr(63 downto 16) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 4;
Nx_Base_Addr(7 downto 0) <= (others => '0');
end if;
end if;
......
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd
View file @ 92f0bc34
......@@ -33,12 +33,12 @@
-- |--| IACKOUT2 |<-|
-- | |__________| |
-- | |
-- | _________ | _________ _________ _________ __________
-- |-->| IDLE |--->| IRQ |-->| WAIT_AS |-->| WAIT_DS |-->| LATCH_DS |-->--|
-- |_________| |_________| |_________| |_________| |__________| |
-- | | |
-- | | _________ _________ |
-- | |---------<------------| IACKOUT1| <--| ACK_INT |<-------|
-- | _________ | _________ _________ _________
-- |-->| IDLE |--->| IRQ |-->| WAIT_AS |-->| WAIT_DS |---------------->|
-- |_________| |_________| |_________| |_________| |
-- | | |
-- | | _________ _________ |
-- | |---------<------------| IACKOUT1| <--| CHECK |<----|
-- | |_________| |_________|
-- | __________ __________ |
-- |--<-----------------| DTACK |<--| DATA_OUT |---<----|
......@@ -46,38 +46,44 @@
--
-- The interrupter wait the IACKIN falling edge in the IRQ state, so if the interrupter
-- don't have interrupt pending for sure it will not respond because it is in IDLE.
-- If the slave module does not have an interrupt pending (IDLE state) and it receives
-- a falling edge on the IACKIN, it shall pass the falling edge through the daisy chain.
-- To obtain this the IACKOUT2 state has been added.
-- Time constraint:
--
-- Time constraint n° 35:
-- Clk _____ _____ _____ _____ _____ _____
-- _____| |_____| |_____| |_____| |_____| |_____| |_____
-- VME_AS1_n_i ______________________________________________________________________
-- ______|
-- VME_AS_n_i __________________________________________________________
-- __________________|
-- AS_RisingEdge ___________
-- __________________| |______________________________________________
-- s_IACKOUT ______________________________________________________________________
-- ______|
-- VME_IACKOUT_o __________________________________________________________
-- __________________|
-- VME_AS1_n_i ____________________________________________________________________
-- ________|
-- VME_AS_n_i ___________________________________
-- _________________________________________|
-- s_AS_RisingEdge ___________
-- _____________________________________________________| |___________
-- s_IACKOUT ____________________________________________________________________
-- ________|
-- VME_IACKOUT_o ____________________________________________________________________
-- ________|
--
-- ______________________________ _____________________________________________
-- IACKOUT 1/2 \/ IDLE/IRQ
-- ------------------------------/\---------------------------------------------
-- _________________________________________________________________ __________
-- IACKOUT 1/2 \/ IDLE/IRQ
-- -----------------------------------------------------------------/\----------
--
-- To avoid the time constraint indicated with the number 35 fig. 55 pag. 183 in the
-- "VMEbus Specification" ANSI/IEEE STD1014-1987, is necessary generate the VME_AS1_n_i
-- signal who is the AS signal sampled only two times and not 3 times as the VME_AS_n_i
-- signal, and assign this signal to the s_IACKOUT signal when the fsm is in the
-- IACKOUTx state.
-- To respect the time constraint indicated with the number 35 fig. 55 pag. 183 in the
-- "VMEbus Specification" ANSI/IEEE STD1014-1987, is necessary to generate the VME_AS1_n_i
-- signal which is the AS signal not sampled, and assign this signal to the s_IACKOUT
-- signal when the fsm is in the IACKOUTx state.
--
-- The LWORD* input is not used now, since this is a D08(O) Interrupter (see Table 31
-- page 157 VMEbus specification).
-- Since this is a D08 interrupter we do not need to monitor the LWORD* and DS1* lines
-- and the Vector (1 byte) is outputted in the D00-D07 data lines.
--____________________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--_____________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -101,16 +107,16 @@ use work.vme64x_pack.all;
--===========================================================================
entity VME_IRQ_Controller is
Port ( clk_i : in std_logic;
reset : in std_logic;
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_AS1_n_i : in std_logic; -- this is the AS* not triple sampled
VME_DS_n_i : in std_logic_vector (1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123 : in std_logic_vector (2 downto 0);
INT_Level : in std_logic_vector (7 downto 0);
INT_Vector : in std_logic_vector (7 downto 0);
INT_Req : in std_logic;
VME_ADDR_123_i : in std_logic_vector (2 downto 0);
INT_Level_i : in std_logic_vector (7 downto 0);
INT_Vector_i : in std_logic_vector (7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector (6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
......@@ -123,29 +129,22 @@ end VME_IRQ_Controller;
--===========================================================================
architecture Behavioral of VME_IRQ_Controller is
--input signals
signal INT_Req_sample : std_logic;
signal s_INT_Req_sample : std_logic;
--output signals
signal s_DTACK : std_logic;
signal s_DTACK_OE : std_logic;
signal s_DTACK_OE_o : std_logic;
signal s_DataDir : std_logic;
signal s_IACKOUT : std_logic;
signal s_IACKOUT_o : std_logic;
signal s_enable : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0);
signal s_Data : std_logic_vector(31 downto 0);
--
signal AS_FallingEdge : std_logic;
signal AS_RisingEdge : std_logic;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, ACK_INT, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal currs, nexts : t_MainFSM;
signal s_AS_FallingEdge : std_logic;
signal s_AS_RisingEdge : std_logic;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, CHECK, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal s_currs, s_nexts : t_MainFSM;
signal s_ack_int : std_logic;
signal s_resetIRQ : std_logic;
signal s_enableIRQ : std_logic;
signal VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal VME_DS_latched : std_logic_vector(1 downto 0);
signal DSlatch : std_logic;
signal ADDRmatch : std_logic;
signal s_VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal s_VME_DS_latched : std_logic_vector(1 downto 0);
signal s_ADDRmatch : std_logic;
signal s_FSM_IRQ : t_FSM_IRQ;
--===========================================================================
-- Architecture begin
--===========================================================================
......@@ -154,68 +153,55 @@ begin
-- Input sampling and edge detection
ASrisingEdge : RisEdgeDetection
port map (
sig_i => VME_AS1_n_i,
sig_i => VME_AS_n_i,
clk_i => clk_i,
RisEdge_o => AS_RisingEdge
RisEdge_o => s_AS_RisingEdge
);
ASfallingEdge : FallingEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
FallEdge_o => AS_FallingEdge
FallEdge_o => s_AS_FallingEdge
);
INT_ReqinputSample : FlipFlopD
port map(
sig_i => INT_Req,
sig_o => INT_Req_sample,
clk_i => clk_i,
reset => '0',
enable => s_enable
);
INT_ReqinputSample : process(clk_i)
begin
if rising_edge(clk_i) then
if s_enable = '1' then
s_INT_Req_sample <= INT_Req_i;
end if;
end if;
end process;
--Output registers:
DTACKOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DTACK_n_o <= s_FSM_IRQ.s_DTACK;
end if;
end process;
DTACKOutputSample : FlipFlopD
port map(
sig_i => s_DTACK,
sig_o => VME_DTACK_n_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
DataDirOutputSample : FlipFlopD
port map(
sig_i => s_DataDir,
sig_o => VME_DATA_DIR_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
IACKOUTOutputSample : FlipFlopD
port map(
sig_i => s_IACKOUT,
sig_o => s_IACKOUT_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
DTACKOEOutputSample : FlipFlopD
port map(
sig_i => s_DTACK_OE,
sig_o => s_DTACK_OE_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
DataDirOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
VME_DATA_DIR_o <= s_FSM_IRQ.s_DataDir;
end if;
end process;
DTACKOEOutputSample : process(clk_i)
begin
if rising_edge(clk_i) then
s_DTACK_OE_o <= s_FSM_IRQ.s_DTACK_OE;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
if s_resetIRQ = '1' then
if s_FSM_IRQ.s_resetIRQ = '1' then
VME_IRQ_n_o <= (others => '1');
elsif s_enableIRQ = '1' then
elsif s_FSM_IRQ.s_enableIRQ = '1' then
VME_IRQ_n_o <= s_IRQ;
end if;
end if;
......@@ -232,188 +218,152 @@ begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
currs <= IDLE;
if reset_n_i = '0' then
s_currs <= IDLE;
else
currs <= nexts;
s_currs <= s_nexts;
end if;
end if;
end process;
-- Update next state
process(currs,INT_Req_sample,VME_AS_n_i,VME_DS_n_i,s_ack_int,VME_IACKIN_n_i,AS_RisingEdge)
process(s_currs,s_INT_Req_sample,VME_AS_n_i,VME_DS_n_i,s_ack_int,VME_IACKIN_n_i,s_AS_RisingEdge)
begin
case currs is
case s_currs is
when IDLE =>
if INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
nexts <= IRQ;
if s_INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
s_nexts <= IRQ;
elsif VME_IACKIN_n_i = '0' then
nexts <= IACKOUT2;
s_nexts <= IACKOUT2;
else
nexts <= IDLE;
s_nexts <= IDLE;
end if;
when IRQ =>
if VME_IACKIN_n_i = '0' then -- Each Interrupter who is driving an interrupt request line
-- low waits for a falling edge on IACKIN input -->
-- the IRQ_Controller have to detect a falling edge on the IACKIN.
nexts <= WAIT_AS;
s_nexts <= WAIT_AS;
else
nexts <= IRQ;
s_nexts <= IRQ;
end if;
when WAIT_AS =>
if VME_AS_n_i = '0' then -- NOT USE FALLING EDGE HERE!
nexts <= WAIT_DS;
s_nexts <= WAIT_DS;
else
nexts <= WAIT_AS;
s_nexts <= WAIT_AS;
end if;
when WAIT_DS =>
if VME_DS_n_i /= "11" then
nexts <= LATCH_DS;
s_nexts <= CHECK;
else
nexts <= WAIT_DS;
s_nexts <= WAIT_DS;
end if;
when LATCH_DS =>
nexts <= ACK_INT;
when ACK_INT =>
-- when LATCH_DS => -- this state is necessary only for D16 ans D32 Interrupters
-- s_nexts <= CHECK;
-- If the interrupter is D16 or D32 add a generic number of LATCH_DS state like in the VME_bus component.
when CHECK =>
if s_ack_int = '1' then
nexts <= DATA_OUT; -- The Interrupter send the INT_Vector
s_nexts <= DATA_OUT; -- The Interrupter send the INT_Vector
else
nexts <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
s_nexts <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
end if;
when IACKOUT1 =>
if AS_RisingEdge = '1' then
nexts <= IRQ;
if s_AS_RisingEdge = '1' then
s_nexts <= IRQ;
else
nexts <= IACKOUT1;
s_nexts <= IACKOUT1;
end if;
when DATA_OUT=>
nexts <= DTACK;
s_nexts <= DTACK;
when IACKOUT2 =>
if AS_RisingEdge = '1' then
nexts <= IDLE;
if s_AS_RisingEdge = '1' then
s_nexts <= IDLE;
else
nexts <= IACKOUT2;
s_nexts <= IACKOUT2;
end if;
when DTACK=>
if AS_RisingEdge = '1' then
nexts <= IDLE;
if s_AS_RisingEdge = '1' then
s_nexts <= IDLE;
else
nexts <= DTACK;
s_nexts <= DTACK;
end if;
when others => null;
end case;
end process;
-- Update Outputs
-- Mealy FSM
process(currs,VME_AS1_n_i)
process(s_currs,VME_AS1_n_i)
begin
case currs is
s_FSM_IRQ <= c_FSM_IRQ;
case s_currs is
when IDLE =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '1';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
when IRQ =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '1';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_enableIRQ <= '1';
s_FSM_IRQ.s_resetIRQ <= '0';
when WAIT_AS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_resetIRQ <= '0';
when WAIT_DS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_resetIRQ <= '0';
-- when LATCH_DS =>
-- s_IACKOUT <= '1';
-- s_DataDir <= '0';
-- s_DTACK <= '1';
-- s_enableIRQ <= '0';
-- s_resetIRQ <= '0';
-- s_DSlatch <= '1';
-- s_DTACK_OE <= '0';
when LATCH_DS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '1';
s_DTACK_OE <= '0';
when CHECK =>
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_resetIRQ <= '0';
when ACK_INT =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when IACKOUT1 =>
s_IACKOUT <= VME_AS1_n_i;
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_IACKOUT <= VME_AS1_n_i;
when IACKOUT2 =>
s_IACKOUT <= VME_AS1_n_i;
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_IACKOUT <= VME_AS1_n_i;
when DATA_OUT=>
s_IACKOUT <= '1';
s_DataDir <= '1';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '1';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_DataDir <= '1';
s_FSM_IRQ.s_resetIRQ <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when DTACK=>
s_IACKOUT <= '1';
s_DataDir <= '1';
s_DTACK <= '0';
s_enableIRQ <= '0';
s_resetIRQ <= '1';
DSlatch <= '0';
s_DTACK_OE <= '1';
s_FSM_IRQ <= c_FSM_IRQ;
s_FSM_IRQ.s_DataDir <= '1';
s_FSM_IRQ.s_DTACK <= '0';
s_FSM_IRQ.s_DTACK_OE <= '1';
when others => null;
end case;
end process;
-- This process provides the IRQ vector
process(INT_Level)
process(INT_Level_i)
begin
case (INT_Level) is
case (INT_Level_i) is
when "00000001" => s_IRQ <= "1111110";
when "00000010" => s_IRQ <= "1111101";
when "00000011" => s_IRQ <= "1111011";
......@@ -429,10 +379,10 @@ begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
VME_ADDR_123_latched <= (others => '0');
elsif AS_FallingEdge = '1' then
VME_ADDR_123_latched <= VME_ADDR_123;
if reset_n_i = '0' then
s_VME_ADDR_123_latched <= (others => '0');
elsif s_AS_FallingEdge = '1' then
s_VME_ADDR_123_latched <= VME_ADDR_123_i;
end if;
end if;
end process;
......@@ -441,10 +391,10 @@ begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
VME_DS_latched <= (others => '0');
elsif DSlatch = '1' then
VME_DS_latched <= VME_DS_n_i;
if reset_n_i = '0' then
s_VME_DS_latched <= (others => '0');
elsif s_FSM_IRQ.s_DSlatch = '1' then
s_VME_DS_latched <= VME_DS_n_i;
end if;
end if;
end process;
......@@ -453,21 +403,24 @@ begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
ADDRmatch <= '0';
elsif unsigned(INT_Level) = unsigned(VME_ADDR_123_latched) then
ADDRmatch <= '1';
if reset_n_i = '0' then
s_ADDRmatch <= '0';
elsif unsigned(INT_Level_i) = unsigned(s_VME_ADDR_123_latched) then
s_ADDRmatch <= '1';
else
ADDRmatch <= '0';
s_ADDRmatch <= '0';
end if;
end if;
end process;
s_ack_int <= (not(VME_DS_latched(0))) and ADDRmatch; --D08 Byte3 access or D32 access
s_Data <= x"000000" & INT_Vector;
s_enable <= (not INT_Req_sample) or (not s_DTACK); -- VME_IACKIN_n_i and s_IACKOUT_o;
-- the INT_Vector is in the D0:7 lines (byte3 in big endian order)
s_ack_int <= s_ADDRmatch; --D08 Interrupter
-- s_ack_int <= (not(s_VME_DS_latched(1))) and s_ADDRmatch and (not(VME_LWORD_n_i))
-- for a D32 Interrupter
s_Data <= x"000000" & INT_Vector_i;
s_enable <= (not s_INT_Req_sample) or ((not s_FSM_IRQ.s_DTACK) and (s_AS_RisingEdge));
-- the INT_Vector is in the D0:D7 lines (byte3 in big endian order)
VME_DTACK_OE_o <= s_DTACK_OE_o;
VME_IACKOUT_n_o <= s_IACKOUT_o;
VME_IACKOUT_n_o <= s_FSM_IRQ.s_IACKOUT;
end Behavioral;
--===========================================================================
-- Architecture end
......
hdl/vme64x-core/rtl/VME_Init.vhd
View file @ 92f0bc34
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--________________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -37,42 +37,42 @@ use work.vme64x_pack.all;
-- Entity declaration
--===========================================================================
entity VME_Init is
Port ( clk_i : in std_logic;
RSTedge : inout std_logic;
CRAddr : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount : out std_logic_vector (8 downto 0);
InitInProgress : out std_logic;
BEG_USR_CR_o : out std_logic_vector (23 downto 0);
END_USR_CR_o : out std_logic_vector (23 downto 0);
BEG_USR_CSR_o : out std_logic_vector (23 downto 0);
END_USR_CSR_o : out std_logic_vector (23 downto 0);
BEG_CRAM_o : out std_logic_vector (23 downto 0);
END_CRAM_o : out std_logic_vector (23 downto 0);
FUNC0_ADEM_o : out std_logic_vector (31 downto 0);
FUNC1_ADEM_o : out std_logic_vector (31 downto 0);
FUNC2_ADEM_o : out std_logic_vector (31 downto 0);
FUNC3_ADEM_o : out std_logic_vector (31 downto 0);
FUNC4_ADEM_o : out std_logic_vector (31 downto 0);
FUNC5_ADEM_o : out std_logic_vector (31 downto 0);
FUNC6_ADEM_o : out std_logic_vector (31 downto 0);
FUNC7_ADEM_o : out std_logic_vector (31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
Port ( clk_i : in std_logic;
RSTedge_i : in std_logic;
CRAddr_i : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount_o : out std_logic_vector (8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector (23 downto 0);
END_USR_CR_o : out std_logic_vector (23 downto 0);
BEG_USR_CSR_o : out std_logic_vector (23 downto 0);
END_USR_CSR_o : out std_logic_vector (23 downto 0);
BEG_CRAM_o : out std_logic_vector (23 downto 0);
END_CRAM_o : out std_logic_vector (23 downto 0);
FUNC0_ADEM_o : out std_logic_vector (31 downto 0);
FUNC1_ADEM_o : out std_logic_vector (31 downto 0);
FUNC2_ADEM_o : out std_logic_vector (31 downto 0);
FUNC3_ADEM_o : out std_logic_vector (31 downto 0);
FUNC4_ADEM_o : out std_logic_vector (31 downto 0);
FUNC5_ADEM_o : out std_logic_vector (31 downto 0);
FUNC6_ADEM_o : out std_logic_vector (31 downto 0);
FUNC7_ADEM_o : out std_logic_vector (31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
end VME_Init;
--===========================================================================
......@@ -103,13 +103,13 @@ architecture Behavioral of VME_Init is
-- Architecture begin
--===========================================================================
begin
InitReadCount <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr);
InitReadCount_o <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr_i);
p_coreInit : process(clk_i)
begin
if rising_edge(clk_i) then
if RSTedge = '1' then
if RSTedge_i = '1' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
......@@ -151,7 +151,7 @@ begin
end process;
s_initInProgress <= '1' when (s_initReadCounter <= (424)) else '0';
InitInProgress <= s_initInProgress;
InitInProgress_o <= s_initInProgress;
s_CRadd_offset <= s_CRaddr - s_CRaddr_base;
process(s_latchCRdata, s_initReadCounter)
......
hdl/vme64x-core/rtl/VME_SharedComps.vhd
View file @ 92f0bc34
......@@ -11,8 +11,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--_______________________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/VME_Wb_master.vhd
View file @ 92f0bc34
......@@ -39,8 +39,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -64,36 +64,32 @@ use work.vme64x_pack.all;
-- Entity declaration
--===========================================================================
entity VME_Wb_master is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width
generic(g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
Port ( s_memReq : in std_logic;
Port ( memReq_i : in std_logic;
clk_i : in std_logic;
cardSel : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
BERRcondition : in std_logic;
sel : in std_logic_vector(7 downto 0);
beatCount : in std_logic_vector(8 downto 0);
locDataInSwap : in std_logic_vector(63 downto 0);
locDataOut : out std_logic_vector(63 downto 0);
rel_locAddr : in std_logic_vector(63 downto 0);
memAckWb : out std_logic;
err : out std_logic;
rty : out std_logic;
RW : in std_logic;
psize_o : out std_logic_vector(8 downto 0);
cardSel_i : in std_logic;
reset_i : in std_logic;
BERRcondition_i : in std_logic;
sel_i : in std_logic_vector(7 downto 0);
locDataInSwap_i : in std_logic_vector(63 downto 0);
locDataOut_o : out std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(63 downto 0);
memAckWb_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
RW_i : in std_logic;
stall_i : in std_logic;
rty_i : in std_logic;
err_i : in std_logic;
W32 : in std_logic;
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector(g_width - 1 downto 0);
wbData_i : in std_logic_vector(g_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_addr_width - 1 downto 0);
WBdata_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
memAckWB_i : in std_logic;
WbSel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
WbSel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
RW_o : out std_logic);
end VME_Wb_master;
......@@ -106,22 +102,22 @@ signal s_cyc : std_logic;
signal s_AckWithError : std_logic;
signal s_wbData_i : std_logic_vector(63 downto 0);
signal s_select : std_logic_vector(8 downto 0);
signal s_DATi_sample : std_logic_vector(g_wb_data_width - 1 downto 0);
--===========================================================================
-- Architecture begin
--===========================================================================
begin
s_select <= cardSel & sel;
s_select <= cardSel_i & sel_i;
s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
s_wbData_i <= std_logic_vector(resize(unsigned(s_DATi_sample),s_wbData_i'length));
-- stb handler
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '1' or mainFSMreset = '1' or (stall_i = '0' and s_cyc = '1') then
if reset_i = '1' or (stall_i = '0' and s_cyc = '1') then
memReq_o <= '0';
elsif s_memReq = '1' and cardSel = '1' and BERRcondition = '0' then
elsif memReq_i = '1' and cardSel_i = '1' and BERRcondition_i = '0' then
memReq_o <= '1';
end if;
end if;
......@@ -131,9 +127,9 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '1' or mainFSMreset = '1' or memAckWB_i = '1' then
if reset_i = '1' or memAckWB_i = '1' then
s_cyc <= '0';
elsif s_memReq = '1' and cardSel = '1' and BERRcondition = '0' then
elsif memReq_i = '1' and cardSel_i = '1' and BERRcondition_i = '0' then
s_cyc <= '1';
end if;
end if;
......@@ -143,80 +139,80 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
RW_o <= RW;
s_AckWithError <=(s_memReq and cardSel and BERRcondition);
RW_o <= RW_i;
s_AckWithError <=(memReq_i and cardSel_i and BERRcondition_i);
end if;
end process;
-- shift data and address for WB data bus 64 bits
gen64: if (g_width = 64) generate
gen64: if (g_wb_data_width = 64) generate
process(clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 3,g_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 3,g_wb_addr_width));
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
case sel is
when "10000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 56);
when "01000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
when "00100000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 40);
when "00010000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 24);
when "00000100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
when "00000010" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 8);
when "11000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 48);
when "00110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 16);
when "11110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap) sll 32);
when "00001111" => WBdata_o <= locDataInSwap;
when "00000001" => WBdata_o <= locDataInSwap;
when "00000011" => WBdata_o <= locDataInSwap;
when "11111111" => WBdata_o <= locDataInSwap;
case sel_i is
when "10000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 56);
when "01000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 48);
when "00100000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 40);
when "00010000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 32);
when "00001000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 24);
when "00000100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 16);
when "00000010" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 8);
when "11000000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 48);
when "00110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 32);
when "00001100" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 16);
when "11110000" => WBdata_o <= std_logic_vector(unsigned(locDataInSwap_i) sll 32);
when "00001111" => WBdata_o <= locDataInSwap_i;
when "00000001" => WBdata_o <= locDataInSwap_i;
when "00000011" => WBdata_o <= locDataInSwap_i;
when "11111111" => WBdata_o <= locDataInSwap_i;
when others => null;
end case;
WbSel_o <= std_logic_vector(sel);
WbSel_o <= std_logic_vector(sel_i);
end if;
end process;
process (s_select,s_wbData_i)
begin
case s_select is
when "100000010" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut'length));
when "100000100" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut'length));
when "100001000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut'length));
when "100010000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(39 downto 0)) srl 32,locDataOut'length));
when "100100000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(47 downto 0)) srl 40,locDataOut'length));
when "101000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(55 downto 0)) srl 48,locDataOut'length));
when "110000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 56,locDataOut'length));
when "100001100" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut'length));
when "100110000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(47 downto 0)) srl 32,locDataOut'length));
when "111000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 48,locDataOut'length));
when "100000001" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)), locDataOut'length));
when "100000011" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)), locDataOut'length));
when "100001111" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut'length));
when "111110000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 32, locDataOut'length));
when "111111111" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i),locDataOut'length));
when others => locDataOut <= (others => '0');
when "100000010" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut_o'length));
when "100000100" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut_o'length));
when "100001000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut_o'length));
when "100010000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(39 downto 0)) srl 32,locDataOut_o'length));
when "100100000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(47 downto 0)) srl 40,locDataOut_o'length));
when "101000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(55 downto 0)) srl 48,locDataOut_o'length));
when "110000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 56,locDataOut_o'length));
when "100001100" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut_o'length));
when "100110000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(47 downto 0)) srl 32,locDataOut_o'length));
when "111000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 48,locDataOut_o'length));
when "100000001" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)), locDataOut_o'length));
when "100000011" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)), locDataOut_o'length));
when "100001111" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when "111110000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i) srl 32, locDataOut_o'length));
when "111111111" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i),locDataOut_o'length));
when others => locDataOut_o <= (others => '0');
end case;
end process;
......@@ -224,19 +220,19 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
-- shift data and address for WB data bus 32 bits
gen32: if (g_width = 32) generate
gen32: if (g_wb_data_width = 32) generate
process(clk_i)
begin
if rising_edge(clk_i) then
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr) srl 2,g_addr_width));
locAddr_o <= std_logic_vector(resize(unsigned(rel_locAddr_i) srl 2,g_wb_addr_width));
end if;
end process;
process(sel)
process(sel_i)
begin
if sel = "10000000" or sel = "01000000" or sel = "00100000" or sel = "00010000"
or sel = "11000000" or sel = "00110000" or sel = "11110000" then
if sel_i = "10000000" or sel_i = "01000000" or sel_i = "00100000" or sel_i = "00010000"
or sel_i = "11000000" or sel_i = "00110000" or sel_i = "11110000" then
s_shift_dx <= '1';
else
s_shift_dx <= '0';
......@@ -246,29 +242,29 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process(clk_i)
begin
if rising_edge(clk_i) then
case sel is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,g_width));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,g_width));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 24,g_width));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 8,g_width));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap) sll 16,g_width));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap),g_width));
case sel_i is
when "10000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24,g_wb_data_width));
when "01000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16,g_wb_data_width));
when "00100000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8,g_wb_data_width));
when "00010000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "00001000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 24,g_wb_data_width));
when "00000100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16,g_wb_data_width));
when "00000010" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 8,g_wb_data_width));
when "11000000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16,g_wb_data_width));
when "00110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "00001100" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i) sll 16,g_wb_data_width));
when "11110000" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "00001111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "00000001" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "00000011" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when "11111111" => WBdata_o <= std_logic_vector(resize(unsigned(locDataInSwap_i),g_wb_data_width));
when others => null;
end case;
if s_shift_dx = '1' then
WbSel_o <= sel(7 downto 4);
WbSel_o <= sel_i(7 downto 4);
else
WbSel_o <= sel(3 downto 0);
WbSel_o <= sel_i(3 downto 0);
end if;
end if;
end process;
......@@ -276,45 +272,57 @@ s_wbData_i <= std_logic_vector(resize(unsigned(wbData_i),s_wbData_i'length));
process (s_select,s_wbData_i)
begin
case s_select is
when "100000010" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut'length));
when "100000100" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut'length));
when "100001000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut'length));
when "100010000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)),locDataOut'length));
when "100100000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8,locDataOut'length));
when "101000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut'length));
when "110000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut'length));
when "100001100" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut'length));
when "100110000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)),locDataOut'length));
when "111000000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut'length));
when "100000001" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)), locDataOut'length));
when "100000011" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)), locDataOut'length));
when "100001111" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut'length));
when "111110000" => locDataOut <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut'length));
when others => locDataOut <= (others => '0');
when "100000010" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8, locDataOut_o'length));
when "100000100" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut_o'length));
when "100001000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut_o'length));
when "100010000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)),locDataOut_o'length));
when "100100000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)) srl 8,locDataOut_o'length));
when "101000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(23 downto 0)) srl 16,locDataOut_o'length));
when "110000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 24,locDataOut_o'length));
when "100001100" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut_o'length));
when "100110000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)),locDataOut_o'length));
when "111000000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)) srl 16,locDataOut_o'length));
when "100000001" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(7 downto 0)), locDataOut_o'length));
when "100000011" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(15 downto 0)), locDataOut_o'length));
when "100001111" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when "111110000" => locDataOut_o <= std_logic_vector(
resize(unsigned(s_wbData_i(31 downto 0)), locDataOut_o'length));
when others => locDataOut_o <= (others => '0');
end case;
end process;
end generate gen32;
err <= err_i;
rty <= rty_i;
memAckWb <= memAckWB_i or s_AckWithError or rty_i;
psize_o <= beatCount;
err_o <= err_i;
rty_o <= rty_i;
memAckWb_o <= memAckWB_i or s_AckWithError or rty_i;
------------------------------------------------------------------------
-- This process registers the WB data input; this is a warranty that this
-- data will be stable during all the time the VME_bus component needs to
-- transfers its to the VME bus.
process(clk_i)
begin
if rising_edge(clk_i) then
if memAckWB_i = '1' then
s_DATi_sample <= wbData_i;
end if;
end if;
end process;
------------------------------------------------------------------------
end Behavioral;
--===========================================================================
-- Architecture end
......
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 92f0bc34
......@@ -43,13 +43,17 @@
-- led 5 <-- WB data bus 32 bits
-- led 6 <-- Module enable
-- led 7 <-- flashing
-- Each VME board plugged in a slot acts as a VME slave module and it has only
-- one CR/CSR space (conforming with the specification) so only one FPGA at time
-- must drive the output lines on the VME bus; only one FPGA at time can carry
-- the vme64x core or other similar VME slave core.
-- Inside each component is possible read a more detailed description. |
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -68,16 +72,15 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use IEEE.numeric_std.unsigned;
use work.vme64x_pack.all;
--===========================================================================
-- Entity declaration
--===========================================================================
entity VME_bus is
generic(g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
generic(g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
);
port(
clk_i : in std_logic;
......@@ -110,26 +113,18 @@ entity VME_bus is
-- WB signals
memReq_o : out std_logic;
memAckWB_i : in std_logic;
wbData_o : out std_logic_vector(g_width - 1 downto 0);
wbData_i : in std_logic_vector(g_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_addr_width - 1 downto 0);
wbSel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
wbData_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
wbSel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
RW_o : out std_logic;
cyc_o : out std_logic;
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
psize_o : out std_logic_vector(8 downto 0);
--FIFO Signals
VMEtoWB : out std_logic;
WBtoVME : out std_logic;
FifoMux : out std_logic;
transfer_done_i : in std_logic;
transfer_done_o : out std_logic;
--CR/CSR space signals:
CRAMaddr_o : out std_logic_vector(f_log2_size(g_CRAM_SIZE)-1 downto 0);
CRAMaddr_o : out std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMdata_i : in std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
......@@ -150,9 +145,8 @@ entity VME_bus is
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
ModuleEnable : in std_logic;
MBLT_Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
W32 : in std_logic;
Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
numBytes : out std_logic_vector(12 downto 0);
transfTime : out std_logic_vector(39 downto 0);
......@@ -247,12 +241,7 @@ architecture RTL of VME_bus is
-- WishBone signals
signal s_sel : unsigned(7 downto 0); -- SEL WB signal
signal s_nx_sel : std_logic_vector(7 downto 0);
signal s_RW : std_logic; -- RW WB signal
-- 2e related signals
signal s_beatCount : unsigned(8 downto 0); -- for 2e modes
signal s_cycleCount : unsigned(7 downto 0); -- Stores cycle count
signal s_DS1pulse : std_logic; -- Pulse on DS1 edge
signal s_RW : std_logic; -- RW WB signal
-- CR/CSR related signals
signal s_CRaddressed : std_logic; -- CR is addressed
......@@ -289,11 +278,6 @@ architecture RTL of VME_bus is
signal s_nx_base_addr : std_logic_vector(63 downto 0);
signal s_func_sel : std_logic_vector(7 downto 0);
signal s_VMEdata64In : unsigned(63 downto 0);
--flag FIFO: if '1' the FIFO is used
signal s_FIFO : std_logic;
signal s_transfer_done_i : std_logic;
signal s_counter : unsigned(25 downto 0);
signal s_countcyc : unsigned(9 downto 0);
......@@ -318,14 +302,15 @@ architecture RTL of VME_bus is
signal s_bytes : std_logic_vector(12 downto 0);
signal s_datawidth : unsigned(3 downto 0);
--
signal s_wbMaster_rst : std_logic;
signal s_num_latchDS : integer;
--===========================================================================
-- Architecture begin
--===========================================================================
begin
--
s_FIFO <= '0'; -- FIFO not used if '0'
FifoMux <= s_FIFO;
-- calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
s_num_latchDS <= f_latchDS(g_clock);
---------
s_is_d64 <= '1' when s_sel= "11111111" else '0'; --used to drive the VME_ADDR_DIR_o
---------
......@@ -477,17 +462,6 @@ with s_addressingType select
"10" when A32_BLT,
"10" when A32_MBLT,
"11" when others;
-- uncomment for using 2e modes:
--with s_XAM select
-- s_XAMtype <= A32_2eVME when x"01",
-- A64_2eVME when x"02",
-- A32_2eSST when x"11",
-- A64_2eSST when x"12",
-- XAM_error when others;
--s_2eType <= TWOe_VME when s_XAMtype = A32_2eVME or s_XAMtype = A64_2eVME else
-- TWOe_SST;
-------------------------------------MAIN FSM--------------------------------|
s_memReq <= s_FSM.s_memReq;
......@@ -522,10 +496,6 @@ with s_addressingType select
when IDLE =>
s_FSM <= c_FSM_default;
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir,
-- s_dataDir to 'Z' in the default configuration.
-- If the S_FPGA will be provided to a core who drives these lines without
-- erase the A_FPGA the above mentioned lines should be changed to 'Z' !!!
-- During the Interrupt ack cycle the Slave can't be accessed
-- so if VME_IACK_n_i is asserted the FSM is in IDLE state.
-- The VME_IACK_n_i signal is asserted by the Interrupt handler
......@@ -562,12 +532,12 @@ with s_addressingType select
s_FSM.s_transferActive <= '1';
if VME_DS_n_i /= "11" then
s_mainFSMstate <= LATCH_DS;
s_mainFSMstate <= LATCH_DS1;
else
s_mainFSMstate <= WAIT_FOR_DS;
end if;
when LATCH_DS =>
when LATCH_DS1 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
......@@ -577,8 +547,58 @@ with s_addressingType select
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
if s_num_latchDS = 1 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
s_mainFSMstate <= LATCH_DS2;
end if;
when LATCH_DS2 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
if s_num_latchDS = 2 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
s_mainFSMstate <= LATCH_DS3;
end if;
when LATCH_DS3 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
if s_num_latchDS = 3 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
s_mainFSMstate <= LATCH_DS4;
end if;
when LATCH_DS4 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
when CHECK_TRANSFER_TYPE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
......@@ -586,10 +606,7 @@ with s_addressingType select
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
if (s_transferType = SINGLE or (s_transferType = BLT and
VME_WRITE_n_i = '0') or (s_transferType = BLT and
VME_WRITE_n_i = '1' and s_transfer_done_i = '1')) and
s_addrWidth /= "11" then
if (s_transferType = SINGLE or s_transferType = BLT) and s_addrWidth /= "11" then
s_mainFSMstate <= MEMORY_REQ;
s_FSM.s_memReq <= '1';
elsif (s_transferType = MBLT or s_addrWidth = "11") and s_dataPhase = '0' then
......@@ -688,267 +705,7 @@ with s_addressingType select
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= '1';
s_FSM.s_transferActive <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
-- uncomment for using 2e modes:
-- when WAIT_FOR_DS_2e =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_2eLatchAddr <= "01";
-- if VME_DS_n_i(0) = '0' then
-- s_mainFSMstate <= ADDR_PHASE_1;
-- end if;
--
-- when ADDR_PHASE_1 =>
-- s_FSM <= c_FSM_default;
-- s_mainFSMstate <= DECODE_ACCESS_2e;
--
-- when DECODE_ACCESS_2e =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_decode <= '1';
-- if s_cardSel = '1' then -- if module is selected, proceed with DTACK,
-- -- else wait here until FSM reset by AS going high
-- s_mainFSMstate <= DTACK_PHASE_1;
-- end if;
--
-- when DTACK_PHASE_1 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= '0';
-- s_FSM.s_berr <= s_berr;
-- if VME_DS_n_i(0) = '1' and s_berr = '0' then
-- s_mainFSMstate <= ADDR_PHASE_2;
-- end if;
--
-- when ADDR_PHASE_2 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_2eLatchAddr <= "10";
-- s_FSM.s_mainDTACK <= '0';
-- s_mainFSMstate <= DTACK_PHASE_2;
--
-- when DTACK_PHASE_2 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- if VME_DS_n_i(0) = '0' then
-- s_mainFSMstate <= ADDR_PHASE_3;
-- end if;
--
-- when ADDR_PHASE_3 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_2eLatchAddr <= "11";
-- s_mainFSMstate <= DTACK_PHASE_3;
--
-- when DTACK_PHASE_3 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= '0';
-- s_FSM.s_retry <= s_retry;
-- if s_RW = '0' and s_retry = '0' and s_2eType = TWOe_VME then
-- s_mainFSMstate <= TWOeVME_WRITE;
-- elsif s_RW = '1' and s_retry = '0' and s_2eType = TWOe_VME then
-- s_mainFSMstate <= TWOeVME_READ;
-- -- elsif s_2eType = TWOe_SST then -- not yet correct
-- -- s_mainFSMstate <= TWOe_FIFO_WAIT_READ;
-- -- s_memReq <= '0';
-- -- s_cyc <= '0';
-- -- else -- not yet correct
-- -- s_mainFSMstate <= TWOe_FIFO_WAIT_READ;
-- -- s_memReq <= '0';
-- -- s_cyc <= '0';
-- -- end if;
-- elsif VME_DS_n_i(0) = '1' or s_retry = '1' then
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
-- end if;
--
-- when TWOeVME_WRITE =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- if s_DS1pulse = '1' and VME_DS_n_i(0) = '0'then
-- s_mainFSMstate <= WAIT_WR_1;
-- s_FSM.s_memReq <= '1';
-- elsif VME_DS_n_i(0) = '1' then
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
-- end if;
--
-- when WAIT_WR_1 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_mainFSMstate <= WAIT_WR_2;
--
-- when WAIT_WR_2 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_mainFSMstate <= WAIT_WB_ACK_WR;
--
-- when WAIT_WB_ACK_WR =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- if s_AckWb = '1' then
-- s_mainFSMstate <= TWOeVME_TOGGLE_WR;
-- end if;
--
-- when TWOeVME_TOGGLE_WR =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= not s_mainDTACK;
-- s_FSM.s_incrementAddr <= '1';
-- s_mainFSMstate <= TWOeVME_WRITE;
--
-- when TWOeVME_READ =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- if s_DS1pulse = '1' and VME_DS_n_i(0) = '0'then
-- s_mainFSMstate <= TWOeVME_MREQ_RD;
-- s_FSM.s_memReq <= '1';
-- elsif VME_DS_n_i(0) = '1' then
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
-- end if;
--
-- when TWOeVME_MREQ_RD =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_mainFSMstate <= WAIT_WB_ACK_RD;
--
-- when WAIT_WB_ACK_RD =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- if s_AckWb = '1' then
-- s_mainFSMstate <= TWOeVME_INCR_ADDR;
-- end if;
--
-- when TWOeVME_INCR_ADDR =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_FSM.s_incrementAddr <= '1';
-- s_FSM.s_dataToAddrBus <= '1';
-- s_mainFSMstate <= TWOeVME_TOGGLE_RD;
--
-- when TWOeVME_TOGGLE_RD =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= not s_mainDTACK;
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_mainFSMstate <= TWOeVME_READ;
--
-- when TWOe_FIFO_WRITE =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- if s_DS1pulse = '1' and s_2eType = TWOe_VME and
-- VME_DS_n_i(0) = '0'then
-- s_FSM.s_memReq <= '1';
-- -- elsif s_DS1pulse = '1' then --VME_DS_n_i(0) = '1' then
-- -- s_memReq <= '1';
-- -- else
-- -- s_memReq <= '0';
-- end if;
--
-- if s_DS1pulse = '1' and s_2eType = TWOe_VME then
-- s_mainFSMstate <= TWOe_TOGGLE_DTACK;
-- elsif VME_DS_n_i(0) = '1' then
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
-- end if;
--
-- when TWOe_TOGGLE_DTACK =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_dataDir <= s_dataDir;
-- s_FSM.s_addrDir <= s_addrDir;
-- s_FSM.s_incrementAddr <= '1';
-- if s_RW = '0' and s_2eType = TWOe_SST then
-- s_mainFSMstate <= TWOe_FIFO_WRITE;
-- s_FSM.s_mainDTACK <= not s_mainDTACK;
-- elsif s_RW = '1' and s_2eType = TWOe_SST then
-- s_mainFSMstate <= TWOe_CHECK_BEAT;
-- s_FSM.s_mainDTACK <= not s_mainDTACK;
-- --elsif s_RW = '0' then
-- -- s_mainFSMstate <= TWOe_FIFO_WRITE;
-- -- s_mainDTACK <= not s_mainDTACK;
-- else
-- s_mainFSMstate <= TWOe_WAIT_FOR_DS1;
-- s_FSM.s_mainDTACK <= not s_mainDTACK;
-- end if;
--
-- when TWOe_WAIT_FOR_DS1 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_dataDir <= s_dataDir;
-- s_FSM.s_addrDir <= s_addrDir;
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataToAddrBus <= '1';
-- if (s_DS1pulse = '1' and s_2eType = TWOe_VME) or s_2eType = TWOe_SST then
-- s_mainFSMstate <= TWOe_CHECK_BEAT;
-- end if;
--
-- when TWOe_FIFO_WAIT_READ =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_memReq <= not stall_i;
-- -- if readFIFOempty_i = '0' then --and s_2eType=TWOe_SST then
-- if stall_i = '0' then --and s_2eType=TWOe_SST then
-- s_mainFSMstate <= TWOe_FIFO_READ;
-- end if;
-- -- s_memReq <= not stall_i; -- access to the wb_dma
-- when TWOe_FIFO_READ =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_dataToAddrBus <= s_AckWb;
-- if s_AckWb = '1' then
-- s_mainFSMstate <= TWOe_TOGGLE_DTACK;
-- end if;
--
-- when TWOe_CHECK_BEAT =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_dataDir <= '1';
-- s_FSM.s_addrDir <= s_is_d64;
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_mainFSMstate <= TWOe_END_1;
--
-- when TWOe_RELEASE_DTACK => -- wait here the AS rising edge --> reset FSM
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
--
-- when TWOe_END_1 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_retry <= '1';
-- s_mainFSMstate <= TWOe_END_2;
--
-- when TWOe_END_2 =>
-- s_FSM <= c_FSM_default;
-- s_FSM.s_dtackOE <= '1';
-- s_FSM.s_mainDTACK <= s_mainDTACK;
-- s_FSM.s_retry <= '1';
-- s_FSM.s_berr <= '1';
-- if VME_DS_n_i = "11" then
-- s_mainFSMstate <= TWOe_RELEASE_DTACK;
-- end if;
s_mainFSMstate <= WAIT_FOR_DS;
when others =>
s_FSM <= c_FSM_default;
......@@ -1042,7 +799,7 @@ with s_addressingType select
(s_addressingType = AM_Error) or s_blockTransferLimit = '1' or
(s_transferType = BLT and (not(s_typeOfDataTransfer = D32 or
s_typeOfDataTransfer = D64))) or (s_transferType = MBLT and
s_typeOfDataTransfer /= D64) or (s_is_d64 = '1' and W32 = '1') then
s_typeOfDataTransfer /= D64) or (s_is_d64 = '1' and g_wb_data_width = 32) then
s_BERRcondition <= '1';
else
......@@ -1051,7 +808,7 @@ with s_addressingType select
end if;
end process;
-- generate the error condition if block transfer overflow the limit
-- generate the error condition if block transfer overflows the limit
-- BLT --> block transfer limit = 256 bytes (rule 2.12a VME64 std ANSI/VITA 1-1994)
-- MBLT --> block transfer limit = 2048 bytes (rule 2.78 VME64 std ANSI/VITA 1-1994)
with s_transferType select
......@@ -1131,38 +888,6 @@ with s_addressingType select
end if;
end if;
end process;
-- uncomment for using 2e modes:
-- p_2eAddrLatch : process(clk_i)
-- begin
-- if rising_edge(clk_i) then
-- if s_reset = '1' or s_mainFSMreset = '1' then
-- s_phase1addr <= (others => '0');
-- s_phase2addr <= (others => '0');
-- s_phase3addr <= (others => '0');
-- else
-- case s_2eLatchAddr is
-- when "01" =>
-- s_phase1addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
-- s_phase2addr <= s_phase2addr;
-- s_phase3addr <= s_phase3addr;
-- when "10" =>
-- s_phase2addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
-- s_phase1addr <= s_phase1addr;
-- s_phase3addr <= s_phase3addr;
-- when "11" =>
-- s_phase3addr <= s_VMEdataInput & s_VMEaddrInput & s_LWORDinput;
-- s_phase1addr <= s_phase1addr;
-- s_phase2addr <= s_phase2addr;
-- when others =>
-- s_phase1addr <= s_phase1addr;
-- s_phase2addr <= s_phase2addr;
-- s_phase3addr <= s_phase3addr;
-- end case;
-- end if;
-- end if;
-- end process;
-- s_XAM <= s_phase1addr(7 downto 0);
-- Local address mapping
with s_addrWidth select
s_locAddrBeforeOffset(63 downto 1) <= x"000000000000" & s_VMEaddrLatched(15 downto 1) when "00",
......@@ -1240,7 +965,7 @@ with s_addressingType select
CRaddr_o <= std_logic_vector(s_CRaddr(11 downto 0));
CRAMaddr_o <= std_logic_vector(resize(s_CrCsrOffsetAddr - unsigned(s_BEG_CRAM(18 downto 0)),
f_log2_size(g_CRAM_SIZE)));
f_log2_size(g_cram_size)));
--------------------DATA HANDLER PROCESS---------------------------- |
-- Data strobe latching
......@@ -1285,19 +1010,19 @@ with s_addressingType select
--swap the data during read or write operation
--sel= 000 --> No swap
--sel= 001 --> Swap Byte eg: 01234567 become 10325476
--sel= 010 --> Swap Word eg: 01234567 become 23016745
--sel= 011 --> Swap Word+ Swap Byte eg: 01234567 become 32107654
--sel= 001 --> Swap Byte eg: 01234567 become 10325476
--sel= 010 --> Swap Word eg: 01234567 become 23016745
--sel= 011 --> Swap Word+ Swap Byte eg: 01234567 become 32107654
--sel= 100 --> Swap DWord + Swap Word+ Swap Byte eg: 01234567 become 76543210
swapper_write: VME_swapper port map(
d_i => std_logic_vector(s_locDataIn),
sel => MBLT_Endian_i,
sel => Endian_i,
d_o => s_locDataInSwap
);
swapper_read: VME_swapper port map(
d_i => std_logic_vector(s_locData),
sel => MBLT_Endian_i,
sel => Endian_i,
d_o => s_locDataSwap
);
......@@ -1331,49 +1056,6 @@ with s_addressingType select
s_locData(63 downto 0) <= s_locDataOut(63 downto 0) sll to_integer(unsigned(s_DataShift));
s_CSRdata <= unsigned(CSRData_i);
-------------------------BEAT COUNT--------------------------------|
-- 2eSST:
-- The Cycle Count informs the slave in advance of the amount of data that
-- it is requested to receive in a write transaction or the amount of data
-- it is to supply in a read request. The cycle count value sent is the beat count
-- divided by two. There are two data beats in each cycle
-- 2eVME:
-- Rule 11.8:
-- The beat count shall be sent in A[15:8] during the second address phase.
-- The value is the number of beats divided by two.
s_cycleCount <= unsigned(s_phase2addr(15 downto 8));
-- The Beat Count information is important if the FIFO is used;
-- during 2e access the Master send this information, during
-- BLT and MBLT access the Beat Count is equal to the block transfer limit.
-- Uncomment the following process for 2edge modes:
-- process(s_cycleCount,s_beatCount,s_XAMtype, s_transferType, s_typeOfDataTransfer)
-- begin --
-- if ((s_XAMtype = A32_2eVME) or (s_XAMtype = A64_2eVME) or (s_XAMtype = A32_2eSST)
-- or (s_XAMtype = A64_2eSST)) then
-- s_beatCount <= (resize(s_cycleCount*2, s_beatCount'length));
-- elsif s_transferType = SINGLE then
-- s_beatCount <= (to_unsigned(1, s_beatCount'length));
-- elsif s_transferType = BLT then
-- --Rule 2.12a VME64std
-- if (s_typeOfDataTransfer = D08_0 or s_typeOfDataTransfer = D08_1 or
-- s_typeOfDataTransfer = D08_2 or s_typeOfDataTransfer = D08_3) then
-- s_beatCount <= (to_unsigned(255, s_beatCount'length));
-- elsif (s_typeOfDataTransfer = D16_01 or s_typeOfDataTransfer = D16_23) then
-- s_beatCount <= (to_unsigned(127, s_beatCount'length));
-- else
-- s_beatCount <= (to_unsigned(31, s_beatCount'length));
-- --32 not 64 becouse the fifo read from wb 64 bit (not 32) every cycle.
-- end if;
-- elsif s_transferType = MBLT and s_FIFO = '1' then -- Rule 2.78 VME64std
-- s_beatCount <= (to_unsigned(255, s_beatCount'length));
-- else
-- s_beatCount <= (to_unsigned(1, s_beatCount'length));
-- end if;
-- end process;
-- Comment the following line for 2e modes
s_beatCount <= (others => '0');
---------------------MEMORY MAPPING--------------------------------
-- WB bus width = 64-bits
......@@ -1450,32 +1132,29 @@ s_beatCount <= (others => '0');
--------------------------WB MASTER-----------------------------------|
--This component acts as WB master for single read/write PIPELINED mode.
--The data and address lines are shifted inside this component.
s_wbMaster_rst <= s_reset or s_mainFSMreset;
Inst_Wb_master: VME_Wb_master
generic map(
g_width => g_width,
g_addr_width => g_addr_width
g_wb_data_width => g_wb_data_width,
g_wb_addr_width => g_wb_addr_width
)
port map(
s_memReq => s_memReq,
memReq_i => s_memReq,
clk_i => clk_i,
cardSel => s_cardSel,
reset => s_reset,
mainFSMreset => s_mainFSMreset,
BERRcondition => s_BERRcondition,
sel => std_logic_vector(s_sel),
beatCount => std_logic_vector(s_beatCount),
locDataInSwap => s_locDataInSwap,
locDataOut => s_locDataOutWb,
rel_locAddr => std_logic_vector(s_rel_locAddr),
memAckWb => s_AckWb,
err => s_err,
rty => s_rty,
RW => s_RW,
psize_o => psize_o,
cardSel_i => s_cardSel,
reset_i => s_wbMaster_rst,
BERRcondition_i => s_BERRcondition,
sel_i => std_logic_vector(s_sel),
locDataInSwap_i => s_locDataInSwap,
locDataOut_o => s_locDataOutWb,
rel_locAddr_i => std_logic_vector(s_rel_locAddr),
memAckWb_o => s_AckWb,
err_o => s_err,
rty_o => s_rty,
RW_i => s_RW,
stall_i => stall_i,
rty_i => rty_i,
err_i => err_i,
W32 => W32,
cyc_o => cyc_o,
memReq_o => memReq_o,
WBdata_o => wbData_o,
......@@ -1621,7 +1300,7 @@ s_beatCount <= (others => '0');
if s_reset = '1' or s_mainFSMreset = '1' then
s_countertime <= (others => '0');
elsif VME_AS_n_i = '0' then
s_countertime <= s_countertime + unsigned(c_CLK_PERIOD);
s_countertime <= s_countertime + to_unsigned(g_clock,40);
end if;
end if;
end process;
......@@ -1664,11 +1343,11 @@ s_beatCount <= (others => '0');
s_initReadCounter <= unsigned(s_initReadCounter1);
Inst_VME_Init: VME_Init port map(
clk_i => clk_i,
RSTedge => s_RSTedge,
CRAddr => std_logic_vector(s_CRaddr),
RSTedge_i => s_RSTedge,
CRAddr_i => std_logic_vector(s_CRaddr),
CRdata_i => CRdata_i,
InitReadCount => s_initReadCounter1,
InitInProgress => s_initInProgress,
InitReadCount_o => s_initReadCounter1,
InitInProgress_o => s_initInProgress,
BEG_USR_CR_o => s_BEG_USER_CR,
END_USR_CR_o => s_END_USER_CR,
BEG_USR_CSR_o => s_BEG_USER_CSR,
......@@ -1723,13 +1402,6 @@ s_beatCount <= (others => '0');
clk_i => clk_i,
RisEdge_o => s_mainFSMreset
);
-- for 2e modes:
DS1EdgeDetect : EdgeDetection
port map (
sig_i => VME_DS_n_i(1),
clk_i => clk_i,
sigEdge_o => s_DS1pulse
);
CRinputSample : DoubleRegInputSample
generic map(
......@@ -1750,16 +1422,6 @@ s_beatCount <= (others => '0');
reg_o => s_CRAMdataIn,
clk_i => clk_i
);
---------------------------Output for FIFO.vhd-------------------------------------|
VMEtoWB <= '1' when (s_cardSel = '1' and (s_transferType = BLT or s_transferType = MBLT) and
VME_WRITE_n_i = '0' and VME_DS_n_i /= "11") else '0';
WBtoVME <= '1' when (s_cardSel = '1' and (s_transferType = BLT or s_transferType = MBLT) and
VME_WRITE_n_i = '1' and VME_DS_n_i /= "11") else '0';
transfer_done_o <= s_mainFSMreset;
--------------------------Input from FIFO-----------------------------------------
s_transfer_done_i <= transfer_done_i when s_FIFO = '1' else '1';
------------------------------LEDS------------------------------------------------|
-- Debug
......@@ -1769,8 +1431,8 @@ s_beatCount <= (others => '0');
if rising_edge(clk_i) then
if s_reset = '1' then
s_led5 <= '1';
else
s_led5 <= not W32;
elsif g_wb_data_width = 32 then
s_led5 <= '0';
end if;
end if;
end process;
......
hdl/vme64x-core/rtl/VME_swapper.vhd
View file @ 92f0bc34
......@@ -13,8 +13,8 @@
--______________________________________________________________________________
-- Authors:
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 08/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 92f0bc34
......@@ -8,8 +8,8 @@
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.02
-- Date 11/2012
-- Version v0.03
--_______________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
......@@ -26,6 +26,7 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--use work.VME_CR_pack.all;
package vme64x_pack is
--__________________________________________________________________________________
-- Records:
......@@ -57,7 +58,17 @@ package vme64x_pack is
s_berr : std_logic;
s_BERR_out : std_logic;
end record;
type t_FSM_IRQ is
record
s_IACKOUT : std_logic;
s_DataDir : std_logic;
s_DTACK : std_logic;
s_enableIRQ : std_logic;
s_resetIRQ : std_logic;
s_DSlatch : std_logic;
s_DTACK_OE : std_logic;
end record;
--_______________________________________________________________________________
-- Constants:
--WB data width:
......@@ -71,35 +82,58 @@ package vme64x_pack is
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
-- Tclk in ns used to calculate the data transfer rate
constant c_CLK_PERIOD : std_logic_vector(19 downto 0) := "00000000000000001010";
--AM table:
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101";
constant c_A24_S : std_logic_vector(5 downto 0) := "111001";
constant c_A24_BLT : std_logic_vector(5 downto 0) := "111011";
constant c_A24_BLT_sup : std_logic_vector(5 downto 0) := "111111";
constant c_A24_MBLT : std_logic_vector(5 downto 0) := "111000";
constant c_A24_MBLT_sup : std_logic_vector(5 downto 0) := "111100";
constant c_A24_LCK : std_logic_vector(5 downto 0) := "110010";
constant c_CR_CSR : std_logic_vector(5 downto 0) := "101111";
constant c_A16 : std_logic_vector(5 downto 0) := "101001";
constant c_A16_sup : std_logic_vector(5 downto 0) := "101101";
constant c_A16_LCK : std_logic_vector(5 downto 0) := "101100";
constant c_A32 : std_logic_vector(5 downto 0) := "001001";
constant c_A32_sup : std_logic_vector(5 downto 0) := "001101";
constant c_A32_BLT : std_logic_vector(5 downto 0) := "001011";
constant c_A32_BLT_sup : std_logic_vector(5 downto 0) := "001111";
constant c_A32_MBLT : std_logic_vector(5 downto 0) := "001000";
constant c_A32_MBLT_sup : std_logic_vector(5 downto 0) := "001100";
constant c_A32_LCK : std_logic_vector(5 downto 0) := "000101";
constant c_A64 : std_logic_vector(5 downto 0) := "000001";
constant c_A64_BLT : std_logic_vector(5 downto 0) := "000011";
constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000";
constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100";
constant c_TWOedge : std_logic_vector(5 downto 0) := "100000";
constant c_A32_2eVME : std_logic_vector(7 downto 0) := "00000001";
constant c_A64_2eVME : std_logic_vector(7 downto 0) := "00000010";
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001";
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010";
constant c_clk_period : integer := 10; --c_CLK_PERIOD : std_logic_vector(19 downto 0) := "00000000000000001010";
-- add here the default boards ID:
constant c_SVEC_ID : integer := 408; -- 0x00000198
constant c_CERN_ID : integer := 524336; -- 0x080030
constant c_RevisionID : integer := 1; -- 0x00000001
--BoardID positions:
constant c_BOARD_ID_p1 : integer := 12;
constant c_BOARD_ID_p2 : integer := 13;
constant c_BOARD_ID_p3 : integer := 14;
constant c_BOARD_ID_p4 : integer := 15;
--ManufacturerID positions:
constant c_Manuf_ID_p1 : integer := 9;
constant c_Manuf_ID_p2 : integer := 10;
constant c_Manuf_ID_p3 : integer := 11;
--RevisionID positions:
constant c_Rev_ID_p1 : integer := 16;
constant c_Rev_ID_p2 : integer := 17;
constant c_Rev_ID_p3 : integer := 18;
constant c_Rev_ID_p4 : integer := 19;
--ProgramID positions:
constant c_Prog_ID_p : integer := 31;
-- AM table.
-- References:
-- Table 2-3 "Address Modifier Codes" pages 21/22 VME64std ANSI/VITA 1-1994
-- Table 2.4 "Extended Address Modifier Code" page 12 2eSST ANSI/VITA 1.5-2003(R2009)
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101"; -- hex code 0x3d
constant c_A24_S : std_logic_vector(5 downto 0) := "111001"; -- hex code 0x39
constant c_A24_BLT : std_logic_vector(5 downto 0) := "111011"; -- hex code 0x3b
constant c_A24_BLT_sup : std_logic_vector(5 downto 0) := "111111"; -- hex code 0x3f
constant c_A24_MBLT : std_logic_vector(5 downto 0) := "111000"; -- hex code 0x38
constant c_A24_MBLT_sup : std_logic_vector(5 downto 0) := "111100"; -- hex code 0x3c
constant c_A24_LCK : std_logic_vector(5 downto 0) := "110010"; -- hex code 0x32
constant c_CR_CSR : std_logic_vector(5 downto 0) := "101111"; -- hex code 0x2f
constant c_A16 : std_logic_vector(5 downto 0) := "101001"; -- hex code 0x29
constant c_A16_sup : std_logic_vector(5 downto 0) := "101101"; -- hex code 0x2d
constant c_A16_LCK : std_logic_vector(5 downto 0) := "101100"; -- hex code 0x2c
constant c_A32 : std_logic_vector(5 downto 0) := "001001"; -- hex code 0x09
constant c_A32_sup : std_logic_vector(5 downto 0) := "001101"; -- hex code 0x0d
constant c_A32_BLT : std_logic_vector(5 downto 0) := "001011"; -- hex code 0x0b
constant c_A32_BLT_sup : std_logic_vector(5 downto 0) := "001111"; -- hex code 0x0f
constant c_A32_MBLT : std_logic_vector(5 downto 0) := "001000"; -- hex code 0x08
constant c_A32_MBLT_sup : std_logic_vector(5 downto 0) := "001100"; -- hex code 0x0c
constant c_A32_LCK : std_logic_vector(5 downto 0) := "000101"; -- hex code 0x05
constant c_A64 : std_logic_vector(5 downto 0) := "000001"; -- hex code 0x01
constant c_A64_BLT : std_logic_vector(5 downto 0) := "000011"; -- hex code 0x03
constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000"; -- hex code 0x00
constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100"; -- hex code 0x04
constant c_TWOedge : std_logic_vector(5 downto 0) := "100000"; -- hex code 0x20
constant c_A32_2eVME : std_logic_vector(7 downto 0) := "00000001"; -- hex code 0x21
constant c_A64_2eVME : std_logic_vector(7 downto 0) := "00000010"; -- hex code 0x22
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001"; -- hex code 0x11
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010"; -- hex code 0x12
--CSR array's index:
constant BAR : integer := 255;
constant BIT_SET_CLR_REG : integer := 254;
......@@ -147,7 +181,7 @@ package vme64x_pack is
constant BYTES0 : integer := FUNC0_ADER_3 -10;
constant BYTES1 : integer := FUNC0_ADER_3 -11;
constant WB32bits : integer := FUNC0_ADER_3 -12;
constant MBLT_Endian : integer := FUNC0_ADER_3 -4;
constant Endian : integer := FUNC0_ADER_3 -4;
-- Initialization CR:
constant BEG_USER_CR : integer := 1;
......@@ -201,6 +235,16 @@ package vme64x_pack is
s_BERR_out => '0'
);
constant c_FSM_IRQ : t_FSM_IRQ :=(
s_IACKOUT => '1',
s_DataDir => '0',
s_DTACK => '1',
s_enableIRQ => '0',
s_resetIRQ => '1',
s_DSlatch => '0',
s_DTACK_OE => '0'
);
-- CSR address:
constant c_BAR_addr : unsigned(19 downto 0) := x"7FFFF"; -- VME64x defined CSR
constant c_BIT_SET_REG_addr : unsigned(19 downto 0) := x"7FFFB";
......@@ -250,7 +294,7 @@ package vme64x_pack is
constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b";
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_WB32bits_addr : unsigned(19 downto 0) := x"7FF33";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
constant c_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
--___________________________________________________________________________________________
-- TYPE:
......@@ -303,7 +347,10 @@ package vme64x_pack is
type t_mainFSMstates is ( IDLE,
DECODE_ACCESS,
WAIT_FOR_DS,
LATCH_DS,
LATCH_DS1,
LATCH_DS2,
LATCH_DS3,
LATCH_DS4,
CHECK_TRANSFER_TYPE,
MEMORY_REQ,
DATA_TO_BUS,
......@@ -359,13 +406,16 @@ package vme64x_pack is
-- functions
function f_div8 (width : integer) return integer;
function f_log2_size (A : natural) return natural;
function f_set_CR_space (BoardID : integer; cr_default : t_cr_array;
ManufacturerID : integer; RevisionID : integer; ProgramID : integer) return t_cr_array;
function f_latchDS (clk_period : integer) return integer;
--_____________________________________________________________________________________________________
--COMPONENTS:
component VME_bus is
generic(
g_width : integer := c_width;
g_addr_width : integer := c_addr_width;
g_CRAM_SIZE : integer := c_CRAM_SIZE
generic( g_clock : integer := c_clk_period;
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width;
g_cram_size : integer := c_CRAM_SIZE
);
port(
clk_i : in std_logic;
......@@ -380,7 +430,7 @@ function f_log2_size (A : natural) return natural;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_IACK_n_i : in std_logic;
memAckWB_i : in std_logic;
wbData_i : in std_logic_vector(g_width - 1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
......@@ -397,11 +447,9 @@ function f_log2_size (A : natural) return natural;
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
ModuleEnable : in std_logic;
MBLT_Endian_i : in std_logic_vector(2 downto 0);
Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
W32 : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
transfer_done_i : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
reset_o : out std_logic;
VME_LWORD_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
......@@ -416,16 +464,12 @@ function f_log2_size (A : natural) return natural;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
memReq_o : out std_logic;
wbData_o : out std_logic_vector(g_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_addr_width - 1 downto 0);
wbSel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
wbData_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
wbSel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
RW_o : out std_logic;
cyc_o : out std_logic;
psize_o : out std_logic_vector(8 downto 0);
VMEtoWB : out std_logic;
WBtoVME : out std_logic;
FifoMux : out std_logic;
CRAMaddr_o : out std_logic_vector(f_log2_size(g_CRAM_SIZE)-1 downto 0);
cyc_o : out std_logic;
CRAMaddr_o : out std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
......@@ -435,8 +479,7 @@ function f_log2_size (A : natural) return natural;
err_flag_o : out std_logic;
numBytes : out std_logic_vector(12 downto 0);
transfTime : out std_logic_vector(39 downto 0);
leds : out std_logic_vector(7 downto 0);
transfer_done_o : out std_logic
leds : out std_logic_vector(7 downto 0)
);
end component VME_bus;
......@@ -525,14 +568,19 @@ function f_log2_size (A : natural) return natural;
component VME_CR_CSR_Space is
generic(
g_CRAM_SIZE : integer := c_CRAM_SIZE;
g_width : integer := c_width
g_cram_size : integer := c_CRAM_SIZE;
g_wb_data_width : integer := c_width;
g_CRspace : t_cr_array; -- := c_cr_array;
g_BoardID : integer := c_SVEC_ID;
g_ManufacturerID : integer := c_CERN_ID;
g_RevisionID : integer := c_RevisionID;
g_ProgramID : integer := 96
);
port(
clk_i : in std_logic;
reset : in std_logic;
CR_addr : in std_logic_vector(11 downto 0);
CRAM_addr : in std_logic_vector(f_log2_size(g_CRAM_SIZE)-1 downto 0);
CRAM_addr : in std_logic_vector(f_log2_size(g_cram_size)-1 downto 0);
CRAM_data_i : in std_logic_vector(7 downto 0);
CRAM_Wen : in std_logic;
en_wr_CSR : in std_logic;
......@@ -554,10 +602,9 @@ function f_log2_size (A : natural) return natural;
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
W32 : out std_logic;
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
MBLT_Endian_o : out std_logic_vector(2 downto 0);
Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0)
......@@ -603,37 +650,33 @@ function f_log2_size (A : natural) return natural;
component VME_Wb_master is
generic(
g_width : integer := c_width;
g_addr_width : integer := c_addr_width
g_wb_data_width : integer := c_width;
g_wb_addr_width : integer := c_addr_width
);
port(
s_memReq : in std_logic;
memReq_i : in std_logic;
clk_i : in std_logic;
cardSel : in std_logic;
reset : in std_logic;
mainFSMreset : in std_logic;
BERRcondition : in std_logic;
sel : in std_logic_vector(7 downto 0);
beatCount : in std_logic_vector(8 downto 0);
locDataInSwap : in std_logic_vector(63 downto 0);
rel_locAddr : in std_logic_vector(63 downto 0);
RW : in std_logic;
cardSel_i : in std_logic;
reset_i : in std_logic;
BERRcondition_i : in std_logic;
sel_i : in std_logic_vector(7 downto 0);
locDataInSwap_i : in std_logic_vector(63 downto 0);
rel_locAddr_i : in std_logic_vector(63 downto 0);
RW_i : in std_logic;
stall_i : in std_logic;
rty_i : in std_logic;
err_i : in std_logic;
wbData_i : in std_logic_vector(g_width - 1 downto 0);
wbData_i : in std_logic_vector(g_wb_data_width - 1 downto 0);
memAckWB_i : in std_logic;
locDataOut : out std_logic_vector(63 downto 0);
memAckWb : out std_logic;
err : out std_logic;
W32 : in std_logic;
rty : out std_logic;
psize_o : out std_logic_vector(8 downto 0);
locDataOut_o : out std_logic_vector(63 downto 0);
memAckWb_o : out std_logic;
err_o : out std_logic;
rty_o : out std_logic;
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector(g_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_addr_width - 1 downto 0);
WbSel_o : out std_logic_vector(f_div8(g_width) - 1 downto 0);
WBdata_o : out std_logic_vector(g_wb_data_width - 1 downto 0);
locAddr_o : out std_logic_vector(g_wb_addr_width - 1 downto 0);
WbSel_o : out std_logic_vector(f_div8(g_wb_data_width) - 1 downto 0);
RW_o : out std_logic
);
end component VME_Wb_master;
......@@ -641,11 +684,11 @@ function f_log2_size (A : natural) return natural;
component VME_Init is
port(
clk_i : in std_logic;
CRAddr : in std_logic_vector(18 downto 0);
CRAddr_i : in std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
RSTedge : inout std_logic;
InitReadCount : out std_logic_vector(8 downto 0);
InitInProgress : out std_logic;
RSTedge_i : in std_logic;
InitReadCount_o : out std_logic_vector(8 downto 0);
InitInProgress_o : out std_logic;
BEG_USR_CR_o : out std_logic_vector(23 downto 0);
END_USR_CR_o : out std_logic_vector(23 downto 0);
BEG_USR_CSR_o : out std_logic_vector(23 downto 0);
......@@ -767,16 +810,16 @@ function f_log2_size (A : natural) return natural;
component VME_IRQ_Controller is
port(
clk_i : in std_logic;
reset : in std_logic;
reset_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123 : in std_logic_vector(2 downto 0);
INT_Level : in std_logic_vector(7 downto 0);
INT_Vector : in std_logic_vector(7 downto 0);
INT_Req : in std_logic;
VME_ADDR_123_i : in std_logic_vector(2 downto 0);
INT_Level_i : in std_logic_vector(7 downto 0);
INT_Vector_i : in std_logic_vector(7 downto 0);
INT_Req_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
......@@ -821,4 +864,76 @@ function f_log2_size (A : natural) return natural is
return(63);
end function f_log2_size;
function f_set_CR_space(BoardID : integer; cr_default : t_cr_array;
ManufacturerID : integer; RevisionID : integer;
ProgramID : integer) return t_cr_array is
variable v_CR_space : t_cr_array(2**12 downto 0);
variable v_BoardID : std_logic_vector(31 downto 0);
variable v_ManufacturerID : std_logic_vector(23 downto 0);
variable v_RevisionID : std_logic_vector(31 downto 0);
variable v_ProgramID : std_logic_vector(7 downto 0);
begin
v_BoardID := std_logic_vector(to_unsigned(BoardID,32));
v_ManufacturerID := std_logic_vector(to_unsigned(ManufacturerID,24));
v_RevisionID := std_logic_vector(to_unsigned(RevisionID,32));
v_ProgramID := std_logic_vector(to_unsigned(ProgramID,8));
for i in cr_default'range loop
case i is
when c_BOARD_ID_p1 => v_CR_space(i) := v_BoardID(31 downto 24);
when c_BOARD_ID_p2 => v_CR_space(i) := v_BoardID(23 downto 16);
when c_BOARD_ID_p3 => v_CR_space(i) := v_BoardID(15 downto 8);
when c_BOARD_ID_p4 => v_CR_space(i) := v_BoardID(7 downto 0);
when c_Manuf_ID_p1 => v_CR_space(i) := v_ManufacturerID(23 downto 16);
when c_Manuf_ID_p2 => v_CR_space(i) := v_ManufacturerID(15 downto 8);
when c_Manuf_ID_p3 => v_CR_space(i) := v_ManufacturerID(7 downto 0);
when c_Rev_ID_p1 => v_CR_space(i) := v_RevisionID(31 downto 24);
when c_Rev_ID_p2 => v_CR_space(i) := v_RevisionID(23 downto 16);
when c_Rev_ID_p3 => v_CR_space(i) := v_RevisionID(15 downto 8);
when c_Rev_ID_p4 => v_CR_space(i) := v_RevisionID(7 downto 0);
when c_Prog_ID_p => v_CR_space(i) := v_ProgramID(7 downto 0);
when others => v_CR_space(i) := cr_default(i);
end case;
-- if i = c_BOARD_ID_p1 then
-- v_CR_space(i) := v_BoardID(31 downto 24);
-- elsif i = c_BOARD_ID_p2 then
-- v_CR_space(i) := v_BoardID(23 downto 16);
-- elsif i = c_BOARD_ID_p3 then
-- v_CR_space(i) := v_BoardID(15 downto 8);
-- elsif i = c_BOARD_ID_p4 then
-- v_CR_space(i) := v_BoardID(7 downto 0);
-- elsif i = c_Manuf_ID_p1 then
-- v_CR_space(i) := v_ManufacturerID(23 downto 16);
-- elsif i = c_Manuf_ID_p2 then
-- v_CR_space(i) := v_ManufacturerID(15 downto 8);
-- elsif i = c_Manuf_ID_p3 then
-- v_CR_space(i) := v_ManufacturerID(7 downto 0);
-- elsif i = c_Rev_ID_p1 then
-- v_CR_space(i) := v_RevisionID(31 downto 24);
-- elsif i = c_Rev_ID_p2 then
-- v_CR_space(i) := v_RevisionID(23 downto 16);
-- elsif i = c_Rev_ID_p3 then
-- v_CR_space(i) := v_RevisionID(15 downto 8);
-- elsif i = c_Rev_ID_p4 then
-- v_CR_space(i) := v_RevisionID(7 downto 0);
-- elsif i = c_Prog_ID_p then
-- v_CR_space(i) := v_ProgramID(7 downto 0);
-- else
-- v_CR_space(i) := cr_default(i);
-- end if;
end loop;
return(v_CR_space);
end function f_set_CR_space;
function f_latchDS(clk_period : integer) return integer is
begin
for I in 1 to 4 loop
if (clk_period * I >= 20) then -- 20 is the max time between the assertion
-- of the DS lines.
return(I);
end if;
end loop;
return(4); -- works for up to 200 MHz
end function f_latchDS;
end vme64x_pack;
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