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VME64x core
Commit 85d50ea6 authored by Tom Levens's avatar Tom Levens
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Reduce warnings in Quartus 

Assign explicit values to s_XAM, s_phase1addr & s_phase2addr. Remove
unused signal s_func_sel.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 62b13b5e
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Showing with 42 additions and 37 deletions
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 85d50ea6
--------------------------------------------------------------------------------
-- CERN (BE-CO-HT)
-- VME64x Core
-- http://www.ohwr.org/projects/vme64x-core
......@@ -191,9 +190,9 @@ architecture RTL of VME_bus is
signal s_locAddr, s_rel_locAddr : unsigned(63 downto 0); -- Local address
signal s_locAddr2e : unsigned(63 downto 0); -- for 2e transfers
signal s_locAddrBeforeOffset : unsigned(63 downto 0);
signal s_phase1addr : unsigned(63 downto 0) := (others => '0'); -- for 2e transfers
signal s_phase2addr : unsigned(63 downto 0) := (others => '0'); --
-- signal s_phase3addr : unsigned(63 downto 0); --
signal s_phase1addr : unsigned(63 downto 0); -- for 2e transfers
signal s_phase2addr : unsigned(63 downto 0); --
--signal s_phase3addr : unsigned(63 downto 0); --
signal s_addrOffset : unsigned(17 downto 0); -- block transfers|
signal s_DataShift : unsigned(5 downto 0);
-- uncomment if 2e is implemented:
......@@ -205,9 +204,9 @@ architecture RTL of VME_bus is
-- Latched signals
signal s_VMEaddrLatched : unsigned(63 downto 1); -- Latch on AS falling edge
signal s_LWORDlatched : std_logic; -- Stores LWORD on falling edge of AS
signal s_DSlatched : std_logic_vector(1 downto 0) := (others => '0'); -- Stores DS
signal s_DSlatched : std_logic_vector(1 downto 0); -- Stores DS
signal s_AMlatched : std_logic_vector(5 downto 0); -- Latch on AS f. edge
signal s_XAM : unsigned(7 downto 0) := (others => '0'); -- Stores received XAM
signal s_XAM : unsigned(7 downto 0); -- Stores received XAM
-- Type of data transfer (depending on VME_DS_n, VME_LWORD_n and VME_ADDR(1))
signal s_typeOfDataTransfer : t_typeOfDataTransfer;
......@@ -264,7 +263,6 @@ architecture RTL of VME_bus is
signal s_is_d64 : std_logic;
signal s_base_addr : unsigned(63 downto 0);
signal s_nx_base_addr : std_logic_vector(63 downto 0);
signal s_func_sel : std_logic_vector(7 downto 0);
signal s_VMEdata64In : unsigned(63 downto 0);
signal s_BERR_out : std_logic;
......@@ -857,6 +855,8 @@ begin
'1' when "10",
'0' when others;
s_phase1addr <= (others => '0');
s_phase2addr <= (others => '0');
s_locAddr2e <= s_phase1addr(63 downto 8) & s_phase2addr(7 downto 0);
-- This process generates the s_locAddr that is used during the access decode
......@@ -926,10 +926,14 @@ begin
p_DSlatching : process (clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_DSlatched <= (others => '0');
else
if s_DSlatch = '1' then
s_DSlatched <= VME_DS_ant_n_i;
end if;
end if;
end if;
end process;
s_VMEdata64In(63 downto 33) <= s_VMEaddrInput(31 downto 1);
......@@ -1106,6 +1110,7 @@ begin
-- This component check if the board is addressed; if the CR/CSR space is
-- addressed the Confaccess signal is asserted
-- If the Wb memory is addressed the CardSel signal is asserted.
s_XAM <= (others => '0');
Inst_Access_Decode : VME_Access_Decode
port map (
......@@ -1151,7 +1156,7 @@ begin
XAm => std_logic_vector(s_XAM),
BAR_i => bar_i,
AddrWidth => s_addrWidth,
Funct_Sel => s_func_sel,
Funct_Sel => open,
Base_Addr => s_nx_base_addr,
Confaccess => s_confAccess,
CardSel => s_cardSel
......
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