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VME64x core
Commit 78cb0c4a authored by Tom Levens's avatar Tom Levens
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Clean-up main FSM 

Remove duplicate registers for all main FSM signals.
Signed-off-by: Tom Levens's avatarTom Levens <tom.levens@cern.ch>
parent 85d50ea6
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Showing with 131 additions and 225 deletions
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 78cb0c4a
......@@ -223,7 +223,6 @@ architecture RTL of VME_bus is
-- Main FSM signals
signal s_mainFSMstate : t_mainFSMstates;
signal s_FSM : t_FSM;
signal s_dataToAddrBus : std_logic; -- (for D64) --> multiplexed transfer
signal s_dataToOutput : std_logic; -- Puts data to VME data bus
signal s_mainDTACK : std_logic; -- DTACK driving
......@@ -237,8 +236,7 @@ architecture RTL of VME_bus is
signal s_mainFSMreset : std_logic; -- Resets main FSM on AS r. edge
signal s_dataPhase : std_logic; -- for A64 and multipl. transf.
signal s_transferActive : std_logic; -- active VME transfer
--signal s_retry : std_logic; -- RETRY signal
signal s_retry_out : std_logic;
signal s_retry : std_logic; -- RETRY signal
-- uncomment if 2e is implemented:
--signal s_berr : std_logic; -- BERR signal
......@@ -275,6 +273,16 @@ architecture RTL of VME_bus is
signal s_wbMaster_rst : std_logic;
signal s_num_latchDS : integer;
function f_latchDS (clk_period : integer) return integer is
begin
for I in 1 to 4 loop
if (clk_period * I >= 20) then -- 20 is the max time between the assertion
return(I); -- of the DS lines.
end if;
end loop;
return(4); -- works for up to 200 MHz
end function f_latchDS;
begin
-- Calculate the number of LATCH DS states necessary to match the timing
......@@ -416,27 +424,6 @@ begin
------------------------------------------------------------------------------
-- MAIN FSM
------------------------------------------------------------------------------
s_memReq <= s_FSM.s_memReq;
s_decode <= s_FSM.s_decode;
s_dtackOE <= s_FSM.s_dtackOE;
s_mainDTACK <= s_FSM.s_mainDTACK;
s_dataDir <= s_FSM.s_dataDir;
s_dataOE <= s_FSM.s_dataOE;
s_addrDir <= s_FSM.s_addrDir;
s_addrOE <= s_FSM.s_addrOE;
s_DSlatch <= s_FSM.s_DSlatch;
s_incrementAddr <= s_FSM.s_incrementAddr;
s_dataPhase <= s_FSM.s_dataPhase;
s_dataToOutput <= s_FSM.s_dataToOutput;
s_dataToAddrBus <= s_FSM.s_dataToAddrBus;
s_transferActive <= s_FSM.s_transferActive;
-- uncomment if 2e is implemented:
--s_2eLatchAddr <= s_FSM.s_2eLatchAddr;
s_retry_out <= s_FSM.s_retry;
-- uncomment if 2e is implemented:
--s_berr <= s_FSM.s_berr;
s_BERR_out <= s_FSM.s_BERR_out;
p_VMEmainFSM : process (clk_i)
begin
if rising_edge(clk_i) then
......@@ -444,13 +431,48 @@ begin
-- FSM resetted after power up,
-- software reset, manually reset,
-- on rising edge of AS.
s_FSM <= c_FSM_default;
s_memReq <= '0';
s_decode <= '0';
s_dtackOE <= '0';
s_mainDTACK <= '1';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
--s_2eLatchAddr <= "00"; -- uncomment if 2e is implemented:
s_retry <= '0';
--s_berr <= '0'; -- uncomment if 2e is implemented:
s_BERR_out <= '0';
s_mainFSMstate <= IDLE;
else
s_memReq <= '0';
s_decode <= '0';
s_dtackOE <= '0';
s_mainDTACK <= '1';
s_dataDir <= '0';
s_dataOE <= '0';
s_addrDir <= '0';
s_addrOE <= '0';
s_DSlatch <= '0';
s_incrementAddr <= '0';
s_dataPhase <= '0';
s_dataToOutput <= '0';
s_dataToAddrBus <= '0';
s_transferActive <= '0';
--s_2eLatchAddr <= "00"; -- uncomment if 2e is implemented:
s_retry <= '0';
--s_berr <= '0'; -- uncomment if 2e is implemented:
s_BERR_out <= '0';
case s_mainFSMstate is
when IDLE =>
s_FSM <= c_FSM_default;
-- During the Interrupt ack cycle the Slave can't be accessed
-- so if VME_IACK_n_i is asserted the FSM is in IDLE state.
-- The VME_IACK_n_i signal is asserted by the Interrupt handler
......@@ -464,9 +486,8 @@ begin
when DECODE_ACCESS =>
-- check if this slave board is addressed and if it is, check the access mode
s_FSM <= c_FSM_default;
s_FSM.s_decode <= '1';
s_FSM.s_DSlatch <= '1';
s_decode <= '1';
s_DSlatch <= '1';
-- uncomment for using 2e modes:
--if s_addressingType = TWOedge then
---- start 2e transfer
......@@ -482,12 +503,11 @@ begin
when WAIT_FOR_DS =>
-- wait until DS /= "11"
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_DSlatch <= '1';
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if VME_DS_n_i /= "11" then
s_mainFSMstate <= LATCH_DS1;
......@@ -498,13 +518,12 @@ begin
when LATCH_DS1 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_DSlatch <= '1';
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if s_num_latchDS = 1 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
......@@ -514,13 +533,12 @@ begin
when LATCH_DS2 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_DSlatch <= '1';
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if s_num_latchDS = 2 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
......@@ -530,13 +548,12 @@ begin
when LATCH_DS3 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_DSlatch <= '1';
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if s_num_latchDS = 3 then
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
else
......@@ -546,55 +563,52 @@ begin
when LATCH_DS4 =>
-- this state is necessary indeed the VME master can assert the
-- DS lines not at the same time
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_DSlatch <= '1';
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_DSlatch <= '1';
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
s_mainFSMstate <= CHECK_TRANSFER_TYPE;
when CHECK_TRANSFER_TYPE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if (s_transferType = SINGLE or s_transferType = BLT) and
s_addrWidth /= "11"
(s_addrWidth /= "11")
then
s_mainFSMstate <= MEMORY_REQ;
s_FSM.s_memReq <= '1';
s_memReq <= '1';
elsif (s_transferType = MBLT or s_addrWidth = "11") and
s_dataPhase = '0'
(s_dataPhase = '0')
then
s_mainFSMstate <= DTACK_LOW;
elsif (s_transferType = MBLT or s_addrWidth = "11") and
s_dataPhase = '1'
(s_dataPhase = '1')
then
s_mainFSMstate <= MEMORY_REQ;
s_FSM.s_memReq <= '1';
s_memReq <= '1';
end if;
when MEMORY_REQ =>
-- To request the memory CR/CSR or WB memory it is sufficient to
-- generate a pulse on s_memReq signal
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if s_memAck = '1' and VME_WRITE_n_i = '0' then
s_mainFSMstate <= DTACK_LOW;
elsif s_memAck = '1' and VME_WRITE_n_i = '1' then
if s_transferType = MBLT then
s_FSM.s_dataToAddrBus <= '1';
s_dataToAddrBus <= '1';
else
s_FSM.s_dataToOutput <= '1';
s_dataToOutput <= '1';
end if;
s_mainFSMstate <= DATA_TO_BUS;
else
......@@ -602,45 +616,42 @@ begin
end if;
when DATA_TO_BUS =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_FSM.s_dataToAddrBus <= s_dataToAddrBus;
s_FSM.s_dataToOutput <= s_dataToOutput;
s_mainFSMstate <= DTACK_LOW;
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
s_dataToAddrBus <= s_dataToAddrBus;
s_dataToOutput <= s_dataToOutput;
s_mainFSMstate <= DTACK_LOW;
when DTACK_LOW =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_dataDir <= VME_WRITE_n_i;
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_dataDir <= VME_WRITE_n_i;
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if s_BERRcondition = '0' and s_rty1 = '0' then
s_FSM.s_mainDTACK <= '0';
s_mainDTACK <= '0';
elsif s_BERRcondition = '0' and s_rty1 = '1' then
s_FSM.s_retry <= '1';
s_retry <= '1';
else
s_FSM.s_BERR_out <= '1';
s_BERR_out <= '1';
end if;
if VME_DS_n_i = "11" then
s_mainFSMstate <= DECIDE_NEXT_CYCLE;
s_FSM.s_dataDir <= '0';
s_dataDir <= '0';
else
s_mainFSMstate <= DTACK_LOW;
end if;
when DECIDE_NEXT_CYCLE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_dtackOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
if (s_transferType = SINGLE and s_addrWidth /= "11") or
(s_transferType = SINGLE and s_addrWidth = "11" and s_dataPhase = '1')
then
......@@ -651,32 +662,29 @@ begin
then
s_mainFSMstate <= INCREMENT_ADDR;
elsif (s_transferType = MBLT or s_addrWidth = "11") and
s_dataPhase = '0'
(s_dataPhase = '0')
then
s_mainFSMstate <= SET_DATA_PHASE;
else
s_mainFSMstate <= DECIDE_NEXT_CYCLE;
s_mainFSMstate <= DECIDE_NEXT_CYCLE;
end if;
when INCREMENT_ADDR =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= s_dataPhase;
s_FSM.s_transferActive <= '1';
s_FSM.s_incrementAddr <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
s_dtackOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= s_dataPhase;
s_transferActive <= '1';
s_incrementAddr <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
when SET_DATA_PHASE =>
s_FSM <= c_FSM_default;
s_FSM.s_dtackOE <= '1';
s_FSM.s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_FSM.s_dataPhase <= '1';
s_FSM.s_transferActive <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
s_dtackOE <= '1';
s_addrDir <= (s_is_d64) and VME_WRITE_n_i;
s_dataPhase <= '1';
s_transferActive <= '1';
s_mainFSMstate <= WAIT_FOR_DS;
when others =>
s_FSM <= c_FSM_default;
s_mainFSMstate <= IDLE;
end case;
......@@ -702,7 +710,7 @@ begin
p_RETRYdriver : process (clk_i)
begin
if rising_edge(clk_i) then
if s_retry_out = '1' then
if s_retry = '1' then
VME_RETRY_n_o <= '0';
VME_RETRY_OE_o <= '1';
else
......
hdl/vme64x-core/rtl/vme64x_pack.vhd
View file @ 78cb0c4a
......@@ -37,50 +37,6 @@ use ieee.numeric_std.all;
package vme64x_pack is
------------------------------------------------------------------------------
-- Records
------------------------------------------------------------------------------
type t_rom_cell is
record
add : integer;
len : integer;
end record;
type t_cr_add_table is array (natural range <>) of t_rom_cell;
type t_FSM is
record
s_memReq : std_logic;
s_decode : std_logic;
s_dtackOE : std_logic;
s_mainDTACK : std_logic;
s_dataDir : std_logic;
s_dataOE : std_logic;
s_addrDir : std_logic;
s_addrOE : std_logic;
s_DSlatch : std_logic;
s_incrementAddr : std_logic;
s_dataPhase : std_logic;
s_dataToOutput : std_logic;
s_dataToAddrBus : std_logic;
s_transferActive : std_logic;
s_2eLatchAddr : std_logic_vector(1 downto 0);
s_retry : std_logic;
s_berr : std_logic;
s_BERR_out : std_logic;
end record;
type t_FSM_IRQ is
record
s_IACKOUT : std_logic;
s_DataDir : std_logic;
s_DTACK : std_logic;
s_enableIRQ : std_logic;
s_resetIRQ : std_logic;
s_DSlatch : std_logic;
s_DTACK_OE : std_logic;
end record;
------------------------------------------------------------------------------
-- Constants
------------------------------------------------------------------------------
......@@ -135,43 +91,6 @@ package vme64x_pack is
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001"; -- 0x11
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010"; -- 0x12
-- Main Finite State machine signals default:
-- When the S_FPGA detects the magic sequency, it erases the A_FPGA so
-- I don't need to drive the s_dtackOE, s_dataOE, s_addrOE, s_addrDir, s_dataDir
-- to 'Z' in the default configuration.
-- If the S_FPGA will be provided to a core who drive these lines without erase the
-- A_FPGA the above mentioned lines should be changed to 'Z' !!!
constant c_FSM_default : t_FSM := (
s_memReq => '0',
s_decode => '0',
s_dtackOE => '0',
s_mainDTACK => '1',
s_dataDir => '0',
s_dataOE => '0',
s_addrDir => '0', -- during IACK cycle the ADDR lines are input
s_addrOE => '0',
s_DSlatch => '0',
s_incrementAddr => '0',
s_dataPhase => '0',
s_dataToOutput => '0',
s_dataToAddrBus => '0',
s_transferActive => '0',
s_2eLatchAddr => "00",
s_retry => '0',
s_berr => '0',
s_BERR_out => '0'
);
constant c_FSM_IRQ : t_FSM_IRQ := (
s_IACKOUT => '1',
s_DataDir => '0',
s_DTACK => '1',
s_enableIRQ => '0',
s_resetIRQ => '1',
s_DSlatch => '0',
s_DTACK_OE => '0'
);
-- Defined CR area
constant c_beg_cr : unsigned(19 downto 0) := x"00000";
constant c_end_cr : unsigned(19 downto 0) := x"00FFF";
......@@ -340,13 +259,6 @@ package vme64x_pack is
--TWOe_END_2
);
type t_initState is (
IDLE,
SET_ADDR,
GET_DATA,
END_INIT
);
type t_FUNC_32b_array is
array (0 to 7) of unsigned(31 downto 0); -- ADER register array
......@@ -363,10 +275,6 @@ package vme64x_pack is
-- Functions
------------------------------------------------------------------------------
function f_latchDS (
clk_period : integer
) return integer;
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
......@@ -880,16 +788,6 @@ end vme64x_pack;
package body vme64x_pack is
function f_latchDS (clk_period : integer) return integer is
begin
for I in 1 to 4 loop
if (clk_period * I >= 20) then -- 20 is the max time between the assertion
return(I); -- of the DS lines.
end if;
end loop;
return(4); -- works for up to 200 MHz
end function f_latchDS;
function f_vme_cr_encode (
manufacturer_id : std_logic_vector( 23 downto 0);
board_id : std_logic_vector( 31 downto 0);
......
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