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VME64x core
Commit 2891a297 authored by dpedrett's avatar dpedrett
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vme64x core ordered 

git-svn-id: http://svn.ohwr.org/vme64x-core/trunk@142 665b4545-5c6b-4c24-801b-41150b02b44b
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hdl/boards/vfc/rtl/IRQ_generator.vhd
View file @ 2891a297
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 11:18:01 06/13/2012
-- Design Name:
-- Module Name: IRQ_generator - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- Dependencies:
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: IRQ_generator.vhd
--_____________________________________________________________________________
-- Description: This block generates an interrupt request; the interrupt request
-- is a pulse on the WB bus slave1_o.int line. The Interrupt frequency is setted
-- by the VME Master writing the FREQ register:
-- Values refer to a 20 MHz clock:
-- | FREQ values: | Time between 2 consecutive interrupts: |
-- | 0x00000000 | NO interrupt (default value) |
-- | 0x08000000 | Interrupt any 6,72 s |
-- | 0x04000000 | Interrupt any 3,36 s |
-- | 0x02000000 | Interrupt any 1,67 s |
-- | 0x01000000 | Interrupt any 0,83 s |
-- | 0x00800000 | Interrupt any 0,42 s |
-- | 0x00400000 | Interrupt any 0,20 s |
-- | 0x00200000 | Interrupt any 0,10 s |
-- | 0x00100000 | Interrupt any 0,05 s |
-- | 0x00080000 | Interrupt any 26 ms |
-- | 0x00040000 | Interrupt any 13 ms |
-- | 0x00020000 | Interrupt any 7 ms |
-- | 0x00010000 | Interrupt any 3 ms |
-- | 0x00008000 | Interrupt any 1,6 ms |
-- | 0x00004000 | Interrupt any 0,8 ms |
-- | 0x00002000 | Interrupt any 0,4 ms |
-- | 0x00001000 | Interrupt any 0,2 ms |
-- | 0x00000800 | Interrupt any 102 us |
-- | 0x00000400 | Interrupt any 50 us |
-- | 0x00000200 | Interrupt any 25 us |
-- | 0x00000100 | Interrupt any 13 us |
-- | 0x00000080 | Interrupt any 6,4 us |
-- | 0x00000040 | Interrupt any 3,2 us |
-- | 0x00000020 | Interrupt any 1,6 us |
-- | 0x00000010 | Interrupt any 800 ns |
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- The IRQ Generator can't generate a new interrupt request before the
-- VME Master read the INT_COUNT register! This operation should be the
-- last operation in the Interrupt service routine.
-- The Master reading the INT_COUNT register can check if it is missing some
-- interrupts; eg if the Master read 0x01, 0x05, 0x09 it means that
-- the Interrupt frequency should be lowered by writing the FREQ register.
--
-- Finite State Machine:
-- ___________ ___________ ____________ ____________
-- | IDLE |--->| CHECK |--->| INCR |--->| IRQ |--->
-- |___________| |___________| |____________| |____________| |
-- | |
-- | ________________ _______________ |
-- |<----------------| WAIT_RD |<----| WAIT_INT_ACK |<----
-- |________________| |_______________|
--
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity IRQ_generator is
Port ( clk_i : in STD_LOGIC;
reset : in STD_LOGIC;
Freq : in STD_LOGIC_VECTOR (31 downto 0);
Int_Count_i : in STD_LOGIC_VECTOR (31 downto 0);
Read_Int_Count : in STD_LOGIC;
INT_ack : in STD_LOGIC;
IRQ_o : out STD_LOGIC;
Int_Count_o : out STD_LOGIC_VECTOR (31 downto 0));
Port ( clk_i : in std_logic;
reset : in std_logic;
Freq : in std_logic_vector (31 downto 0);
Int_Count_i : in std_logic_vector (31 downto 0);
Read_Int_Count : in std_logic;
INT_ack : in std_logic;
IRQ_o : out std_logic;
Int_Count_o : out std_logic_vector (31 downto 0));
end IRQ_generator;
architecture Behavioral of IRQ_generator is
signal s_en_int : std_logic;
type t_FSM is (IDLE, CHECK, INCR, IRQ, WAIT_INT_ACK, WAIT_RD);
signal currs, nexts : t_FSM;
signal s_IRQ_o : std_logic;
signal s_count : unsigned(31 downto 0);
signal s_en_int : std_logic;
signal currs, nexts : t_FSM;
signal s_IRQ_o : std_logic;
signal s_count : unsigned(31 downto 0);
signal s_Rd_Int_Count_delayed : std_logic;
signal s_pulse : std_logic;
signal s_count_int : unsigned(31 downto 0);
signal s_count_req : unsigned(31 downto 0);
signal s_incr : std_logic;
signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
signal s_pulse : std_logic;
signal s_count_int : unsigned(31 downto 0);
signal s_count_req : unsigned(31 downto 0);
signal s_incr : std_logic;
signal s_gen_irq : std_logic;
signal s_count0 : std_logic;
signal s_Freq : std_logic_vector(31 downto 0);
begin
-- In/Out sample
RDinputSample : entity work.DoubleSigInputSample
port map(
sig_i => Read_Int_Count,
......@@ -70,6 +118,9 @@ IRQOutputSample : entity work.FlipFlopD
reset => '0',
enable => '1'
);
-- Upload s_Freq signal; this operation should be done when the
-- internal count is 0 because the VME Master can change the FREQ
-- register at any time.
process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -79,8 +130,9 @@ process(clk_i)
end if;
end if;
end process;
end process;
-- check if s_count is 0
process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -91,7 +143,8 @@ process(clk_i)
end if;
end if;
end process;
--if FREQ = 0x00000000 --> No interrupt
process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -102,18 +155,21 @@ process(clk_i)
s_en_int <= '1';
end if;
end if;
end process;
end process;
--Counter
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' or s_pulse = '1' then s_count <= (others => '0');
if reset = '0' or s_pulse = '1' then
s_count <= (others => '0');
elsif s_en_int = '1' then
s_count <= s_count + 1;
s_count <= s_count + 1;
end if;
end if;
end process;
--
-- Interrupt pulse generator
process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -124,27 +180,32 @@ process(clk_i)
end if;
end if;
end process;
--Counter interrupts
--Counter interrupt pulse --> to INT_COUNT register
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_count_int <= (others => '0');
if reset = '0' then
s_count_int <= (others => '0');
elsif s_en_int = '1' and s_pulse = '1' then
s_count_int <= s_count_int + 1;
s_count_int <= s_count_int + 1;
end if;
end if;
end process;
--Counter interrupts requests
--Counter interrupt requests
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then s_count_req <= (others => '0');
if reset = '0' then
s_count_req <= (others => '0');
elsif s_incr = '1' then
s_count_req <= s_count_req + 1;
s_count_req <= s_count_req + 1;
end if;
end if;
end process;
--
-- if INT_COUNT > Interrupt requests than generate an interrupt request
process(clk_i)
begin
if rising_edge(clk_i) then
......@@ -155,6 +216,7 @@ process(clk_i)
end if;
end if;
end process;
-- Update current state
process(clk_i)
begin
......@@ -164,7 +226,7 @@ begin
end if;
end if;
end process;
-- generate next state
process(currs,s_gen_irq,INT_ack,s_Rd_Int_Count_delayed)
begin
case currs is
......@@ -197,11 +259,10 @@ begin
else
nexts <= WAIT_RD;
end if;
end case;
end process;
-- Update outputs
process(currs)
begin
case currs is
......@@ -228,9 +289,9 @@ begin
when WAIT_RD =>
s_incr <= '0';
s_IRQ_o <= '0';
end case;
end process;
Int_Count_o <= std_logic_vector(s_count_int);
end Behavioral;
hdl/boards/vfc/rtl/TOP_LEVEL.vhd
View file @ 2891a297
--__________________________________________________________________________________
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
--
-- References:
-- The VMEbus specification ANSI/IEEE STD1014-1987
-- The VME64std ANSI/VITA 1-1994
-- The VME64x ANSI/VITA 1.1-1997
--________________________________________________________________________________________________
-- Description: This core implements an interface to transfer data from the VME bus to the WB bus.
-- This core is slave in the VME side and master in the WB side.
-- The design adheres to the VME64 Extensions Standard providing the Plug-and-play capabilities.
--______________________________________________________________________
-- Description:
-- The aim of this top level is to debug the vme64x interface so in the
-- WB side a RAM memory WB capable has been inserted as show in the following
-- block diagram.
--
-- TOP_LEVEL's block diagram
-- ___ ______________________ ___________________
-- | B | | | | |
-- | A | | VME TO WB | | |
-- | C | | INTERFACE | | |
-- | K | | (VME64xCore_Top.vhd) | | SPRAM |
-- | P |_______| | |__________| WB |
-- | L |_______| | |__________| SLAVE |
-- | A | | VME | WB |Point to | (xwb_dpram.vhd) |
-- | N | | SLAVE | MASTER | Point | 64-bit port |
-- | E | | | |Interconn | Byte Granularity |
-- | | | | | | |
-- | | | | | | |
-- |___| |______________________| |___________________|
--
-- To test the VME to WB interface a single port ram, as wb slave, has been inserted.
-- (The wb slave inserted is more generic and there is the possibility to insert a
-- double port ram so the name that you can read is xwb_dpram. However for the test
-- is sufficient a spram).
-- The wb slave supports both the modality CLASSIC and PIPELINED.
-- A little about the clk:
-- ____________________________________________________________
-- ___ | ______________________ ___________________ |
-- | B | | | | | | |
-- | A | | | VME TO WB | | | |
-- | C | | | INTERFACE | | | |
-- | K | | | (VME64xCore_Top.vhd) | | SPRAM | |
-- | P |_____|__| | |__________| WB | |
-- | L |_____|__| | |__________| SLAVE | |
-- | A | | | VME | WB |Point to | (xwb_ram.vhd) | |
-- | N | | | SLAVE | MASTER | Point | 64-bit port | |
-- | E | | | | |Interconn | Byte Granularity | |
-- | | | | | | | | |
-- | | | | | | | | |
-- |___| | |______________________| |___________________| |
-- |____________________________________________________________|
--
--
-- The wb slave supports the PIPELINED mode.
-- A little about the clk:
-- The VME is an asynchronous and handshake protocol so the vme64x interface
-- has to work at any clock frequency but since all the asynchronous signals
-- are sampled and the core work around the main FSM that of course is a synchronous
-- machine and the VME standards provide a set of timing rules, not all the
-- clock frequency ensure proper operation of the core.
--
-- 1) Fig. 25 pag. 107----"VMEbus Specification" ANSI/IEEE STD1014-1987
-- min 30ns
-- <------->
-- _________
-- AS*______/ \______
-- As show in the figure, to be sure that the slave detects the rising edge
-- and the following falling edge on the AS* signal the clk_i's period must be
-- maximum 30 ns.
-- 2) Fig. 20 pag. 99----"VMEbus Specification" ANSI/IEEE STD1014-1987
-- max 20ns
-- <--->
-- ______
-- \__________DSA*
-- ___________
-- \_____DSB*
-- \_____DSB*
-- The Master may not assert the data strobo lines at the same time; the maximum delay between
-- the two falling edge is 20 ns --> in the MFS machine in the VME_bus.vhd file has been inserted
-- The Master may not assert the data strobe lines at the same time; the
-- maximum delay between the two falling edge is 20 ns --> in the MFS
-- machine in the VME_bus.vhd file the LATCH_DS state has been inserted and the
-- minimum clk_i's period must be of 10 ns.
--
-- VME to WB interface:
-- VME to WB interface:
-- A dedicated Configuration ROM/Control&StatusRegister (CR/CSR) address space has been
-- introduced.
-- The CR/CSR space can be accessed with the Addressing Type CR_CSR (AM = 0x2f). This is
-- a A24 sddressing type, SINGLE transfer type.
-- The CR/CSR space can be accessed only with the data transfer type D08_Byte3 because
-- the CR/CSR space provide only Byte(3) locations.
-- The optional CRAM space has been inserted from the location 0x001003 to 0x07fbff.
-- (add here all the other functionality of the core after tested; es A16 BLT D08O/E)
--
-- See the VME64xCore_Top.vhd component
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
--Library UNISIM;
-- uncomment to use the PLL
-- Library UNISIM;
-- use UNISIM.vcomponents.all;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.wishbone_pkg.all;
use work.wishbone_pkg.all;
--Library UNISIM;
--use UNISIM.vcomponents.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
--library UNISIM;
entity TOP_LEVEL is
port(
port(
clk_i : in std_logic; -- 100 MHz clock input
clk_i : in std_logic;
Reset : in std_logic; -- hand reset; button PB1
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
......@@ -93,8 +97,7 @@ port(
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_LWORD_n_b : inout std_logic;
VME_ADDR_b : inout std_logic_vector(31 downto 1);
VME_DATA_b : inout std_logic_vector(31 downto 0);
......@@ -102,19 +105,18 @@ port(
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
VME_IACK_n_i : in std_logic; --Added by Davide
VME_IACK_n_i : in std_logic;
-- VME buffers
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
RST_i : in std_logic;
rst_n_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0)
VME_RETRY_OE_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- not used
RST_i : in std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
end TOP_LEVEL;
......@@ -123,52 +125,56 @@ architecture Behavioral of TOP_LEVEL is
COMPONENT VME64xCore_Top
PORT(
clk_i : IN std_logic;
VME_AS_n_i : IN std_logic;
VME_RST_n_i : IN std_logic;
VME_WRITE_n_i : IN std_logic;
VME_AM_i : IN std_logic_vector(5 downto 0);
VME_DS_n_i : IN std_logic_vector(1 downto 0);
VME_GA_i : IN std_logic_vector(5 downto 0);
VME_BBSY_n_i : IN std_logic;
VME_IACKIN_n_i : IN std_logic;
VME_IACK_n_i : in std_logic;
RST_i : IN std_logic;
DAT_i : IN std_logic_vector(63 downto 0);
ERR_i : IN std_logic;
RTY_i : IN std_logic;
ACK_i : IN std_logic;
STALL_i : IN std_logic;
IRQ_i : IN std_logic;
INT_ack : OUT std_logic;
VME_LWORD_n_b : INOUT std_logic;
VME_ADDR_b : INOUT std_logic_vector(31 downto 1);
VME_DATA_b : INOUT std_logic_vector(31 downto 0);
VME_BERR_o : OUT std_logic;
VME_DTACK_n_o : OUT std_logic;
VME_RETRY_n_o : OUT std_logic;
VME_RETRY_OE_o : OUT std_logic;
VME_IRQ_n_o : OUT std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : OUT std_logic;
VME_DTACK_OE_o : OUT std_logic;
VME_DATA_DIR_o : OUT std_logic;
VME_DATA_OE_N_o : OUT std_logic;
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
DAT_o : OUT std_logic_vector(63 downto 0);
ADR_o : OUT std_logic_vector(63 downto 0);
CYC_o : OUT std_logic;
LOCK_o : OUT std_logic;
SEL_o : OUT std_logic_vector(7 downto 0);
STB_o : OUT std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0);
reset_o : out std_logic;
WE_o : OUT std_logic
-- VME signals:
clk_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WB signals
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
ERR_i : in std_logic;
RTY_i : in std_logic;
ACK_i : in std_logic;
STALL_i : in std_logic;
IRQ_i : in std_logic;
INT_ack : out std_logic;
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
WE_o : out std_logic;
reset_o : out std_logic;
-- for debug:
leds : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT xwb_dpram
COMPONENT xwb_ram
generic(
g_size : natural := 256;
g_init_file : string := "";
......@@ -177,90 +183,88 @@ COMPONENT xwb_dpram
g_slave1_granularity : t_wishbone_address_granularity
);
PORT(
clk_sys_i : IN std_logic;
rst_n_i : IN std_logic;
INT_ack : IN std_logic;
slave1_i : IN t_wishbone_slave_in;
slave1_o : OUT t_wishbone_slave_out
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
INT_ack : in std_logic;
slave1_i : in t_wishbone_slave_in;
slave1_o : out t_wishbone_slave_out
);
END COMPONENT;
signal WbDat_i : std_logic_vector(63 downto 0);
signal WbDat_o : std_logic_vector(63 downto 0);
signal WbAdr_o : std_logic_vector(63 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbLock_o : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(7 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
--signal clk_40MHz : std_logic;
signal clk_fb : std_logic;
--signal clk_2 : std_logic;
--signal status : std_logic_vector(1 downto 0);
signal locked : std_logic;
--signal clk_180 : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst : std_logic;
signal WbDat_i : std_logic_vector(63 downto 0);
signal WbDat_o : std_logic_vector(63 downto 0);
signal WbAdr_o : std_logic_vector(63 downto 0);
signal WbCyc_o : std_logic;
signal WbErr_i : std_logic;
signal WbRty_i : std_logic;
signal WbSel_o : std_logic_vector(7 downto 0);
signal WbStb_o : std_logic;
signal WbAck_i : std_logic;
signal WbWe_o : std_logic;
signal WbStall_i : std_logic;
signal WbIrq_i : std_logic;
signal Rst : std_logic;
signal clk_in : std_logic;
signal s_locked : std_logic;
signal s_fb : std_logic;
signal s_INT_ack : std_logic;
signal s_rst : std_logic;
--mux
signal s_VME_DATA_b_o : std_logic_vector(31 downto 0);
signal s_VME_DATA_DIR : std_logic;
signal s_VME_ADDR_DIR : std_logic;
signal s_VME_ADDR_b_o : std_logic_vector(31 downto 1);
signal s_VME_LWORD_n_b_o : std_logic;
begin
Inst_VME64xCore_Top: VME64xCore_Top PORT MAP(
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b => VME_LWORD_n_b,
VME_ADDR_b => VME_ADDR_b,
VME_DATA_b => VME_DATA_b,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
clk_i => clk_in,
VME_AS_n_i => VME_AS_n_i,
VME_RST_n_i => Rst,
VME_WRITE_n_i => VME_WRITE_n_i,
VME_AM_i => VME_AM_i,
VME_DS_n_i => VME_DS_n_i,
VME_GA_i => VME_GA_i,
VME_BERR_o => VME_BERR_o,
VME_DTACK_n_o => VME_DTACK_n_o,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_LWORD_n_b_i => VME_LWORD_n_b,
VME_LWORD_n_b_o => s_VME_LWORD_n_b_o,
VME_ADDR_b_i => VME_ADDR_b,
VME_ADDR_b_o => s_VME_ADDR_b_o,
VME_DATA_b_i => VME_DATA_b,
VME_DATA_b_o => s_VME_DATA_b_o,
VME_BBSY_n_i => VME_BBSY_n_i,
VME_IRQ_n_o => VME_IRQ_n_o,
VME_IACKIN_n_i => VME_IACKIN_n_i,
VME_IACK_n_i => VME_IACK_n_i,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => VME_DATA_DIR_o,
VME_DTACK_OE_o => VME_DTACK_OE_o,
VME_DATA_DIR_o => s_VME_DATA_DIR,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_DIR_o => s_VME_ADDR_DIR,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => RST_i,
DAT_i => WbDat_i, --
DAT_o => WbDat_o, --
ADR_o => WbAdr_o, --
CYC_o => WbCyc_o, --
ERR_i => WbErr_i, --
LOCK_o => WbLock_o,
RTY_i => WbRty_i, --
SEL_o => WbSel_o, --
STB_o => WbStb_o, --
ACK_i => WbAck_i, --
WE_o => WbWe_o, --
STALL_i => WbStall_i, --
IRQ_i => WbIrq_i, --
INT_ack => s_INT_ack,
reset_o => s_rst,
RST_i => RST_i,
DAT_i => WbDat_i,
DAT_o => WbDat_o,
ADR_o => WbAdr_o,
CYC_o => WbCyc_o,
ERR_i => WbErr_i,
RTY_i => WbRty_i,
SEL_o => WbSel_o,
STB_o => WbStb_o,
ACK_i => WbAck_i,
WE_o => WbWe_o,
STALL_i => WbStall_i,
IRQ_i => WbIrq_i,
INT_ack => s_INT_ack,
reset_o => s_rst,
-- Add by Davide for debug:
leds => leds
leds => leds
);
Inst_xwb_dpram: xwb_dpram
Inst_xwb_ram: xwb_ram
generic map(g_size => 256,
g_init_file => "",
g_must_have_init_file => false,
......@@ -268,35 +272,43 @@ Inst_xwb_dpram: xwb_dpram
g_slave1_granularity => BYTE
)
port map(
clk_sys_i => clk_in,
rst_n_i => s_rst,
INT_ack => s_INT_ack,
slave1_i.cyc => WbCyc_o,
slave1_i.stb => WbStb_o,
slave1_i.adr => WbAdr_o,
slave1_i.sel => WbSel_o,
slave1_i.we => WbWe_o,
slave1_i.dat => WbDat_o,
slave1_o.ack => WbAck_i,
slave1_o.err => WbErr_i,
slave1_o.rty => WbRty_i,
slave1_o.stall => WbStall_i,
slave1_o.int => WbIrq_i,
slave1_o.dat => WbDat_i
clk_sys_i => clk_in,
rst_n_i => s_rst,
INT_ack => s_INT_ack,
slave1_i.cyc => WbCyc_o,
slave1_i.stb => WbStb_o,
slave1_i.adr => WbAdr_o,
slave1_i.sel => WbSel_o,
slave1_i.we => WbWe_o,
slave1_i.dat => WbDat_o,
slave1_o.ack => WbAck_i,
slave1_o.err => WbErr_i,
slave1_o.rty => WbRty_i,
slave1_o.stall => WbStall_i,
slave1_o.int => WbIrq_i,
slave1_o.dat => WbDat_i
);
Rst <= VME_RST_n_i and Reset;
Rst <= VME_RST_n_i and Reset;
---------------------------------------------------------------------------------
-- buffers...The buffers on the board work in the same way
VME_DATA_b <= s_VME_DATA_b_o when s_VME_DATA_DIR = '1' else (others => 'Z');
VME_ADDR_b <= s_VME_ADDR_b_o when s_VME_ADDR_DIR = '1' else (others => 'Z');
VME_LWORD_n_b <= s_VME_LWORD_n_b_o when s_VME_ADDR_DIR = '1' else 'Z';
---------------------------------------------------------------------------------
-- Outputs:
VME_ADDR_DIR_o <= s_VME_ADDR_DIR;
VME_DATA_DIR_o <= s_VME_DATA_DIR;
-- uncomment to use the PLL:
-- PLL_BASE_inst : PLL_BASE
-- generic map (
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 30, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- BANDWIDTH => "OPTIMIZED", -- "HIGH", "LOW" or "OPTIMIZED"
-- CLKFBOUT_MULT => 30, -- Multiply value for all CLKOUT clock outputs (1-64)
-- CLKFBOUT_PHASE => 0.000, -- Phase offset in degrees of the clock feedback output
-- -- (0.0-360.0).
-- CLKIN_PERIOD => 50.000, -- Input clock period in ns to ps resolution (i.e. 33.333 is 30
-- -- MHz).
-- -- CLKOUT0_DIVIDE - CLKOUT5_DIVIDE: Divide amount for CLKOUT# clock output (1-128)
-- CLKOUT0_DIVIDE => 12,
-- CLKOUT1_DIVIDE => 1,
......@@ -304,40 +316,44 @@ Rst <= VME_RST_n_i and Reset;
-- CLKOUT3_DIVIDE => 1,
-- CLKOUT4_DIVIDE => 1,
-- CLKOUT5_DIVIDE => 1,
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE: Duty cycle for CLKOUT# clock output (0.01-0.99).
-- -- CLKOUT0_DUTY_CYCLE - CLKOUT5_DUTY_CYCLE:
-- -- Duty cycle for CLKOUT# clock output (0.01-0.99).
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKOUT3_DUTY_CYCLE => 0.500,
-- CLKOUT4_DUTY_CYCLE => 0.500,
-- CLKOUT5_DUTY_CYCLE => 0.500,
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE: Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- -- CLKOUT0_PHASE - CLKOUT5_PHASE:
-- -- Output phase relationship for CLKOUT# clock output (-360.0-360.0).
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT3_PHASE => 0.000,
-- CLKOUT4_PHASE => 0.000,
-- CLKOUT5_PHASE => 0.000,
-- CLK_FEEDBACK => "CLKFBOUT", -- Clock source to drive CLKFBIN ("CLKFBOUT" or "CLKOUT0")
-- COMPENSATION => "SYSTEM_SYNCHRONOUS", -- "SYSTEM_SYNCHRONOUS", "SOURCE_SYNCHRONOUS", "EXTERNAL"
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "SYSTEM_SYNCHRONOUS",
-- DIVCLK_DIVIDE => 1, -- Division value for all output clocks (1-52)
-- REF_JITTER => 0.1, -- Reference Clock Jitter in UI (0.000-0.999).
-- RESET_ON_LOSS_OF_LOCK => FALSE -- Must be set to FALSE
-- )
-- port map (
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- CLKFBOUT => s_fb, -- 1-bit output: PLL_BASE feedback output
-- -- CLKOUT0 - CLKOUT5: 1-bit (each) output: Clock outputs
-- CLKOUT0 => clk_in, --clk 50 MHz
-- CLKOUT0 => clk_in, --clk 50 MHz
-- CLKOUT1 => open,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- LOCKED => s_locked, -- 1-bit output: PLL_BASE lock status output
-- CLKFBIN => s_fb, -- 1-bit input: Feedback clock input
-- CLKIN => clk_i, -- 1-bit input: Clock input
-- RST => '0' -- 1-bit input: Reset input
-- );
-- comment the next line if the PLL is used:
clk_in <= clk_i;
end Behavioral;
hdl/boards/vfc/rtl/ram_8bits.vhd
View file @ 2891a297
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 08:56:12 05/31/2012
-- Design Name:
-- Module Name: ram_8bits - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--______________________________________________________________________________
-- VME TO WB INTERFACE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- CERN,BE/CO-HT
--______________________________________________________________________________
-- File: ram_8bits.vhd
--______________________________________________________________________________
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
----------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity ram_8bits is
generic (
size : natural := 256
size : natural := 256
);
Port ( addr : in STD_LOGIC_VECTOR (f_log2_size(size)-1 downto 0);
di : in STD_LOGIC_VECTOR (7 downto 0);
do : out STD_LOGIC_VECTOR (7 downto 0);
we : in STD_LOGIC;
clk_i : in STD_LOGIC);
Port ( addr : in std_logic_vector (f_log2_size(size)-1 downto 0);
di : in std_logic_vector (7 downto 0);
do : out std_logic_vector (7 downto 0);
we : in std_logic;
clk_i : in std_logic);
end ram_8bits;
architecture Behavioral of ram_8bits is
......
hdl/boards/vfc/rtl/spram.vhd
View file @ 2891a297
----------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 09:53:50 05/23/2012
-- Design Name:
-- Module Name: spram - Behavioral
-- Project Name:
-- Target Devices:
-- Tool versions:
-- Description:
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
----------------------------------------------------------------------------------
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: spram.vhd
--______________________________________________________________________________
-- Description: single port ram with byte granularity
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_arith.all;
library work;
use work.genram_pkg.all;
--use work.genram_pkg.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;
-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;
entity spram is
generic (
-- standard parameters
g_data_width : natural := 64;
g_size : natural := 256;
-- if true, the user can write individual bytes by using bwe_i
g_with_byte_enable : boolean := true;
g_with_byte_enable : boolean := true; --not used
-- RAM read-on-write conflict resolution. Can be "read_first" (read-then-write)
-- or "write_first" (write-then-read)
g_addr_conflict_resolution : string := "read_first";
g_init_file : string := ""
g_addr_conflict_resolution : string := "read_first"; -- not used
g_init_file : string := "" -- not used
);
port (
--rst_n_i : in std_logic; -- synchronous reset, active LO
clk_i : in std_logic; -- clock input
-- byte write enable
bwe_i : in std_logic_vector(((g_data_width)/8)-1 downto 0);
-- global write enable (masked by bwe_i if g_with_byte_enable = true)
--we_i : in std_logic;
-- address input
a_i : in std_logic_vector(f_log2_size(g_size)-1 downto 0);
-- data input
d_i : in std_logic_vector(g_data_width-1 downto 0);
-- data output
q_o : out std_logic_vector(g_data_width-1 downto 0)
);
......@@ -71,38 +61,18 @@ end spram;
architecture Behavioral of spram is
constant c_num_bytes : integer := (g_data_width)/8;
--type t_ram_type is array(g_size-1 downto 0) of std_logic_vector(g_data_width-1 downto 0);
--signal sram : t_ram_type;
begin
spram: for i in 0 to c_num_bytes-1 generate
ram8bits : entity work.ram_8bits
generic map(g_size)
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
we => bwe_i(i),
port map(addr => a_i,
di => d_i(8*i+7 downto 8*i),
do => q_o(8*i+7 downto 8*i),
we => bwe_i(i),
clk_i => clk_i
);
end generate;
--process(clk_i)
-- begin
--for i in c_num_bytes-1 downto 0 loop
-- if rising_edge(clk_i) then
-- if (bwe_i(i) = '1') then
-- sram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i) <= d_i(8*i+7 downto 8*i);
-- else
---- q_o(8*i+7 downto 8*i) <= sram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
-- end if;
--end if;
-- end loop;
-- end process;
--q_o(8*i+7 downto 8*i) <= sram(conv_integer(unsigned(a_i)))(8*i+7 downto 8*i);
--end generate;
--q_o <= sram(conv_integer(unsigned(a_i)));
end Behavioral;
hdl/boards/vfc/sim/testbench/VME64x_Package.vhd
View file @ 2891a297
......@@ -18,7 +18,7 @@ use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use work.all;
use work.VME_pack.all;
use work.vme64x_pack.all;
package VME64x is
......@@ -65,7 +65,7 @@ type t_Buffer_MBLT is array (0 to 258) of std_logic_vector(63 downto 0); --
--The buffer has 258 positions, not 256; the last position is for test the error if i transfer more of 256 bytes.
type t_dataTransferType is (D08Byte0, D08Byte1, D08Byte2, D08Byte3, D16Byte01, D16Byte23, D32); -- for D64 use dataTransferType D32!
type t_AddressingType is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
type t_Addressing_Type is (A24, A24_BLT, A24_MBLT, A24_LCK, CR_CSR, A16, A16_LCK, A32, A32_BLT, A32_MBLT, A32_LCK,
A64, A64_BLT, A64_MBLT, A64_LCK, A32_2eVME, A64_2eVME, A32_2eSST, A64_2eSST, error);
......@@ -140,7 +140,7 @@ constant ADER2_2e_b : std_logic_vector(31 downto 0) := BA(7 downto 3) & "0000000
constant c_FUNC0_ADER_1 : std_logic_vector := x"7FF6B";
constant c_FUNC0_ADER_2 : std_logic_vector := x"7FF67";
constant c_FUNC0_ADER_3 : std_logic_vector := x"7FF63";
constant c_BYTES0 : std_logic_vector := x"7FF3b";
constant c_MBLT_Endian : std_logic_vector := x"7Ff53";
constant c_IRQ_Vector : std_logic_vector := x"7FF5F";
constant c_IRQ_level : std_logic_vector := x"7FF5B";
......
hdl/boards/vfc/sim/testbench/VME64x_SIM_Package.vhd
View file @ 2891a297
......@@ -18,8 +18,8 @@ use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.numeric_std.unsigned;
use work.all;
use work.VME_pack.all;
use work.vme64x_pack.all;
use work.VME64x.all;
use work.VME_CR_pack.all;
use std.textio.all;
......@@ -30,87 +30,87 @@ package VME64xSim is
-- function <function_name> (signal <signal_name> : in <type_declaration>) return <type_declaration>;
procedure WriteCSR (c_address : in std_logic_vector(19 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure S_Write (v_address : in std_logic_vector(63 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64S_Write (v_address : in std_logic_vector(63 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64S_Read (v_address : in std_logic_vector(63 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure S_Read (v_address : in std_logic_vector(63 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure Blt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure Blt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64Blt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64Blt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure Mblt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64Mblt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure Mblt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure A64Mblt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure Interrupt_Handler(signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record; signal s_dataToReceive : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type);
procedure ReadCR_CSR(c_address : in std_logic_vector(19 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure SetAmAddress (signal s_dataTransferType : in t_dataTransferType;
signal s_AddressingType : in t_AddressingType; Vme64xAM : out std_logic_vector(5 downto 0);
signal s_AddressingType : in t_Addressing_Type; Vme64xAM : out std_logic_vector(5 downto 0);
DataType : out std_logic_vector(3 downto 0));
procedure SetXAmAddress(signal s_AddressingType : in t_AddressingType; v_XAm : out std_logic_vector(7 downto 0));
procedure SetXAmAddress(signal s_AddressingType : in t_Addressing_Type; v_XAm : out std_logic_vector(7 downto 0));
procedure A64SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_AddressingType; v_address : out std_logic_vector(63 downto 0));
procedure A64SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_Addressing_Type; v_address : out std_logic_vector(63 downto 0));
procedure ShiftData (write_n : in std_logic; signal s_dataTransferType : in t_dataTransferType; signal s_dataToShift : in std_logic_vector(31 downto 0); v_dataToShiftOut : out std_logic_vector(31 downto 0));
procedure SetCrCsrAddress (c_address : in std_logic_vector(19 downto 0); v_address : out std_logic_vector(31 downto 0));
procedure SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_AddressingType; v_address : out std_logic_vector(31 downto 0));
procedure ControlCR (signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; signal VME64xBus_In : in VME64xBusIn_Record;
procedure SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_Addressing_Type; v_address : out std_logic_vector(31 downto 0));
procedure ControlCR (signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; signal VME64xBus_In : in VME64xBusIn_Record;
signal s_dataToReceive : inout std_logic_vector(31 downto 0); signal VME64xBus_Out : out VME64xBusOut_Record);
procedure TWOeVME_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_AddressingType : in t_AddressingType; v_beat_count : in std_logic_vector(7 downto 0);
signal s_AddressingType : in t_Addressing_Type; v_beat_count : in std_logic_vector(7 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
procedure TWOeVME_read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_AddressingType : in t_AddressingType; v_beat_count : in std_logic_vector(7 downto 0);
signal s_AddressingType : in t_Addressing_Type; v_beat_count : in std_logic_vector(7 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record);
end VME64xSim;
......@@ -119,7 +119,7 @@ end VME64xSim;
package body VME64xSim is
procedure WriteCSR (c_address : in std_logic_vector(19 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -183,7 +183,7 @@ begin
end ;
procedure ReadCR_CSR (c_address : in std_logic_vector(19 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -254,7 +254,7 @@ begin
end ReadCR_CSR;
procedure SetAmAddress (signal s_dataTransferType : in t_dataTransferType;
signal s_AddressingType : in t_AddressingType; Vme64xAM : out std_logic_vector (5 downto 0);
signal s_AddressingType : in t_Addressing_Type; Vme64xAM : out std_logic_vector (5 downto 0);
DataType : out std_logic_vector (3 downto 0)) is
begin
......@@ -327,7 +327,7 @@ DataType : out std_logic_vector (3 downto 0)) is
v_address := x"00" & not VME_GA(4 downto 0) & c_address(18 downto 0);
end SetCrCsrAddress;
procedure ControlCR (signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; signal VME64xBus_In : in VME64xBusIn_Record;
procedure ControlCR (signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; signal VME64xBus_In : in VME64xBusIn_Record;
signal s_dataToReceive : inout std_logic_vector(31 downto 0); signal VME64xBus_Out : out VME64xBusOut_Record) is
......@@ -358,7 +358,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure S_Write (v_address : in std_logic_vector(63 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -417,7 +417,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end ;
procedure S_Read (v_address : in std_logic_vector(63 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -482,7 +482,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
--------------------------------------------------------------------------
procedure Blt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -546,7 +546,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure Blt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -606,7 +606,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure Mblt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
......@@ -680,7 +680,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure Mblt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -757,7 +757,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_AddressingType; v_address : out std_logic_vector(31 downto 0)) is
procedure SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_Addressing_Type; v_address : out std_logic_vector(31 downto 0)) is
begin
case s_AddressingType is
......@@ -774,7 +774,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end case;
end;
procedure A64SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_AddressingType; v_address : out std_logic_vector(63 downto 0)) is
procedure A64SetAddress (c_address : in std_logic_vector(63 downto 0); signal s_AddressingType : in t_Addressing_Type; v_address : out std_logic_vector(63 downto 0)) is
begin
case s_AddressingType is
......@@ -791,21 +791,19 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure Interrupt_Handler(signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record; signal s_dataToReceive : in std_logic_vector(31 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType) is
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type) is
--variable v_dataTransferType : t_dataTransferType;
--variable v_AddressingType : t_AddressingType;
--variable v_AddressingType : t_Addressing_Type;
variable v_address : std_logic_vector(63 downto 0);
--variable v_dataToReceive : std_logic_vector(31 downto 0);
variable ti : time;
begin
report "Sono qui bella 1!";
wait until VME64xBus_In.Vme64xIRQ /= x"0000000";
report "Sono qui bella 2!";
ti := now;
--wait until VME64xBus_In.Vme64xIRQ /= x"0000000";
if VME64xBus_In.Vme64xDtackN /='1' or VME64xBus_In.Vme64xBerrN /='0' then
wait until VME64xBus_In.Vme64xDtackN ='1' and VME64xBus_In.Vme64xBerrN = '0';
end if;
report "Sono qui bella 3!";
--initialisation
VME64xBus_Out.Vme64xAsN <='1';
VME64xBus_Out.Vme64xWRITEN <='1';
......@@ -823,8 +821,9 @@ DataType : out std_logic_vector (3 downto 0)) is
VME64xBus_Out.Vme64xAsN <='0';
VME64xBus_Out.Vme64xDs0N <='0';
VME64xBus_Out.Vme64xDs1N <='0';
wait until (VME64xBus_In.Vme64xDtackN = '0' or VME64xBus_In.Vme64xBerrN = '1');
wait until (VME64xBus_In.Vme64xDtackN = '0' or VME64xBus_In.Vme64xBerrN = '1' or (now > (ti + 2 us)));
wait for 10 ns;
if (VME64xBus_In.Vme64xDtackN = '0') then
VME64xBus_Out.Vme64xAsN <='1';
VME64xBus_Out.Vme64xDs0N <='1';
VME64xBus_Out.Vme64xDs1N <='1';
......@@ -838,11 +837,19 @@ DataType : out std_logic_vector (3 downto 0)) is
--v_dataToReceive := x"00000001";
S_Read(v_address => v_address, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
else
VME64xBus_Out.Vme64xAsN <='1';
VME64xBus_Out.Vme64xDs0N <='1';
VME64xBus_Out.Vme64xDs1N <='1';
VME64xBus_Out.Vme64xIACK <= '1';
VME64xBus_Out.Vme64xLWORDN <='1';
VME64xBus_Out.Vme64xIACKIN <= '1';
wait for 30 ns;
end if;
end;
procedure A64S_Write (v_address : in std_logic_vector(63 downto 0); signal s_dataToSend : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -907,7 +914,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure A64S_Read (v_address : in std_logic_vector(63 downto 0); signal s_dataToReceive : in std_logic_vector(31 downto 0); -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType;
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type;
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -980,7 +987,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure A64Blt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record)is
variable n : integer;
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -1049,7 +1056,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure A64Blt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_BLT : in t_Buffer_BLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
......@@ -1123,7 +1130,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure A64Mblt_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record)is
variable n : integer;
variable Vme64xAM : std_logic_vector(5 downto 0);
......@@ -1198,7 +1205,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure A64Mblt_Read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_AddressingType; num : in std_logic_vector(8 downto 0);
signal s_dataTransferType : in t_dataTransferType; signal s_AddressingType : in t_Addressing_Type; num : in std_logic_vector(8 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
......@@ -1277,7 +1284,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure SetXAmAddress(signal s_AddressingType : in t_AddressingType; v_XAm : out std_logic_vector(7 downto 0))is
procedure SetXAmAddress(signal s_AddressingType : in t_Addressing_Type; v_XAm : out std_logic_vector(7 downto 0))is
begin
case s_AddressingType is
when A32_2eVME => v_XAm := c_A32_2eVME;
......@@ -1290,7 +1297,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure TWOeVME_write(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_AddressingType : in t_AddressingType; v_beat_count : in std_logic_vector(7 downto 0);
signal s_AddressingType : in t_Addressing_Type; v_beat_count : in std_logic_vector(7 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
......@@ -1378,7 +1385,7 @@ DataType : out std_logic_vector (3 downto 0)) is
end;
procedure TWOeVME_read(v_address : in std_logic_vector(63 downto 0); signal s_Buffer_MBLT : in t_Buffer_MBLT; -- this procedure is for A16, A24, A32 address type
signal s_AddressingType : in t_AddressingType; v_beat_count : in std_logic_vector(7 downto 0);
signal s_AddressingType : in t_Addressing_Type; v_beat_count : in std_logic_vector(7 downto 0);
signal VME64xBus_In : in VME64xBusIn_Record; signal VME64xBus_Out : out VME64xBusOut_Record) is
variable n : integer;
......
hdl/boards/vfc/sim/testbench/VME64x_TB.vhd
View file @ 2891a297
--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 15:50:49 03/28/2012
-- Design Name:
-- Module Name: /opt/ohwr/CERN_VME64x_modif/HDL/VFC_ISE_core/hdl/VME64x_TB.vhd
-- Project Name: VME64xTest
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: TOP_LEVEL
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
library std;
......@@ -34,19 +9,14 @@ use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;
use IEEE.numeric_std.all;
use IEEE.numeric_std.unsigned;
use work.all;
use work.VME_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
use work.VME64xSim.all;
use work.VME64x.all;
use work.wishbone_pkg.all;
use std.textio.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
use work.vme64x_pack.all;
ENTITY VME64x_TB IS
END VME64x_TB;
......@@ -81,7 +51,6 @@ ARCHITECTURE behavior OF VME64x_TB IS
VME_ADDR_DIR_o : OUT std_logic;
VME_ADDR_OE_N_o : OUT std_logic;
RST_i : IN std_logic;
rst_n_i : IN std_logic;
Reset : IN std_logic
);
END COMPONENT;
......@@ -99,7 +68,6 @@ ARCHITECTURE behavior OF VME64x_TB IS
signal VME_IACKIN_n_i : std_logic := '1';
signal VME_IACK_n_i : std_logic := '1';
signal RST_i : std_logic := '0';
signal rst_n_i : std_logic := '0';
signal Reset : std_logic := '1';
--BiDirs
......@@ -127,7 +95,7 @@ ARCHITECTURE behavior OF VME64x_TB IS
signal s_Buffer_BLT : t_Buffer_BLT;
signal s_Buffer_MBLT : t_Buffer_MBLT;
signal s_dataTransferType : t_dataTransferType;
signal s_AddressingType : t_AddressingType;
signal s_AddressingType : t_Addressing_Type;
-- Control signals
signal s_dataToSendOut : std_logic_vector(31 downto 0);
......@@ -174,7 +142,6 @@ BEGIN
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
RST_i => RST_i,
rst_n_i => rst_n_i,
Reset => Reset
);
......@@ -246,55 +213,55 @@ test_VME64x : process
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
-- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
s_dataToReceive <= x"00000009";
ReadCR_CSR(c_address => c_FUNC0_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
--read ADER0:
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
-- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
s_dataToReceive <= x"000000c0";
ReadCR_CSR(c_address => c_FUNC0_ADER_3, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
-- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
s_dataToReceive <= x"00000000";
ReadCR_CSR(c_address => c_FUNC0_ADER_2, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
-- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
s_dataToReceive <= x"00000000";
ReadCR_CSR(c_address => c_FUNC0_ADER_1, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
--
-- wait for 30 ns;
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- -- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
-- s_dataToReceive <= x"00000024";
-- ReadCR_CSR(c_address => c_FUNC0_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 30 ns;
--
-- --read ADER0:
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- -- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
-- s_dataToReceive <= x"000000c0";
-- ReadCR_CSR(c_address => c_FUNC0_ADER_3, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 30 ns;
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- -- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
-- s_dataToReceive <= x"00000000";
-- ReadCR_CSR(c_address => c_FUNC0_ADER_2, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 30 ns;
--
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- -- Put the data to receive in the 8 lsb also if you are using D08Byte1 or D08Byte2 ecc..
-- s_dataToReceive <= x"00000000";
-- ReadCR_CSR(c_address => c_FUNC0_ADER_1, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 30 ns;
--
report "START WRITE CSR";
......@@ -536,8 +503,8 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A16_S(31 downto 24);
WriteCSR(c_address => c_FUNC0_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_dataToSend <= x"000000" & ADER0_A16_S(31 downto 24);
WriteCSR(c_address => c_FUNC2_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
......@@ -548,7 +515,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A16_S(23 downto 16);
WriteCSR(c_address => c_FUNC0_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC2_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
......@@ -558,7 +525,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A16_S(15 downto 8);
WriteCSR(c_address => c_FUNC0_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC2_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
......@@ -569,183 +536,183 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A16_S(7 downto 0);
WriteCSR(c_address => c_FUNC0_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC2_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
-- start write ADER1
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64(31 downto 24);
WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64(23 downto 16);
WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64(15 downto 8);
WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64(7 downto 0);
WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
-- start write ADER2 (ADER1_b)
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64_b(31 downto 24);
WriteCSR(c_address => c_FUNC2_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64_b(23 downto 16);
WriteCSR(c_address => c_FUNC2_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64_b(15 downto 8);
WriteCSR(c_address => c_FUNC2_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER1_A64_b(7 downto 0);
WriteCSR(c_address => c_FUNC2_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
-- start write ADER3
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_A32_2eVME(31 downto 24);
WriteCSR(c_address => c_FUNC3_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_A32_2eVME(23 downto 16);
WriteCSR(c_address => c_FUNC3_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_A32_2eVME(15 downto 8);
WriteCSR(c_address => c_FUNC3_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_A32_2eVME(7 downto 0);
WriteCSR(c_address => c_FUNC3_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
-- start write ADER4 (ADER2_b)
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_2e_b(31 downto 24);
WriteCSR(c_address => c_FUNC4_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_2e_b(23 downto 16);
WriteCSR(c_address => c_FUNC4_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_2e_b(15 downto 8);
WriteCSR(c_address => c_FUNC4_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
-- s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
-- s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_2e_b(7 downto 0);
WriteCSR(c_address => c_FUNC4_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
-- s_dataToSend <= x"000000" & ADER1_A64(31 downto 24);
-- WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64(23 downto 16);
-- WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64(15 downto 8);
-- WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64(7 downto 0);
-- WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- -- start write ADER2 (ADER1_b)
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64_b(31 downto 24);
-- WriteCSR(c_address => c_FUNC2_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64_b(23 downto 16);
-- WriteCSR(c_address => c_FUNC2_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64_b(15 downto 8);
-- WriteCSR(c_address => c_FUNC2_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER1_A64_b(7 downto 0);
-- WriteCSR(c_address => c_FUNC2_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
-- -- start write ADER3
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_A32_2eVME(31 downto 24);
-- WriteCSR(c_address => c_FUNC3_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_A32_2eVME(23 downto 16);
-- WriteCSR(c_address => c_FUNC3_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_A32_2eVME(15 downto 8);
-- WriteCSR(c_address => c_FUNC3_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_A32_2eVME(7 downto 0);
-- WriteCSR(c_address => c_FUNC3_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
-- -- start write ADER4 (ADER2_b)
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_2e_b(31 downto 24);
-- WriteCSR(c_address => c_FUNC4_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_2e_b(23 downto 16);
-- WriteCSR(c_address => c_FUNC4_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_2e_b(15 downto 8);
-- WriteCSR(c_address => c_FUNC4_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
-- wait for 20 ns;
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_2e_b(7 downto 0);
-- WriteCSR(c_address => c_FUNC4_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
-- check some ADER byte :
......@@ -755,21 +722,21 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToReceive <= x"000000" & c_A16 &"00";
ReadCR_CSR(c_address => c_FUNC0_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
ReadCR_CSR(c_address => c_FUNC2_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
report "FUNC0_ADER_0 Correct!!!!";
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToReceive <= x"000000" & c_A64 &"00";
ReadCR_CSR(c_address => c_FUNC1_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
report "FUNC1_ADER_0 Correct!!!!";
-- s_dataTransferType <= D08Byte3;
-- s_AddressingType <= CR_CSR;
--
-- s_dataToReceive <= x"000000" & c_A64 &"00";
-- ReadCR_CSR(c_address => c_FUNC1_ADER_0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
-- report "FUNC1_ADER_0 Correct!!!!";
report "THE MASTER HAS WRITTEN CORRECTLY ALL THE ADERs $$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$$";
-- start write BAR
......@@ -1063,14 +1030,14 @@ test_VME64x : process
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------
-- The Master write again the ADER 0 for access with A24 mode!
-- The Master write again the ADER 1 for access with A24 mode!
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_S(31 downto 24);
WriteCSR(c_address => c_FUNC0_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1081,7 +1048,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_S(23 downto 16);
WriteCSR(c_address => c_FUNC0_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1091,7 +1058,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_S(15 downto 8);
WriteCSR(c_address => c_FUNC0_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1102,7 +1069,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_S(7 downto 0);
WriteCSR(c_address => c_FUNC0_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1390,6 +1357,13 @@ test_VME64x : process
VME64xBus_In => VME64xBus_in, VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToReceive <= x"00000040";
ReadCR_CSR(c_address => c_BYTES0, s_dataToReceive => s_dataToReceive, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_in,
VME64xBus_Out => VME64xBus_Out);
s_dataTransferType <= D32; -- Data transfer type is D32 also if the data width is 64!!
s_AddressingType <= A32_MBLT;
s_address <= x"0000000000000010"; --Put here a multiple of 8!!!
......@@ -1440,7 +1414,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(31 downto 24);
WriteCSR(c_address => c_FUNC0_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1451,7 +1425,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(23 downto 16);
WriteCSR(c_address => c_FUNC0_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1461,7 +1435,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(15 downto 8);
WriteCSR(c_address => c_FUNC0_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
......@@ -1472,7 +1446,7 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER0_A24_MBLT(7 downto 0);
WriteCSR(c_address => c_FUNC0_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
WriteCSR(c_address => c_FUNC1_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
-- ADER0 written
......@@ -1535,7 +1509,6 @@ test_VME64x : process
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000002";
--s_address <= x"0000000000000000";
WriteCSR(c_address => c_IRQ_level , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
......@@ -1552,6 +1525,14 @@ test_VME64x : process
WriteCSR(c_address => c_IRQ_Vector , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 10 ns;
--Test if the daisy chaine is working;
s_dataTransferType <= D32;
s_AddressingType <= A32;
s_dataToReceive <= x"00000003";
Interrupt_Handler(VME64xBus_In => VME64xBus_In,VME64xBus_Out => VME64xBus_Out,s_dataToReceive => s_dataToReceive,
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType);
--The master write FREQ register in the RAM
wait for 10 ns;
......@@ -1652,7 +1633,7 @@ test_VME64x : process
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--Check if the falling edge is passed on the IACKOUT daisy chain
--_____________________________________________________________________________________________________________________________________
--TEST A64
s_dataTransferType <= D08Byte3;
......@@ -1662,6 +1643,70 @@ test_VME64x : process
WriteCSR(c_address => c_FUNC4_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC4_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC4_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC4_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC3_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC3_ADER_2 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000000";
WriteCSR(c_address => c_FUNC3_ADER_1 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
wait for 20 ns;
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"00000004";
WriteCSR(c_address => c_FUNC3_ADER_0 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
s_dataTransferType <= D32;
......@@ -1813,32 +1858,32 @@ test_VME64x : process
s_dataTransferType => s_dataTransferType, s_AddressingType => s_AddressingType,
num => s_num, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
--__________________________________________________________________________________________________________________________________________
s_dataTransferType <= D08Byte3;
s_AddressingType <= CR_CSR;
s_dataToSend <= x"000000" & ADER2_A32_2eVME(31 downto 24);
WriteCSR(c_address => c_FUNC5_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
VME64xBus_Out => VME64xBus_Out);
s_AddressingType <= A32_2eVME;
s_beat_count <= "00001000";
s_address <= x"0000000000000010";
TWOeVME_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT,
s_AddressingType => s_AddressingType,
v_beat_count => s_beat_count, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
wait for 30 ns;
s_AddressingType <= A64_2eVME;
s_beat_count <= "00001000";
s_address <= x"0000000000000010";
TWOeVME_read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT,
s_AddressingType => s_AddressingType,
v_beat_count => s_beat_count, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
--
-- s_dataTransferType <= D08Byte3;
--
-- s_AddressingType <= CR_CSR;
--
-- s_dataToSend <= x"000000" & ADER2_A32_2eVME(31 downto 24);
-- WriteCSR(c_address => c_FUNC5_ADER_3 , s_dataToSend => s_dataToSend, s_dataTransferType => s_dataTransferType,
-- s_AddressingType => s_AddressingType, VME64xBus_In => VME64xBus_In,
-- VME64xBus_Out => VME64xBus_Out);
--
--
-- s_AddressingType <= A32_2eVME;
-- s_beat_count <= "00001000";
-- s_address <= x"0000000000000010";
-- TWOeVME_write(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT,
-- s_AddressingType => s_AddressingType,
-- v_beat_count => s_beat_count, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
--
-- wait for 30 ns;
-- s_AddressingType <= A64_2eVME;
-- s_beat_count <= "00001000";
-- s_address <= x"0000000000000010";
-- TWOeVME_read(v_address => s_address, s_Buffer_MBLT => s_Buffer_MBLT,
-- s_AddressingType => s_AddressingType,
-- v_beat_count => s_beat_count, VME64xBus_In => VME64xBus_In, VME64xBus_Out => VME64xBus_Out);
--
report "FINE///////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////";
......@@ -1923,11 +1968,9 @@ test_VME64x : process
wait for 50 ns;
VME_RST_n_i <= '0';
RST_i <= '1';
rst_n_i <= '0';
wait for 50 ns;
VME_RST_n_i <= '1';
RST_i <= '0';
rst_n_i <= '1';
wait for 600 ns;
wait;
......
hdl/boards/vfc/syn/VME64xTest.xise
View file @ 2891a297
......@@ -15,119 +15,126 @@
<version xil_pn:ise_version="13.1" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="../rtl/xwb_dpram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="Implementation" xil_pn:seqID="22"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME64xCore_NoIpTop.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="19"/>
<association xil_pn:name="Implementation" xil_pn:seqID="19"/>
</file>
<file xil_pn:name="../rtl/ram_8bits.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="../rtl/spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_bus.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/Buff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/common_components.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../vme64x-core/rtl/genram_pkg.vhd" xil_pn:type="FILE_VHDL"/>
<file xil_pn:name="../../../vme64x-core/rtl/gen_buff.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/TrueDpBlockRam.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
<file xil_pn:name="../../../vme64x-core/rtl/vme64x_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/DpBlockRam.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
<file xil_pn:name="../sim/testbench/VME64x_TB.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="25"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="62"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="62"/>
</file>
<file xil_pn:name="../rtl/TOP_LEVEL.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../sim/testbench/VME64x_SIM_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="23"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="63"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="63"/>
</file>
<file xil_pn:name="../sim/testbench/VME64x_TB.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="24"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="12"/>
<file xil_pn:name="../sim/testbench/VME64x_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="21"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="64"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="64"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CR_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
<file xil_pn:name="../SFpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CSR_pack.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../vme64x-core/rtl/VME_Access_Decode.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Funct_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Am_Match.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_pack.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Wb_master.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="../sim/testbench/VME64x_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="16"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME_swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../sim/testbench/VME64x_SIM_Package.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="17"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME_Init.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="../SFpga.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME64xCore_Top.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="20"/>
<association xil_pn:name="Implementation" xil_pn:seqID="20"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/FIFO.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
<file xil_pn:name="../../../vme64x-core/rtl/VME_CR_CSR_Space.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/VME_IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/SharedComps.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../vme64x-core/rtl/VME_SharedComps.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="../rtl/spram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="../rtl/ram_8bits.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../../../vme64x-core/rtl/VME_DpBlockRam.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/swapper.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="../../../../../CERN_VME64x_modif/HDL/VFC_ISE_core/hdl/common_components.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="18"/>
<association xil_pn:name="Implementation" xil_pn:seqID="18"/>
<file xil_pn:name="../rtl/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="../../../../../CERN_VME64x_modif/HDL/VFC_ISE_core/hdl/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="../rtl/wishbone_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="Implementation" xil_pn:seqID="17"/>
</file>
<file xil_pn:name="../../../../../CERN_VME64x_modif/HDL/VFC_ISE_core/hdl/genram_pkg.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/IRQ_Controller.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="../rtl/IRQ_generator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
<association xil_pn:name="Implementation" xil_pn:seqID="16"/>
</file>
<file xil_pn:name="../../../vme64x-core/rtl/vme64x_core.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
<file xil_pn:name="../rtl/xwb_ram.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="22"/>
<association xil_pn:name="Implementation" xil_pn:seqID="21"/>
</file>
</files>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -150,20 +157,21 @@
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Name" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="true" xil_pn:valueState="non-default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -173,10 +181,11 @@
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Data Flow window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF ModelSim" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xc6slx150t" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Family" xil_pn:value="Spartan6" xil_pn:valueState="non-default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-2" xil_pn:valueState="default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
......@@ -203,7 +212,7 @@
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="JTAG Clock" xil_pn:valueState="non-default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -226,6 +235,7 @@
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -237,6 +247,7 @@
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HDL Instantiation Template Target Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore Pre-Compiled Library Warning Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -247,6 +258,7 @@
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
......@@ -263,8 +275,8 @@
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="List window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Behavioral Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Fit Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Map Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Par Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Log All Signals In Post-Translate Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -275,9 +287,8 @@
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Fit UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="uut" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Map UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="ModelSim Post-Par UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
......@@ -296,11 +307,14 @@
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Fit" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VCOM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VLOG Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other VSIM Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -311,7 +325,7 @@
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Existing Symbol" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="For Inputs and Outputs" xil_pn:valueState="non-default"/>
<property xil_pn:name="Package" xil_pn:value="fgg676" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
......@@ -364,12 +378,14 @@
<property xil_pn:name="Retiming Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="work.VME64x_TB" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="uut" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -378,17 +394,21 @@
<property xil_pn:name="Signal window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Resolution" xil_pn:value="Default (1 ps)" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Modelsim" xil_pn:value="1000ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Source window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-2" xil_pn:valueState="non-default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.VME64x_TB" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Structure window" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Modelsim-SE VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="../../svec/SVEC.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -404,6 +424,10 @@
<property xil_pn:name="Use Custom Do File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Do File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Explicit Declarations Only" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
......@@ -417,6 +441,7 @@
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Syntax" xil_pn:value="93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Variables window" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
......@@ -435,12 +460,12 @@
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostFitSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="Architecture|VME64x_TB|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-03-28T12:28:48" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="A748943FFB0B0ACDAF8C2208B8E71EB6" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2012-06-25T11:58:41" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="7041170BED0C04ACD164D2C85EA89384" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
......@@ -449,13 +474,4 @@
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>
hdl/vme64x-core/rtl/VME64xCore_Top.vhd 0 → 100755
View file @ 2891a297
--_____________________________________________________________________________|
-- VME TO WB INTERFACE |
-- |
-- CERN,BE/CO-HT |
--_____________________________________________________________________________|
-- File: VME64xCore_Top.vhd |
--_____________________________________________________________________________|
-- Description:
-- This core implements an interface to transfer data between the VMEbus and the WBbus.
-- This core is a Slave in the VME side and Master in the WB side.
-- The main blocks: |
-- |
-- ________________________________________________________________
-- | VME64xCore_Top.vhd |
-- |__ ____________________ __________________ |
-- | | | | | | |
-- |S | | VME_bus.vhd | | | |
-- V |A | | | |VME_to_WB_FIFO.vhd| |
-- M |M | | | | | (not yet | |
-- E |P | | VME | WB | | implemented) | | W
-- |L | | slave | master | | | | B
-- B |I | | | | _______ | | |
-- U |N | | | | | CSR | | | | B
-- S |G | | | | |______ | |__________________| | U
-- | | | | | | _________________ | S
-- | | | | |CRAM | | | |
-- |__| | | |______ | | IRQ_Controller | |
-- | | | | | | | |
-- | | | | CR | | | |
-- | |____________________| |_______| |_________________| |
-- |________________________________________________________________|
--
-- All the VMEbus's asynchronous signals must be sampled 2 or 3 times to avoid |
-- metastability problem.
-- The main component is the VME_bus on the left of the block diagram. Inside this component
-- you can find the main finite state machine who coordinates all the synchronisms.
-- The WB protocol is more faster than the VME protocol so to make independent
-- the two protocols a FIFO memory can be introduced.
-- The FIFO is necessary only during 2eSST access mode.
-- During the block transfer without FIFO the VME_bus accesses directly at the Wb bus in
-- Single pipelined read/write mode. If this is the only Wb master this solution is
-- better than the solution with FIFO.
-- In this base version of the core the FIFO is not implemented indeed the 2e access modes
-- aren't supported yet.
-- A Configuration ROM/Control Status Register (CR/CSR) address space has been
-- introduced. The CR/CSR space can be accessed with the data transfer type
-- D08_3, D16_23, D32.
-- To access the CR/CSR space: AM = 0x2f --> this is A24 addressing type, SINGLE
-- transfer type. Base Address = Slot Number.
-- This interface is provided with an Interrupter. The IRQ Controller receives from
-- the Application (WB bus) an interrupt request and transfers this interrupt request
-- on the VMEbus. This component acts also during the Interrupt acknowledge cycle,
-- sending the status/ID to the Interrupt handler.
-- Inside each component is possible to read a more detailed description.
-- Access modes supported:
-- http://www.ohwr.org/projects/vme64x-core/repository/changes/trunk/
-- documentation/user_guides/VFC_access.pdf
--______________________________________________________________________________
--
-- References:
-- The VMEbus specification ANSI/IEEE STD1014-1987
-- The VME64std ANSI/VITA 1-1994
-- The VME64x ANSI/VITA 1.1-1997
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
entity VME64xCore_Top is
port(
clk_i : in std_logic;
-- for the IRQ_Generator and relative registers
reset_o : out std_logic; -- asserted when '1'
-- VME
VME_AS_n_i : in std_logic;
VME_RST_n_i : in std_logic; -- asserted when '0'
VME_WRITE_n_i : in std_logic;
VME_AM_i : in std_logic_vector(5 downto 0);
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_BERR_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKIN_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
VME_IACKOUT_n_o : out std_logic;
-- VME buffers
VME_DTACK_OE_o : out std_logic;
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
-- WishBone
RST_i : in std_logic;
DAT_i : in std_logic_vector(63 downto 0);
DAT_o : out std_logic_vector(63 downto 0);
ADR_o : out std_logic_vector(63 downto 0);
CYC_o : out std_logic;
ERR_i : in std_logic;
RTY_i : in std_logic;
SEL_o : out std_logic_vector(7 downto 0);
STB_o : out std_logic;
ACK_i : in std_logic;
WE_o : out std_logic;
STALL_i : in std_logic;
-- IRQ Generator
INT_ack : out std_logic;
IRQ_i : in std_logic;
-- Add by Davide for debug:
leds : out std_logic_vector(7 downto 0)
);
end VME64xCore_Top;
architecture RTL of VME64xCore_Top is
signal s_CRAMdataOut : std_logic_vector(7 downto 0);
signal s_CRAMaddr : std_logic_vector(18 downto 0);
signal s_CRAMdataIn : std_logic_vector(7 downto 0);
signal s_CRAMwea : std_logic;
signal s_CRaddr : std_logic_vector(11 downto 0);
signal s_CRdata : std_logic_vector(7 downto 0);
signal s_RW : std_logic;
signal s_reset : std_logic;
signal s_IRQlevelReg : std_logic_vector(7 downto 0);
signal s_FIFOreset : std_logic;
signal s_VME_DATA_IRQ : std_logic_vector(31 downto 0);
signal s_VME_DATA_VMEbus : std_logic_vector(31 downto 0);
signal s_VME_DATA_b : std_logic_vector(31 downto 0);
signal s_DATi_sample : std_logic_vector(63 downto 0);
signal s_fifo : std_logic;
signal s_VME_DTACK_VMEbus : std_logic;
signal s_VME_DTACK_IRQ : std_logic;
signal s_VME_DTACK_OE_VMEbus : std_logic;
signal s_VME_DTACK_OE_IRQ : std_logic;
signal s_VME_DATA_DIR_VMEbus : std_logic;
signal s_VME_DATA_DIR_IRQ : std_logic;
signal s_INT_Level : std_logic_vector(7 downto 0);
signal s_INT_Vector : std_logic_vector(7 downto 0);
signal s_VME_IRQ_n_o : std_logic_vector(6 downto 0);
signal s_reset_IRQ : std_logic;
signal s_VME_GA_oversampled : std_logic_vector(5 downto 0);
signal s_CSRData_o : std_logic_vector(7 downto 0);
signal s_CSRData_i : std_logic_vector(7 downto 0);
signal s_CrCsrOffsetAddr : std_logic_vector(18 downto 0);
signal s_Ader0 : std_logic_vector(31 downto 0);
signal s_Ader1 : std_logic_vector(31 downto 0);
signal s_Ader2 : std_logic_vector(31 downto 0);
signal s_Ader3 : std_logic_vector(31 downto 0);
signal s_Ader4 : std_logic_vector(31 downto 0);
signal s_Ader5 : std_logic_vector(31 downto 0);
signal s_Ader6 : std_logic_vector(31 downto 0);
signal s_Ader7 : std_logic_vector(31 downto 0);
signal s_en_wr_CSR : std_logic;
signal s_err_flag : std_logic;
signal s_reset_flag : std_logic;
signal s_Sw_Reset : std_logic;
signal s_ModuleEnable : std_logic;
signal s_MBLT_Endian : std_logic_vector(2 downto 0);
signal s_BAR : std_logic_vector(4 downto 0);
signal s_time : std_logic_vector(39 downto 0);
signal s_bytes : std_logic_vector(12 downto 0);
-- Oversampled input signals
signal VME_RST_n_oversampled : std_logic;
signal VME_AS_n_oversampled : std_logic;
signal VME_AS_n_oversampled1 : std_logic;
signal VME_LWORD_n_oversampled : std_logic;
signal VME_WRITE_n_oversampled : std_logic;
signal VME_DS_n_oversampled : std_logic_vector(1 downto 0);
signal VME_DS_n_oversampled_1 : std_logic_vector(1 downto 0);
signal VME_GA_oversampled : std_logic_vector(5 downto 0);
signal VME_ADDR_oversampled : std_logic_vector(31 downto 1);
signal VME_DATA_oversampled : std_logic_vector(31 downto 0);
signal VME_AM_oversampled : std_logic_vector(5 downto 0);
signal VME_IACK_n_oversampled : std_logic;
signal VME_IACKIN_n_oversampled : std_logic;
begin
AMinputSample : RegInputSample
generic map(
width => 6
)
port map(
reg_i => VME_AM_i,
reg_o => VME_AM_oversampled,
clk_i => clk_i
);
DATAinputSample : RegInputSample
generic map(
width => 32
)
port map (
reg_i => VME_DATA_b_i,
reg_o => VME_DATA_oversampled,
clk_i => clk_i
);
ADDRinputSample : RegInputSample
generic map(
width => 31
)
port map(
reg_i => VME_ADDR_b_i,
reg_o => VME_ADDR_oversampled,
clk_i => clk_i
);
GAinputSample : RegInputSample
generic map(
width => 6
)
port map(
reg_i => VME_GA_i,
reg_o => VME_GA_oversampled,
clk_i => clk_i
);
DSinputSample : RegInputSample
generic map(
width => 2
)
port map(
reg_i => VME_DS_n_i,
reg_o => VME_DS_n_oversampled,
clk_i => clk_i
);
WRITEinputSample : SigInputSample
port map(
sig_i => VME_WRITE_n_i,
sig_o => VME_WRITE_n_oversampled,
clk_i => clk_i
);
LWORDinputSample : SigInputSample
port map(
sig_i => VME_LWORD_n_b_i,
sig_o => VME_LWORD_n_oversampled,
clk_i => clk_i
);
ASinputSample1 : DoubleSigInputSample -- for the IRQ_Controller
port map(
sig_i => VME_AS_n_i,
sig_o => VME_AS_n_oversampled1,
clk_i => clk_i
);
ASinputSample : SigInputSample
port map(
sig_i => VME_AS_n_i,
sig_o => VME_AS_n_oversampled,
clk_i => clk_i
);
RSTinputSample : SigInputSample
port map(
sig_i => VME_RST_n_i,
sig_o => VME_RST_n_oversampled,
clk_i => clk_i
);
IACKinputSample : SigInputSample
port map(
sig_i => VME_IACK_n_i,
sig_o => VME_IACK_n_oversampled,
clk_i => clk_i
);
IACKINinputSample : SigInputSample
port map(
sig_i => VME_IACKIN_n_i,
sig_o => VME_IACKIN_n_oversampled,
clk_i => clk_i
);
Inst_VME_bus: VME_bus PORT MAP(
clk_i => clk_i,
reset_o => s_reset, -- asserted when '1'
-- VME
VME_RST_n_i => VME_RST_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_LWORD_n_b_o => VME_LWORD_n_b_o,
VME_LWORD_n_b_i => VME_LWORD_n_oversampled,
VME_RETRY_n_o => VME_RETRY_n_o,
VME_RETRY_OE_o => VME_RETRY_OE_o,
VME_WRITE_n_i => VME_WRITE_n_oversampled,
VME_DS_n_i => VME_DS_n_oversampled,
VME_GA_i => VME_GA_oversampled,
VME_DTACK_n_o => s_VME_DTACK_VMEbus,
VME_DTACK_OE_o => s_VME_DTACK_OE_VMEbus,
VME_BERR_o => VME_BERR_o,
VME_ADDR_b_i => VME_ADDR_oversampled,
VME_ADDR_b_o => VME_ADDR_b_o,
VME_ADDR_DIR_o => VME_ADDR_DIR_o,
VME_ADDR_OE_N_o => VME_ADDR_OE_N_o,
VME_DATA_b_i => VME_DATA_oversampled,
VME_DATA_b_o => s_VME_DATA_VMEbus,
VME_DATA_DIR_o => s_VME_DATA_DIR_VMEbus,
VME_DATA_OE_N_o => VME_DATA_OE_N_o,
VME_AM_i => VME_AM_oversampled,
VME_BBSY_n_i => VME_BBSY_n_i, -- not used
VME_IACK_n_i => VME_IACK_n_oversampled,
-- WB
memReq_o => STB_o,
memAckWB_i => ACK_i,
wbData_o => DAT_o,
wbData_i => s_DATi_sample,
locAddr_o => ADR_o,
wbSel_o => SEL_o,
RW_o => s_RW,
cyc_o => CYC_o,
err_i => ERR_i,
rty_i => RTY_i,
stall_i => STALL_i,
-- FIFO signals; the FIFO is not implemented in this
-- base version of the core so the relative signals
-- are "open"
psize_o => open,
VMEtoWB => open,
WBtoVME => open,
FifoMux => open,
transfer_done_i => '1',
transfer_done_o => open,
-- CR/CSR signals
CRAMaddr_o => s_CRAMaddr,
CRAMdata_o => s_CRAMdataIn,
CRAMdata_i => s_CRAMdataOut,
CRAMwea_o => s_CRAMwea,
CRaddr_o => s_CRaddr,
CRdata_i => s_CRdata,
VME_GA_oversampled_o => s_VME_GA_oversampled,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
CSRData_o => s_CSRData_o,
CSRData_i => s_CSRData_i,
err_flag_o => s_err_flag,
reset_flag_i => s_reset_flag,
Ader0 => s_Ader0,
Ader1 => s_Ader1,
Ader2 => s_Ader2,
Ader3 => s_Ader3,
Ader4 => s_Ader4,
Ader5 => s_Ader5,
Ader6 => s_Ader6,
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
MBLT_Endian_i => s_MBLT_Endian,
Sw_Reset => s_Sw_Reset,
BAR_i => s_BAR,
numBytes => s_bytes,
transfTime => s_time,
-- debug
leds => leds
);
---------------------------------------------------------------------------------
-- output
VME_IRQ_n_o <= not s_VME_IRQ_n_o; --The buffers will invert again the logic level
WE_o <= not s_RW;
reset_o <= s_reset;
INT_ack <= s_VME_DTACK_IRQ;
--------------------------------------------------------------------------------
--Multiplexer added on the output signal used by either VMEbus.vhd and the IRQ_controller.vhd
VME_DATA_b_o <= s_VME_DATA_VMEbus WHEN VME_IACK_n_oversampled ='1' ELSE
s_VME_DATA_IRQ;
VME_DTACK_n_o <= s_VME_DTACK_VMEbus WHEN VME_IACK_n_oversampled ='1' ELSE
s_VME_DTACK_IRQ;
VME_DTACK_OE_o <= s_VME_DTACK_OE_VMEbus WHEN VME_IACK_n_oversampled ='1' ELSE
s_VME_DTACK_OE_IRQ;
VME_DATA_DIR_o <= s_VME_DATA_DIR_VMEbus WHEN VME_IACK_n_oversampled ='1' ELSE
s_VME_DATA_DIR_IRQ;
--------------------------------------------------------------------------------
-- Interrupter
Inst_VME_IRQ_Controller: VME_IRQ_Controller PORT MAP(
clk_i => clk_i,
reset => s_reset_IRQ, -- asserted when low
VME_IACKIN_n_i => VME_IACKIN_n_oversampled,
VME_AS_n_i => VME_AS_n_oversampled,
VME_AS1_n_i => VME_AS_n_oversampled1,
VME_DS_n_i => VME_DS_n_oversampled,
VME_LWORD_n_i => VME_LWORD_n_oversampled,
VME_ADDR_123 => VME_ADDR_oversampled(3 downto 1),
INT_Level => s_INT_Level,
INT_Vector => s_INT_Vector ,
INT_Req => IRQ_i,
VME_IRQ_n_o => s_VME_IRQ_n_o,
VME_IACKOUT_n_o => VME_IACKOUT_n_o,
VME_DTACK_n_o => s_VME_DTACK_IRQ,
VME_DTACK_OE_o => s_VME_DTACK_OE_IRQ,
VME_DATA_o => s_VME_DATA_IRQ,
DataDir => s_VME_DATA_DIR_IRQ
);
s_reset_IRQ <= not(s_reset);
--------------------------------------------------------------------------
--CR/CSR space
Inst_VME_CR_CSR_Space: VME_CR_CSR_Space PORT MAP(
clk_i => clk_i,
s_reset => s_reset,
CR_addr => s_CRaddr,
CR_data => s_CRdata,
CRAM_addr => s_CRAMaddr,
CRAM_data_o => s_CRAMdataOut,
CRAM_data_i => s_CRAMdataIn,
CRAM_Wen => s_CRAMwea,
en_wr_CSR => s_en_wr_CSR,
CrCsrOffsetAddr => s_CrCsrOffsetAddr,
VME_GA_oversampled => s_VME_GA_oversampled,
locDataIn => s_CSRData_o,
s_err_flag => s_err_flag,
s_reset_flag => s_reset_flag,
CSRdata => s_CSRData_i,
Ader0 => s_Ader0,
Ader1 => s_Ader1,
Ader2 => s_Ader2,
Ader3 => s_Ader3,
Ader4 => s_Ader4,
Ader5 => s_Ader5,
Ader6 => s_Ader6,
Ader7 => s_Ader7,
ModuleEnable => s_ModuleEnable,
Sw_Reset => s_Sw_Reset,
MBLT_Endian_o => s_MBLT_Endian,
BAR_o => s_BAR,
INT_Level => s_INT_Level,
numBytes => s_bytes,
transfTime => s_time,
INT_Vector => s_INT_Vector
);
------------------------------------------------------------------------
-- This process sampling the WB data input; this is a warranty that this
-- data will be stable during all the time the VME_bus component needs to
-- transfers its to the VME bus.
process(clk_i)
begin
if rising_edge(clk_i) then
if ACK_i = '1' then
s_DATi_sample <= DAT_i;
end if;
end if;
end process;
------------------------------------------------------------------------
end RTL;
hdl/vme64x-core/rtl/VME_Access_Decode.vhd 0 → 100644
View file @ 2891a297
--__________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--_________________________________________________________________________________
-- File: VME_Access_Decode.vhd
--_________________________________________________________________________________
-- Description: This component check if the board is addressed and if it is, allows
-- the access to CR/CSR space asserting the Confaccess signal, or allows the access
-- to WB bus asserting the CardSel signal.
-- The access to CR/CSR space is possible if:
-- 1) Addr[23:19] = BAR[7:3], (BAR[7:3] = not VME_GA_i), (VME_GA_i = not Slot number)
-- 2) AM = 0x2f
-- 3) The initialization is finished (wait about 8800 ns after power-up or software reset)
-- To Access the Wb bus we have 7 function; only one at time can be selected. If one of
-- these functions is selected the CardSel signal is asserted (this is the responding Slave).
-- To access the Wb bus we need to decode the AM and the address lines; so as shown in
-- the block diagram the main component are two: VME_Funct_Match, VME_Am_Match.
-- ___________________________________________
-- | VME_Access_Decode.vhd |
-- | |
-- | ____________ ____________ |
-- | | | | | |
-- | | FUNCTION | | AM | |
-- | | | | | |
-- | | MATCH | | MATCH | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | | | | | |
-- | |____________| |____________| |
-- | |
-- |___________________________________________|
-- Each function has one ADER, one ADEM, one AMCAP and one XAMCAP registers.
-- The ADEM, AMCAP, XAMCAP are in the CR memory; the Master can't write these registers
-- The ADER registers are collocated in the CSR space so the VME master has to write
-- these registers properly after the initialization.
-- How to access:
-- ADER[31:0]
-- [31:8] --> compare bits (put here the base address)
-- [7:2] --> AM
-- [1] --> '0'
-- [0] --> XAM bit: '0'; '1' only for 2e access mode
-- If XAM is '1' it will be:
-- [31:10] --> compare bits (put here the base address)
-- [9:2] --> XAM
-- [1] --> '0'
-- [0] --> '1'
-- ADEM[31:0]
-- [31:8] --> mask bits (put here the base address)
-- [7:4] --> "0000"
-- [3] --> '0' --> The ADER is programmable
-- [2] --> DFS
-- [1] --> '0'
-- [0] --> EFM : '0'
-- EFM = Extra Function Mask: if '1' the next ADEM (and so the next AMCAP, XAMCAP and ADER)
-- provides the upper bit's mask for a 64 bit decoder.
-- This bit is '1' during A64 and 2e access.
-- DFS = Dynamic Function Decoder: a '1' here means this function can be used to decode
-- different access mode. Since different access mode have different AM this bit
-- influences the way of work of the AM Match component. If '1' this function has to
-- decode different address length (eg. A16 or A24 or A32) so the mask bits
-- should be all '1' !!!
-- AMCAP[63:0]
-- 6 AM lines --> 2**6 = 64 different configuration
-- This register is 64 bits wide and each bit rappresents one AM configuration.
-- If the bit is '1' it means that the corrisponding AM is supported by this function.
-- If the corresponding ADEM's DFS is 0, only the AMCAP's bits with the same address
-- width must be '1'.
-- If the corresponding ADEM's DFS is 1, one or more AMCAP's bits can be '1'
-- eg: "1011101100000000001000100000000100000000000000001011101100000000" this
-- function supports the following access mode:
-- A24_S, A24_BLT, A24_MBLT, A16_S, A32_S, A32_BLT, A32_MBLT supervisor and user access
-- XAMCAP[255:0]
-- 8 XAM lines --> 2**8 = 256 different configuration
-- This register is 256 bits wide and each bit rappresents one XAM configuration.
-- If the bit is '1' it means that the corrisponding XAM is supported
-- by this function.
-- This register is used during the decode phase if the XAM bit is asserted (1).
-- Before accessing the board the VME Master must write the ADER registers. Of course for
-- writing properly the ADER the VME Master need to know the corrisponding ADEM and check if EFM
-- or DFS bits are asserted (Read CR memory). If DFS is asserted the VME Master can read also
-- the AMCAP and XAMCAP and check the access mode supported by each function.
-- How this decode process can be used:
-- eg1. lets imagine that we want be able to access different storage device; we can assign
-- one base address and one function at each storage.
-- Now the VME Master has to write the base address of each storage in the corrisponding
-- ADER's compare bits and after this operation each function decodes the access to
-- the corresponding storage.
-- eg2. this example is relative to our application; the vme64x interface has to transfer
-- data from the VMEbus to WB bus and in this core we have only one WB master. We
-- can use the same base address for all the functions because we will access always
-- at this WB master, and use the different functions to access with different mode eg:
-- function0 --> A24_S, A24_BLT, A24_MBLT, A16_S, A32_S, A32_BLT, A32_MBLT modes
-- function1 and function2 --> A64, A64_BLT, A64_MBLT
-- function3 and function4 --> 2eVME and 2eSST modes
-- Note that if the address is 64 bits wide we need of two ADER and two ADEM to decode the
-- address so we need of two functions! (see also EFM bit definition)
-- Of course you can mix these two example and set up one system with more storage devices each
-- with his base address and assign at each storage more than one function for access it
-- with all the access modes.
-- It is also possible extend the number of the functions defining other ADEM, AMCAP, XAMCAP
-- and ADER in the User CR Space and User CSR Space (see the VME_CR_CSR_Space.vhd component)
-- respectively.
-- In the VME_Funct_Match.vhd and VME_Am_Match.vhd components you can find more detail
-- about the decode process.
--
-- To access the board both the FunctMatch(i) and AmMatch(i) must be equal to one.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
-------------------------------------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
entity VME_Access_Decode is
Port ( clk_i : in STD_LOGIC;
s_reset : in STD_LOGIC;
s_mainFSMreset : in STD_LOGIC;
s_decode : in STD_LOGIC;
ModuleEnable : in STD_LOGIC;
InitInProgress : in STD_LOGIC;
Addr : in STD_LOGIC_VECTOR (63 downto 0);
Ader0 : in STD_LOGIC_VECTOR (31 downto 0);
Ader1 : in STD_LOGIC_VECTOR (31 downto 0);
Ader2 : in STD_LOGIC_VECTOR (31 downto 0);
Ader3 : in STD_LOGIC_VECTOR (31 downto 0);
Ader4 : in STD_LOGIC_VECTOR (31 downto 0);
Ader5 : in STD_LOGIC_VECTOR (31 downto 0);
Ader6 : in STD_LOGIC_VECTOR (31 downto 0);
Ader7 : in STD_LOGIC_VECTOR (31 downto 0);
Adem0 : in STD_LOGIC_VECTOR (31 downto 0);
Adem1 : in STD_LOGIC_VECTOR (31 downto 0);
Adem2 : in STD_LOGIC_VECTOR (31 downto 0);
Adem3 : in STD_LOGIC_VECTOR (31 downto 0);
Adem4 : in STD_LOGIC_VECTOR (31 downto 0);
Adem5 : in STD_LOGIC_VECTOR (31 downto 0);
Adem6 : in STD_LOGIC_VECTOR (31 downto 0);
Adem7 : in STD_LOGIC_VECTOR (31 downto 0);
AmCap0 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap1 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap2 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap3 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap4 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap5 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap6 : in STD_LOGIC_VECTOR (63 downto 0);
AmCap7 : in STD_LOGIC_VECTOR (63 downto 0);
XAmCap0 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap1 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap2 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap3 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap4 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap5 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap6 : in STD_LOGIC_VECTOR (255 downto 0);
XAmCap7 : in STD_LOGIC_VECTOR (255 downto 0);
Am : in STD_LOGIC_VECTOR (5 downto 0);
XAm : in STD_LOGIC_VECTOR (7 downto 0);
BAR : in STD_LOGIC_VECTOR (4 downto 0);
AddrWidth : in STD_LOGIC_VECTOR (1 downto 0);
Funct_Sel : out STD_LOGIC_VECTOR (7 downto 0);
Base_Addr : out STD_LOGIC_VECTOR (63 downto 0);
Confaccess : out std_logic;
CardSel : out std_logic
);
end VME_Access_Decode;
architecture Behavioral of VME_Access_Decode is
signal s_Func_Match : std_logic_vector(7 downto 0);
signal s_Am_Match : std_logic_vector(7 downto 0);
signal s_nx_base_addr : std_logic_vector(63 downto 0);
signal s_func_sel : std_logic_vector(7 downto 0);
signal s_DFS : std_logic_vector(7 downto 0);
begin
Funct_Sel <= s_func_sel;
Inst_Funct_Match: VME_Funct_Match PORT MAP(
clk_i => clk_i,
s_reset => s_reset,
s_decode => s_decode,
s_mainFSMreset => s_mainFSMreset,
Addr => Addr,
AddrWidth => AddrWidth,
Ader0 => Ader0,
Ader1 => Ader1,
Ader2 => Ader2,
Ader3 => Ader3,
Ader4 => Ader4,
Ader5 => Ader5,
Ader6 => Ader6,
Ader7 => Ader7,
Adem0 => Adem0,
Adem1 => Adem1,
Adem2 => Adem2,
Adem3 => Adem3,
Adem4 => Adem4,
Adem5 => Adem5,
Adem6 => Adem6,
Adem7 => Adem7,
FunctMatch => s_Func_Match,
DFS_o => s_DFS,
Nx_Base_Addr => s_nx_base_addr
);
Inst_Am_Match: VME_Am_Match PORT MAP(
clk_i => clk_i,
s_reset => s_reset,
s_mainFSMreset => s_mainFSMreset,
Ader0 => Ader0,
Ader1 => Ader1,
Ader2 => Ader2,
Ader3 => Ader3,
Ader4 => Ader4,
Ader5 => Ader5,
Ader6 => Ader6,
Ader7 => Ader7,
AmCap0 => AmCap0,
AmCap1 => AmCap1,
AmCap2 => AmCap2,
AmCap3 => AmCap3,
AmCap4 => AmCap4,
AmCap5 => AmCap5,
AmCap6 => AmCap6,
AmCap7 => AmCap7,
XAmCap0 => XAmCap0,
XAmCap1 => XAmCap1,
XAmCap2 => XAmCap2,
XAmCap3 => XAmCap3,
XAmCap4 => XAmCap4,
XAmCap5 => XAmCap5,
XAmCap6 => XAmCap6,
XAmCap7 => XAmCap7,
Am => Am,
XAm => XAm,
DFS_i => s_DFS,
s_decode => s_decode,
AmMatch => s_Am_Match
);
process(clk_i)
begin
if rising_edge(clk_i) then
CardSel <= '0';
Base_Addr <= (others => '0');
if ModuleEnable = '1' and InitInProgress = '0' then
for I in 0 to 7 loop
if s_func_sel(i) = '1' then
CardSel <= '1';
Base_Addr <= s_nx_base_addr;
exit;
end if;
end loop;
end if;
end if;
end process;
s_func_sel <= s_Func_Match and s_Am_Match;
Confaccess <= '1' when unsigned(BAR) = unsigned(Addr(23 downto 19)) and
Am = c_CR_CSR and InitInProgress = '0' else '0';
------------------------------------------------------
end Behavioral;
hdl/vme64x-core/rtl/VME_Am_Match.vhd 0 → 100644
View file @ 2891a297
--_______________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________________________
-- File: VME_ Am_Match.vhd
--______________________________________________________________________________________
-- Description: this component checks if the AM match the capability of the function.
-- If it is the corrispondent AmMatch's bit is asserted. This condition is necessary but
-- not sufficient to select the function and access the board.
-- If DFS = '0' the function supports only access modes with the same address width;
-- 1 function --> only 1 address width;
-- is sufficient check the AMCAP; AmMatch(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am))).
-- If DFS = '1' the function supports access modes with different address wide so AmMatch(i)
-- is asserted only if AMCAP(i)(to_integer(unsigned(Am))) = '1' and ADER[7:2] = AM and
-- s_FUNC_AMCAP(i)(to_integer(unsigned(Am)))='1'.
-- If ADER(i)'s XAM bit is asserted than AmMatch(i) is asserted only if AM = 0x20 and if the
-- XAMCAP(i)(to_integer(unsigned(XAm))) = '1' and if DFS = '1' also ADER[9:2] must be equal
-- to XAM[7:0] lines.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
entity VME_Am_Match is
Port ( clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
Ader0 : in std_logic_vector (31 downto 0);
Ader1 : in std_logic_vector (31 downto 0);
Ader2 : in std_logic_vector (31 downto 0);
Ader3 : in std_logic_vector (31 downto 0);
Ader4 : in std_logic_vector (31 downto 0);
Ader5 : in std_logic_vector (31 downto 0);
Ader6 : in std_logic_vector (31 downto 0);
Ader7 : in std_logic_vector (31 downto 0);
AmCap0 : in std_logic_vector (63 downto 0);
AmCap1 : in std_logic_vector (63 downto 0);
AmCap2 : in std_logic_vector (63 downto 0);
AmCap3 : in std_logic_vector (63 downto 0);
AmCap4 : in std_logic_vector (63 downto 0);
AmCap5 : in std_logic_vector (63 downto 0);
AmCap6 : in std_logic_vector (63 downto 0);
AmCap7 : in std_logic_vector (63 downto 0);
XAmCap0 : in std_logic_vector (255 downto 0);
XAmCap1 : in std_logic_vector (255 downto 0);
XAmCap2 : in std_logic_vector (255 downto 0);
XAmCap3 : in std_logic_vector (255 downto 0);
XAmCap4 : in std_logic_vector (255 downto 0);
XAmCap5 : in std_logic_vector (255 downto 0);
XAmCap6 : in std_logic_vector (255 downto 0);
XAmCap7 : in std_logic_vector (255 downto 0);
Am : in std_logic_vector (5 downto 0);
XAm : in std_logic_vector (7 downto 0);
DFS_i : in std_logic_vector (7 downto 0);
s_decode : in std_logic;
AmMatch : out std_logic_vector (7 downto 0));
end VME_Am_Match;
architecture Behavioral of VME_Am_Match is
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_amcap_match : std_logic_vector(7 downto 0);
signal s_xamcap_match : std_logic_vector(7 downto 0);
signal debugAm : integer;
begin
s_FUNC_ADER(0) <= unsigned(Ader0);
s_FUNC_ADER(1) <= unsigned(Ader1);
s_FUNC_ADER(2) <= unsigned(Ader2);
s_FUNC_ADER(3) <= unsigned(Ader3);
s_FUNC_ADER(4) <= unsigned(Ader4);
s_FUNC_ADER(5) <= unsigned(Ader5);
s_FUNC_ADER(6) <= unsigned(Ader6);
s_FUNC_ADER(7) <= unsigned(Ader7);
s_FUNC_AMCAP(0) <= unsigned(AmCap0);
s_FUNC_AMCAP(1) <= unsigned(AmCap1);
s_FUNC_AMCAP(2) <= unsigned(AmCap2);
s_FUNC_AMCAP(3) <= unsigned(AmCap3);
s_FUNC_AMCAP(4) <= unsigned(AmCap4);
s_FUNC_AMCAP(5) <= unsigned(AmCap5);
s_FUNC_AMCAP(6) <= unsigned(AmCap6);
s_FUNC_AMCAP(7) <= unsigned(AmCap7);
s_FUNC_XAMCAP(0) <= unsigned(XAmCap0);
s_FUNC_XAMCAP(1) <= unsigned(XAmCap1);
s_FUNC_XAMCAP(2) <= unsigned(XAmCap2);
s_FUNC_XAMCAP(3) <= unsigned(XAmCap3);
s_FUNC_XAMCAP(4) <= unsigned(XAmCap4);
s_FUNC_XAMCAP(5) <= unsigned(XAmCap5);
s_FUNC_XAMCAP(6) <= unsigned(XAmCap6);
s_FUNC_XAMCAP(7) <= unsigned(XAmCap7);
p_AMmatch : process(clk_i)
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' or s_reset = '1' then
AmMatch <= (others => '0');
debugAm <= 0;
elsif s_decode = '1' then
for i in AmMatch'range loop
if DFS_i(i) = '1' then
if s_FUNC_ADER(i)(XAM_MODE) = '0' then
if unsigned(s_FUNC_ADER(i)(7 downto 2)) = unsigned(Am) then
AmMatch(i) <= s_amcap_match(i);
debugAm <= 1;
else
AmMatch(i) <= '0';
end if;
else
if (unsigned(XAm) = unsigned(s_FUNC_ADER(i)(9 downto 2))) then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 2;
else
AmMatch(i) <= '0';
end if;
end if;
else
if s_FUNC_ADER(i)(XAM_MODE) = '1' then
AmMatch(i) <= s_xamcap_match(i) and s_amcap_match(i);
debugAm <= 3;
else
AmMatch(i) <= s_amcap_match(i);
debugAm <= 4;
end if;
end if;
end loop;
end if;
end if;
end process;
------------------------------------------------------
-- Check if the AM is in the AMCAP register
process(s_FUNC_AMCAP, Am)
begin
s_amcap_match <= (others => '0');
for i in 0 to 7 loop
s_amcap_match(i) <= s_FUNC_AMCAP(i)(to_integer(unsigned(Am)));
end loop;
end process;
-------------------------------------------------------
-- Check if the XAM is in the XAMCAP register
process(s_FUNC_XAMCAP, XAm)
begin
s_xamcap_match <= (others => '0');
for i in 0 to 7 loop
s_xamcap_match(i) <= s_FUNC_XAMCAP(i)(to_integer(unsigned(XAm)));
end loop;
end process;
------------------------------------------------------
end Behavioral;
hdl/vme64x-core/rtl/VME_CR_CSR_Space.vhd 0 → 100644
View file @ 2891a297
--________________________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
-- File: VME_CR_CSR_Space.vhd
--________________________________________________________________________________________________
-- Description:
-- Only the third location of each 4-byte group is implemented so is possible write the CSR/CRAM
-- selecting the data transfer mode D08_Byte3, D16_Byte23, D32. If other data transfer mode are
-- selected the write operation will not be successful.
-- If the Master access the board for a reading operation with data transfer type different than
-- D08_Byte3, D16_Byte23, D32 the data that will be read is 0.
-- width = 1 byte
-- /---------------------------------/
-- _________________________________
-- | |0x7ffff
-- | |
-- | Defined and Reserved CSR |
-- | |
-- | Table 10-13 "Defined Control |
-- | Status register Assignments" |
-- | ANSI/VITA 1.1-1997 |
-- | VME64 Extensions |
-- |_________________________________|0x7fc00
-- | |0x7fbff
-- | |
-- | |
-- | CRAM |
-- | |
-- | |
-- | |
-- | |
-- |_________________________________|0x1000
-- | |0xfff
-- | |
-- | Defined and reserved CR |
-- | |
-- | Table 10-12 "Defined |
-- | Configuration ROM Assignments" |
-- | ANSI/VITA 1.1-1997 |
-- | VME64 Extensions |
-- | |
-- |_________________________________| 0x00
--
-- If the size of the register is bigger than 1 byte, (eg: ADER is 4 bytes) these bytes are
-- storaged in the BIG_ENDIAN ORDER!!
-- User CR and User CSR are not implemented.
-- In addition to the registers of the table 10-13 in the CSR space you can find:
-- _
-- IRQ_Vector --> 0x7FF5F |--> for the Interrupter
-- IRQ_level --> 0x7FF5B _|
--
-- MBLT_Endian --> 0x7FF53 --> for the swapper
-- _
-- TIME0_ns --> 0x7FF4f |
-- TIME1_ns --> 0x7FF4b |
-- TIME2_ns --> 0x7FF47 |
-- TIME3_ns --> 0x7FF43 | --> to calculate the transfer rate
-- TIME4_ns --> 0x7FF3f |
-- BYTES0 --> 0x7FF3b |
-- BYTES1 --> 0x7FF37 _|
--
-- CRAM memory Added. How to use the CRAM:
-- 1) The Master read the CRAM_OWNER Register location 0x7fff3; if 0 the CRAM is free
-- 2) The Master write his ID in the CRAM_OWNER Register location 0x7fff3
-- 3) If the Master can read his ID in the CRAM_OWNER Register it means that this master
-- is the owner of the CRAM.
-- If other Master write their ID in the CRAM_OWNER Register when it contains a non-zero
-- value, the write operation will not be successful --> this allows the first
-- Master that writes a non-zero value to acquire ownership.
-- 4) When a Master has the ownership of the CRAM the Bit Set Register's bit 2,
-- location 0x7fffb, should be setted.
-- 5) The Master can release the ownership by writing '1' in the bit 2 to the Bit Set
-- Register location 0x7fffb.
-- Other flags:
-- Module Enable --> Bit Set Register's bit 4 location 0x7fffb
-- If this bit is '0' the slave module's address decoding is not enable and
-- the Wb bus can't be accessed.
-- Error flag --> Bit Set Register's bit 3 location 0x7fffb
-- When the Slave asserts the BERR* line should asserts also this bit.
-- CRAM_OWNER flag --> Bit Set Register's bit 2 location 0x7fffb
-- The Master can clear these flags by writing '1' in the corresponding bits to the Bit Clr Register
-- location 0x7fff7.
--
-- Software reset --> Bit Set Register's bit 7 location 0x7fffb
-- This bit acts as software reset, indeed if the Master writes '1' here,
-- the module will be resetted and reinitializated.
-- The reset condition is temporary because during the initialization the default
-- configuration is uploaded again, so the Master don't need to remove the
-- module from reset mode by writing '1' in the bit 7 to the Bit Clr Register.
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
use work.VME_CR_pack.all;
use work.VME_CSR_pack.all;
entity VME_CR_CSR_Space is
Port ( -- VMEbus.vhd signals
clk_i : in std_logic;
s_reset : in std_logic;
CR_addr : in std_logic_vector (11 downto 0);
CR_data : out std_logic_vector (7 downto 0);
CRAM_addr : in std_logic_vector (18 downto 0);
CRAM_data_o : out std_logic_vector (7 downto 0);
CRAM_data_i : in std_logic_vector (7 downto 0);
CRAM_Wen : in std_logic;
en_wr_CSR : in std_logic;
CrCsrOffsetAddr : in std_logic_vector (18 downto 0);
VME_GA_oversampled : in std_logic_vector (5 downto 0);
locDataIn : in std_logic_vector (7 downto 0);
s_err_flag : in std_logic;
s_reset_flag : out std_logic;
CSRdata : out std_logic_vector(7 downto 0);
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
-- VMEbus.vhd DECODER signals
Ader0 : out std_logic_vector(31 downto 0);
Ader1 : out std_logic_vector(31 downto 0);
Ader2 : out std_logic_vector(31 downto 0);
Ader3 : out std_logic_vector(31 downto 0);
Ader4 : out std_logic_vector(31 downto 0);
Ader5 : out std_logic_vector(31 downto 0);
Ader6 : out std_logic_vector(31 downto 0);
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
MBLT_Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
-- IRQ_controller signals
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0)
);
end VME_CR_CSR_Space;
architecture Behavioral of VME_CR_CSR_Space is
signal s_CSRarray : t_CSRarray; -- Array of CSR registers
signal s_bar_written : std_logic;
signal s_CSRdata : unsigned(7 downto 0);
signal s_FUNC_ADER : t_FUNC_32b_array;
signal s_CrCsrOffsetAddr : unsigned(18 downto 0);
signal s_locDataIn : unsigned(7 downto 0);
signal s_CrCsrOffsetAderIndex : unsigned(18 downto 0);
begin
--------------------------------------------------------------------------------
-- CR
process(clk_i)
begin
if rising_edge(clk_i) then
CR_data <= c_cr_array(to_integer(unsigned(CR_addr)));
end if;
end process;
--------------------------------------------------------------------------------
-- CSR Write
s_locDataIn <= unsigned(locDataIn);
s_CrCsrOffsetAderIndex <= s_CrCsrOffsetAddr -
(c_FUNC0_ADER_3_addr(18 downto 0) srl 2) + FUNC0_ADER_3;
p_CSR_Write : process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' then
s_CSRarray(BAR) <= (others => '0');
s_bar_written <= '0';
for i in 254 downto BYTES1 loop -- Initialization of the CSR memory
s_CSRarray(i) <= c_csr_array(i);
end loop;
elsif s_bar_written = '0' then
-- initialization of BAR reg to access the CR/CSR space
s_CSRarray(BAR)(7 downto 3) <= unsigned(not VME_GA_oversampled(4 downto 0));
s_CSRarray(BAR)(2 downto 0) <= "000";
s_bar_written <= '1';
elsif (en_wr_CSR = '1') then
case to_integer(s_CrCsrOffsetAddr) is
when to_integer("00" & c_BAR_addr(18 downto 2)) =>
s_CSRarray(BAR) <= s_locDataIn(7 downto 0);
s_bar_written <= '1';
when to_integer("00" & c_BIT_SET_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
s_CSRarray(BIT_SET_CLR_REG)(i) <= s_locDataIn(i);
end loop;
when to_integer("00" & c_BIT_CLR_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
if s_locDataIn(i) = '1' and i = 2 then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '0';
s_CSRarray(CRAM_OWNER) <= x"00";
elsif s_locDataIn(i) = '1' and i = 3 then
s_reset_flag <= '1';
else
if s_locDataIn(i) = '1' then
s_CSRarray(BIT_SET_CLR_REG)(i) <= '0';
end if;
end if;
end loop;
when to_integer("00" & c_CRAM_OWNER_addr(18 downto 2)) =>
if s_CSRarray(CRAM_OWNER) = x"00" and s_locDataIn(7 downto 0) /= x"00" then
-- Write register give ownership only if register value is 0
s_CSRarray(CRAM_OWNER) <= s_locDataIn(7 downto 0);
s_CSRarray(BIT_SET_CLR_REG)(2) <= '1';
end if;
when to_integer("00" & c_USR_BIT_SET_REG_addr(18 downto 2)) =>
s_CSRarray(USR_BIT_SET_CLR_REG) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_USR_BIT_CLR_REG_addr(18 downto 2)) =>
for i in 0 to 7 loop
if s_locDataIn(i) = '1' then
s_CSRarray(USR_BIT_SET_CLR_REG)(i) <= '0';
end if;
end loop;
when to_integer("00" & c_FUNC0_ADER_3_addr(18 downto 2)) to
to_integer("00" & c_FUNC7_ADER_0_addr(18 downto 2)) =>
s_CSRarray(to_integer(s_CrCsrOffsetAderIndex)) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_IRQ_Vector_addr(18 downto 2)) =>
s_CSRarray(IRQ_Vector) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_IRQ_level_addr(18 downto 2)) =>
s_CSRarray(IRQ_level) <= s_locDataIn(7 downto 0);
when to_integer("00" & c_MBLT_Endian_addr(18 downto 2)) =>
s_CSRarray(MBLT_Endian) <= s_locDataIn(7 downto 0);
when others => null;
end case;
else
s_reset_flag <= '0';
s_CSRarray(BYTES0) <= unsigned(numBytes(7 downto 0));
s_CSRarray(BYTES1) <= resize(unsigned(numBytes(12 downto 8)),8);
s_CSRarray(TIME0_ns) <= unsigned(transfTime(7 downto 0));
s_CSRarray(TIME1_ns) <= unsigned(transfTime(15 downto 8));
s_CSRarray(TIME2_ns) <= unsigned(transfTime(23 downto 16));
s_CSRarray(TIME3_ns) <= unsigned(transfTime(31 downto 24));
s_CSRarray(TIME4_ns) <= unsigned(transfTime(39 downto 32));
end if;
end if;
end process;
------------------------------------------------------------------------------------------------------------------------------------
--CSR Read
process(s_CSRarray, s_CrCsrOffsetAddr,s_err_flag)
begin
s_CSRdata <= (others => '0');
case (s_CrCsrOffsetAddr) is
when "00" & c_BAR_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BAR);
when "00" & c_BIT_SET_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
BIT_SET_CLR_REG)(7 downto 4) & s_err_flag & s_CSRarray(BIT_SET_CLR_REG)(2 downto 0);
when "00" & c_BIT_CLR_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
BIT_SET_CLR_REG)(7 downto 4) & s_err_flag & s_CSRarray(BIT_SET_CLR_REG)(2 downto 0);
when "00" & c_CRAM_OWNER_addr(18 downto 2) => s_CSRdata <= s_CSRarray(CRAM_OWNER);
when "00" & c_USR_BIT_SET_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
USR_BIT_SET_CLR_REG);
when "00" & c_USR_BIT_CLR_REG_addr(18 downto 2) => s_CSRdata <= s_CSRarray(
USR_BIT_SET_CLR_REG);
when "00" & c_FUNC7_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_0);
when "00" & c_FUNC7_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_1);
when "00" & c_FUNC7_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_2);
when "00" & c_FUNC7_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC7_ADER_3);
when "00" & c_FUNC6_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_0);
when "00" & c_FUNC6_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_1);
when "00" & c_FUNC6_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_2);
when "00" & c_FUNC6_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC6_ADER_3);
when "00" & c_FUNC5_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_0);
when "00" & c_FUNC5_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_1);
when "00" & c_FUNC5_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_2);
when "00" & c_FUNC5_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC5_ADER_3);
when "00" & c_FUNC4_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_0);
when "00" & c_FUNC4_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_1);
when "00" & c_FUNC4_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_2);
when "00" & c_FUNC4_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC4_ADER_3);
when "00" & c_FUNC3_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_0);
when "00" & c_FUNC3_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_1);
when "00" & c_FUNC3_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC3_ADER_3);
when "00" & c_FUNC2_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_0);
when "00" & c_FUNC2_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_1);
when "00" & c_FUNC2_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_2);
when "00" & c_FUNC2_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC2_ADER_3);
when "00" & c_FUNC1_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_0);
when "00" & c_FUNC1_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_1);
when "00" & c_FUNC1_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_2);
when "00" & c_FUNC1_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC1_ADER_3);
when "00" & c_FUNC0_ADER_0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_0);
when "00" & c_FUNC0_ADER_1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_1);
when "00" & c_FUNC0_ADER_2_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_2);
when "00" & c_FUNC0_ADER_3_addr(18 downto 2) => s_CSRdata <= s_CSRarray(FUNC0_ADER_3);
when "00" & c_IRQ_Vector_addr (18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_Vector);
when "00" & c_IRQ_level_addr(18 downto 2) => s_CSRdata <= s_CSRarray(IRQ_level);
when "00" & c_MBLT_Endian_addr(18 downto 2) => s_CSRdata <= s_CSRarray(MBLT_Endian);
when "00" & c_TIME0_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME0_ns);
when "00" & c_TIME1_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME1_ns);
when "00" & c_TIME2_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME2_ns);
when "00" & c_TIME3_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME3_ns);
when "00" & c_TIME4_ns_addr(18 downto 2) => s_CSRdata <= s_CSRarray(TIME4_ns);
when "00" & c_BYTES0_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES0);
when "00" & c_BYTES1_addr(18 downto 2) => s_CSRdata <= s_CSRarray(BYTES1);
when others => s_CSRdata <= (others => '0');
end case;
end process;
INT_Level <= std_logic_vector(s_CSRarray(IRQ_level));
INT_Vector <= std_logic_vector(s_CSRarray(IRQ_Vector));
CSRdata <= std_logic_vector(s_CSRdata);
s_CrCsrOffsetAddr <= unsigned(CrCsrOffsetAddr);
GADER_1 : for i in 0 to 7 generate
GADER_2 : for h in 0 to 3 generate
s_FUNC_ADER(i)(8*(4-h)-1 downto 8*(3-h)) <= s_CSRarray(FUNC0_ADER_3+(h+i*4));
end generate GADER_2;
end generate GADER_1;
Ader0 <= std_logic_vector(s_FUNC_ADER(0));
Ader1 <= std_logic_vector(s_FUNC_ADER(1));
Ader2 <= std_logic_vector(s_FUNC_ADER(2));
Ader3 <= std_logic_vector(s_FUNC_ADER(3));
Ader4 <= std_logic_vector(s_FUNC_ADER(4));
Ader5 <= std_logic_vector(s_FUNC_ADER(5));
Ader6 <= std_logic_vector(s_FUNC_ADER(6));
Ader7 <= std_logic_vector(s_FUNC_ADER(7));
ModuleEnable <= s_CSRarray(BIT_SET_CLR_REG)(4);
MBLT_Endian_o <= std_logic_vector(s_CSRarray(MBLT_Endian)(2 downto 0));
Sw_Reset <= s_CSRarray(BIT_SET_CLR_REG)(7);
BAR_o <= std_logic_vector(s_CSRarray(BAR)(7 downto 3));
---------------------------------------------------------------------------------------------------------------
-- CRAM:
CRAM_1 : dpblockram
generic map(dl => 8, -- Length of the data word
al => 19, -- Size of the addr map (10 = 1024 words)
nw => 2**19) -- Number of words
-- 'nw' has to be coherent with 'al'
port map(clk => clk_i, -- Global Clock
we => CRAM_Wen, -- Write Enable
aw => CRAM_addr, -- Write Address
ar => (others => '0'), -- Read Address
di => CRAM_data_i, -- Data input
dw => CRAM_data_o, -- Data write, normaly open
do => open); -- Data output
end Behavioral;
hdl/vme64x-core/rtl/VME_CR_pack.vhd
View file @ 2891a297
--_______________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________________________
-- File: VME_ CR_pack.vhd
--______________________________________________________________________________________
-- Description: ROM memory (CR space)
--______________________________________________________________________________
-- Authors: Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
use work.VME_pack.all;
use work.vme64x_pack.all;
package VME_CR_pack is
constant c_amcap : std_logic_vector(63 downto 0) :=
"1111111100000000001100100000000000000000000100001111111100001011";
constant c_amcap0 : std_logic_vector(63 downto 0) :=
"1011101100000000101000100000000100000000000000001011101100000000"; -- added by Davide
-- the function 0 support the modalities: A24, A24S, A24_BLT, A24_MBLT, A16, A32, A32_BLT, A32_MBLT, A64, A64_BLT, A64_MBLT, Two Edge
constant c_amcap1 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000001011"; -- added by Davide for modalities A64, A64_BLT, A64_MBLT
constant c_amcap2 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000100000000000000000000000000000000"; -- added by Davide for modalities TWO_edge
constant c_xamcap0 : std_logic_vector(255 downto 0) :=
(others => '0'); -- added by Davide
constant c_xamcap2 : std_logic_vector(255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000060006"; -- added by Davide
constant c_amb : t_cr_array(0 to 7) :=(
c_amcap(7 downto 0), c_amcap(15 downto 8),
c_amcap(23 downto 16), c_amcap(31 downto 24),
c_amcap(39 downto 32), c_amcap(47 downto 40),
c_amcap(55 downto 48), c_amcap(63 downto 56));
constant c_amb0 : t_cr_array(0 to 7) :=( -- Added by Davide
c_amcap0(7 downto 0), c_amcap0(15 downto 8),
c_amcap0(23 downto 16), c_amcap0(31 downto 24),
c_amcap0(39 downto 32), c_amcap0(47 downto 40),
c_amcap0(55 downto 48), c_amcap0(63 downto 56));
constant c_amb1 : t_cr_array(0 to 7) :=( -- Added by Davide
c_amcap1(7 downto 0), c_amcap1(15 downto 8),
c_amcap1(23 downto 16), c_amcap1(31 downto 24),
c_amcap1(39 downto 32), c_amcap1(47 downto 40),
c_amcap1(55 downto 48), c_amcap1(63 downto 56));
constant c_amb2 : t_cr_array(0 to 7) :=( -- Added by Davide
c_amcap2(7 downto 0), c_amcap2(15 downto 8),
c_amcap2(23 downto 16), c_amcap2(31 downto 24),
c_amcap2(39 downto 32), c_amcap2(47 downto 40),
c_amcap2(55 downto 48), c_amcap2(63 downto 56));
constant c_xam0 : t_cr_array(0 to 31) :=( -- Added by Davide
c_xamcap0(7 downto 0), c_xamcap0(15 downto 8),c_xamcap0(23 downto 16), c_xamcap0(31 downto 24),
c_xamcap0(39 downto 32), c_xamcap0(47 downto 40), c_xamcap0(55 downto 48), c_xamcap0(63 downto 56),
c_xamcap0(71 downto 64), c_xamcap0(79 downto 72), c_xamcap0(87 downto 80), c_xamcap0(95 downto 88),
c_xamcap0(103 downto 96), c_xamcap0(111 downto 104), c_xamcap0(119 downto 112),c_xamcap0(127 downto 120),
c_xamcap0(135 downto 128), c_xamcap0(143 downto 136), c_xamcap0(151 downto 144), c_xamcap0(159 downto 152),
c_xamcap0(167 downto 160), c_xamcap0(175 downto 168), c_xamcap0(183 downto 176), c_xamcap0(191 downto 184),
c_xamcap0(199 downto 192), c_xamcap0(207 downto 200), c_xamcap0(215 downto 208), c_xamcap0(223 downto 216),
c_xamcap0(231 downto 224), c_xamcap0(239 downto 232), c_xamcap0(247 downto 240), c_xamcap0(255 downto 248));
constant c_xam2 : t_cr_array(0 to 31) :=( -- Added by Davide
c_xamcap2(7 downto 0), c_xamcap2(15 downto 8),c_xamcap2(23 downto 16), c_xamcap2(31 downto 24),
c_xamcap2(39 downto 32), c_xamcap2(47 downto 40), c_xamcap2(55 downto 48), c_xamcap2(63 downto 56),
c_xamcap2(71 downto 64), c_xamcap2(79 downto 72), c_xamcap2(87 downto 80), c_xamcap2(95 downto 88),
c_xamcap2(103 downto 96), c_xamcap2(111 downto 104), c_xamcap2(119 downto 112),c_xamcap2(127 downto 120),
c_xamcap2(135 downto 128), c_xamcap2(143 downto 136), c_xamcap2(151 downto 144), c_xamcap2(159 downto 152),
c_xamcap2(167 downto 160), c_xamcap2(175 downto 168), c_xamcap2(183 downto 176), c_xamcap2(191 downto 184),
c_xamcap2(199 downto 192), c_xamcap2(207 downto 200), c_xamcap2(215 downto 208), c_xamcap2(223 downto 216),
c_xamcap2(231 downto 224), c_xamcap2(239 downto 232), c_xamcap2(247 downto 240), c_xamcap2(255 downto 248));
constant c_cr_array : t_cr_array(2**12 downto 0) :=
(
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"01",
16#02# => x"00",
16#03# => x"00",
--Configuration ROM data acces width
16#04# => x"00",
--CSR data acces width
16#05# => x"81", -- it was 01...changed by Davide
--CR/CSR Space Specification ID
16#06# => x"01",
--Ascii "C"
16#07# => x"43",
--Ascii "R"
16#08# => x"52",
--Manufacturer's ID
16#09# => x"01",
16#0A# => x"02",
16#0B# => x"03",
--board id
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
16#0F# => x"03",
--Rev id
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
16#13# => x"03",
--Point to ascii null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"12",
--Offset to BEG_USER_CR --Added by Davide
16#20# => x"00",
16#21# => x"00",
16#22# => x"00",
--Offset to END_USER_CR --Added by Davide
16#23# => x"00",
16#24# => x"00",
16#25# => x"00",
--Offset to BEG_CRAM --Added by Davide
16#26# => x"00",
16#27# => x"10", --10
16#28# => x"00", --00
--Offset to END_CRAM --Added by Davide
16#29# => x"07",
16#2A# => x"fb",
16#2B# => x"ef",
--Offset to BEG_USER_CSR --Added by Davide
16#2C# => x"07",
16#2D# => x"fb",
16#2E# => x"f0", --NB: 0x7fbf0 and NOT 0x7fbf3 because is possible access with D32 mode
--Offset to END_USER_CSR --Added by Davide
16#2F# => x"07",
16#30# => x"fb",
16#31# => x"ff",
--CRAM_ACCESS_WIDTH
16#39# => x"81",
--Function data access width
16#40# => x"85", -- Fun 0 accepts MD32, D16, D08(EO) cycles
16#41# => x"85", -- Fun 1
16#42# => x"85", -- Fun 2
16#43# => x"85", -- Fun 3
16#44# => x"85", -- Fun 4
16#45# => x"85", -- Fun 5
16#46# => x"85", -- Fun 6
16#47# => x"85", -- Fun 7
--Function AM code Mask
16#48# => c_amb0(7), -- Fun 0 --modified by Davide
16#49# => c_amb0(6), -- Fun 0
16#4A# => c_amb0(5), -- Fun 0
16#4B# => c_amb0(4), -- Fun 0
16#4C# => c_amb0(3), -- Fun 0
16#4D# => c_amb0(2), -- Fun 0
16#4E# => c_amb0(1), -- Fun 0
16#4F# => c_amb0(0), -- Fun 0
16#50# => c_amb0(7), -- Fun 1 --modified by Davide
16#51# => c_amb0(6), -- Fun 1
16#52# => c_amb0(5), -- Fun 1
16#53# => c_amb0(4), -- Fun 1
16#54# => c_amb0(3), -- Fun 1
16#55# => c_amb0(2), -- Fun 1
16#56# => c_amb0(1), -- Fun 1
16#57# => c_amb0(0), -- Fun 1
16#58# => c_amb0(7), -- Fun 2 --modified by Davide
16#59# => c_amb0(6), -- Fun 2
16#5A# => c_amb0(5), -- Fun 2
16#5B# => c_amb0(4), -- Fun 2
16#5C# => c_amb0(3), -- Fun 2
16#5D# => c_amb0(2), -- Fun 2
16#5E# => c_amb0(1), -- Fun 2
16#5F# => c_amb0(0), -- Fun 2
16#60# => c_amb1(7), -- Fun 3
16#61# => c_amb1(6), -- Fun 3
16#62# => c_amb1(5), -- Fun 3
16#63# => c_amb1(4), -- Fun 3
16#64# => c_amb1(3), -- Fun 3
16#65# => c_amb1(2), -- Fun 3
16#66# => c_amb1(1), -- Fun 3
16#67# => c_amb1(0), -- Fun 3
16#68# => x"00", -- Fun 3_b --These are not used because the FUNC 3 decode the access mode: A64 --> 2 ADER, 2 ADEM
16#69# => x"00", -- Fun 3_b
16#6A# => x"00", -- Fun 3_b
16#6B# => x"00", -- Fun 3_b
16#6C# => x"00", -- Fun 3_b
16#6D# => x"00", -- Fun 3_b
16#6E# => x"00", -- Fun 3_b
16#6F# => x"00", -- Fun 3_b
16#70# => c_amb2(7), -- Fun 4
16#71# => c_amb2(6), -- Fun 4
16#72# => c_amb2(5), -- Fun 4
16#73# => c_amb2(4), -- Fun 4
16#74# => c_amb2(3), -- Fun 4
16#75# => c_amb2(2), -- Fun 4
16#76# => c_amb2(1), -- Fun 4
16#77# => c_amb2(0), -- Fun 4
16#78# => x"00", -- Fun 4_b
16#79# => x"00", -- Fun 4_b
16#7A# => x"00", -- Fun 4_b
16#7B# => x"00", -- Fun 4_b
16#7C# => x"00", -- Fun 4_b
16#7D# => x"00", -- Fun 4_b
16#7E# => x"00", -- Fun 4_b
16#7F# => x"00", -- Fun 4_b
--Xamcap
16#88# => c_xam0(31), -- Fun 0 XAMCAP MSB
16#89# => c_xam0(30),
16#8A# => c_xam0(29),
16#8B# => c_xam0(28),
16#8C# => c_xam0(27),
16#8D# => c_xam0(26),
16#8E# => c_xam0(25),
16#8F# => c_xam0(24),
16#90# => c_xam0(23),
16#91# => c_xam0(22),
16#92# => c_xam0(21),
16#93# => c_xam0(20),
16#94# => c_xam0(19),
16#95# => c_xam0(18),
16#96# => c_xam0(17),
16#97# => c_xam0(16),
16#98# => c_xam0(15),
16#99# => c_xam0(14),
16#9A# => c_xam0(13),
16#9B# => c_xam0(12),
16#9C# => c_xam0(11),
16#9D# => c_xam0(10),
16#9E# => c_xam0(9),
16#9F# => c_xam0(8),
16#A0# => c_xam0(7),
16#A1# => c_xam0(6),
16#A2# => c_xam0(5),
16#A3# => c_xam0(4),
16#A4# => c_xam0(3),
16#A5# => c_xam0(2),
16#A6# => c_xam0(1),
16#A7# => c_xam0(0),
16#A8# => c_xam0(31), -- Fun 1 XAMCAP MSB
16#A9# => c_xam0(30),
16#AA# => c_xam0(29),
16#AB# => c_xam0(28),
16#AC# => c_xam0(27),
16#AD# => c_xam0(26),
16#AE# => c_xam0(25),
16#AF# => c_xam0(24),
16#B0# => c_xam0(23),
16#B1# => c_xam0(22),
16#B2# => c_xam0(21),
16#B3# => c_xam0(20),
16#B4# => c_xam0(19),
16#B5# => c_xam0(18),
16#B6# => c_xam0(17),
16#B7# => c_xam0(16),
16#B8# => c_xam0(15),
16#B9# => c_xam0(14),
16#BA# => c_xam0(13),
16#BB# => c_xam0(12),
16#BC# => c_xam0(11),
16#BD# => c_xam0(10),
16#BE# => c_xam0(9),
16#BF# => c_xam0(8),
16#C0# => c_xam0(7),
16#C1# => c_xam0(6),
16#C2# => c_xam0(5),
16#C3# => c_xam0(4),
16#C4# => c_xam0(3),
16#C5# => c_xam0(2),
16#C6# => c_xam0(1),
16#C7# => c_xam0(0),
16#C8# => c_xam0(31), -- Fun 2 XAMCAP MSB
16#C9# => c_xam0(30),
16#CA# => c_xam0(29),
16#CB# => c_xam0(28),
16#CC# => c_xam0(27),
16#CD# => c_xam0(26),
16#CE# => c_xam0(25),
16#CF# => c_xam0(24),
16#D0# => c_xam0(23),
16#D1# => c_xam0(22),
16#D2# => c_xam0(21),
16#D3# => c_xam0(20),
16#D4# => c_xam0(19),
16#D5# => c_xam0(18),
16#D6# => c_xam0(17),
16#D7# => c_xam0(16),
16#D8# => c_xam0(15),
16#D9# => c_xam0(14),
16#DA# => c_xam0(13),
16#DB# => c_xam0(12),
16#DC# => c_xam0(11),
16#DD# => c_xam0(10),
16#DE# => c_xam0(9),
16#DF# => c_xam0(8),
16#E0# => c_xam0(7),
16#E1# => c_xam0(6),
16#E2# => c_xam0(5),
16#E3# => c_xam0(4),
16#E4# => c_xam0(3),
16#E5# => c_xam0(2),
16#E6# => c_xam0(1),
16#E7# => c_xam0(0),
16#E8# => c_xam0(31), -- Fun 3 XAMCAP MSB
16#E9# => c_xam0(30),
16#EA# => c_xam0(29),
16#EB# => c_xam0(28),
16#EC# => c_xam0(27),
16#ED# => c_xam0(26),
16#EE# => c_xam0(25),
16#EF# => c_xam0(24),
16#F0# => c_xam0(23),
16#F1# => c_xam0(22),
16#F2# => c_xam0(21),
16#F3# => c_xam0(20),
16#F4# => c_xam0(19),
16#F5# => c_xam0(18),
16#F6# => c_xam0(17),
16#F7# => c_xam0(16),
16#F8# => c_xam0(15),
16#F9# => c_xam0(14),
16#FA# => c_xam0(13),
16#FB# => c_xam0(12),
16#FC# => c_xam0(11),
16#FD# => c_xam0(10),
16#FE# => c_xam0(9),
16#FF# => c_xam0(8),
16#100# => c_xam0(7),
16#101# => c_xam0(6),
16#102# => c_xam0(5),
16#103# => c_xam0(4),
16#104# => c_xam0(3),
16#105# => c_xam0(2),
16#106# => c_xam0(1),
16#107# => c_xam0(0),
16#108# => c_xam0(31), -- Fun 3_b XAMCAP MSB
16#109# => c_xam0(30),
16#10A# => c_xam0(29),
16#10B# => c_xam0(28),
16#10C# => c_xam0(27),
16#10D# => c_xam0(26),
16#10E# => c_xam0(25),
16#10F# => c_xam0(24),
16#110# => c_xam0(23),
16#111# => c_xam0(22),
16#112# => c_xam0(21),
16#113# => c_xam0(20),
16#114# => c_xam0(19),
16#115# => c_xam0(18),
16#116# => c_xam0(17),
16#117# => c_xam0(16),
16#118# => c_xam0(15),
16#119# => c_xam0(14),
16#11A# => c_xam0(13),
16#11B# => c_xam0(12),
16#11C# => c_xam0(11),
16#11D# => c_xam0(10),
16#11E# => c_xam0(9),
16#11F# => c_xam0(8),
16#120# => c_xam0(7),
16#121# => c_xam0(6),
16#122# => c_xam0(5),
16#123# => c_xam0(4),
16#124# => c_xam0(3),
16#125# => c_xam0(2),
16#126# => c_xam0(1),
16#127# => c_xam0(0),
16#128# => c_xam2(31), -- Fun 4 XAMCAP MSB
16#129# => c_xam2(30),
16#12A# => c_xam2(29),
16#12B# => c_xam2(28),
16#12C# => c_xam2(27),
16#12D# => c_xam2(26),
16#12E# => c_xam2(25),
16#12F# => c_xam2(24),
16#130# => c_xam2(23),
16#131# => c_xam2(22),
16#132# => c_xam2(21),
16#133# => c_xam2(20),
16#134# => c_xam2(19),
16#135# => c_xam2(18),
16#136# => c_xam2(17),
16#137# => c_xam2(16),
16#138# => c_xam2(15),
16#139# => c_xam2(14),
16#13A# => c_xam2(13),
16#13B# => c_xam2(12),
16#13C# => c_xam2(11),
16#13D# => c_xam2(10),
16#13E# => c_xam2(9),
16#13F# => c_xam2(8),
16#140# => c_xam2(7),
16#141# => c_xam2(6),
16#142# => c_xam2(5),
16#143# => c_xam2(4),
16#144# => c_xam2(3),
16#145# => c_xam2(2),
16#146# => c_xam2(1),
16#147# => c_xam2(0),
16#148# => c_xam0(31), -- Fun 4_b XAMCAP MSB
16#149# => c_xam0(30),
16#14A# => c_xam0(29),
16#14B# => c_xam0(28),
16#14C# => c_xam0(27),
16#14D# => c_xam0(26),
16#14E# => c_xam0(25),
16#14F# => c_xam0(24),
16#150# => c_xam0(23),
16#151# => c_xam0(22),
16#152# => c_xam0(21),
16#153# => c_xam0(20),
16#154# => c_xam0(19),
16#155# => c_xam0(18),
16#156# => c_xam0(17),
16#157# => c_xam0(16),
16#158# => c_xam0(15),
16#159# => c_xam0(14),
16#15A# => c_xam0(13),
16#15B# => c_xam0(12),
16#15C# => c_xam0(11),
16#15D# => c_xam0(10),
16#15E# => c_xam0(9),
16#15F# => c_xam0(8),
16#160# => c_xam0(7),
16#161# => c_xam0(6),
16#162# => c_xam0(5),
16#163# => c_xam0(4),
16#164# => c_xam0(3),
16#165# => c_xam0(2),
16#166# => c_xam0(1),
16#167# => c_xam0(0),
16#168# => c_xam0(31), -- Fun 5 XAMCAP MSB
16#169# => c_xam0(30),
16#16A# => c_xam0(29),
16#16B# => c_xam0(28),
16#16C# => c_xam0(27),
16#16D# => c_xam0(26),
16#16E# => c_xam0(25),
16#16F# => c_xam0(24),
16#170# => c_xam0(23),
16#171# => c_xam0(22),
16#172# => c_xam0(21),
16#173# => c_xam0(20),
16#174# => c_xam0(19),
16#175# => c_xam0(18),
16#176# => c_xam0(17),
16#177# => c_xam0(16),
16#178# => c_xam0(15),
16#179# => c_xam0(14),
16#17A# => c_xam0(13),
16#17B# => c_xam0(12),
16#17C# => c_xam0(11),
16#17D# => c_xam0(10),
16#17E# => c_xam0(9),
16#17F# => c_xam0(8),
16#180# => c_xam0(7),
16#181# => c_xam0(6),
16#182# => c_xam0(5),
16#183# => c_xam0(4),
16#184# => c_xam0(3),
16#185# => c_xam0(2),
16#186# => c_xam0(1),
16#187# => c_xam0(0),
--...
--16#C6# => x"00", -- Fun 0 XAMCAP LSB
--16#C7# => x"01", -- Fun 0 XAMCAP LSB
--......
-- Address Decoder Mask ADEM
16#188# => x"ff", -- Fun 0
16#189# => x"ff", -- Fun 0
16#18A# => x"f8", -- Fun 0
16#18B# => x"00", -- Fun 0
16#18c# => x"00", -- Fun 1
16#18d# => x"ff", -- Fun 1
16#18e# => x"00", -- Fun 1
16#18f# => x"00", -- Fun 1
16#190# => x"ff", -- Fun 2
16#191# => x"00", -- Fun 2
16#192# => x"00", -- Fun 2
16#193# => x"00", -- Fun 2
16#194# => x"00", -- Fun 3
16#195# => x"00", -- Fun 3
16#196# => x"00", -- Fun 3
16#197# => x"01", -- Fun 3
16#198# => x"ff", -- Fun 4 (used for decoding FUNC3)
16#199# => x"ff", -- Fun 4 (used for decoding FUNC3)
16#19a# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19b# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19c# => x"ff", -- Fun 5
16#19d# => x"00", -- Fun 5
16#19e# => x"00", -- Fun 5
16#19f# => x"01", -- Fun 5
16#1a0# => x"00", -- Fun 6
16#1a1# => x"00", -- Fun 6
16#1a2# => x"00", -- Fun 6
16#1a3# => x"00", -- Fun 6
others => (others => '0'));
end VME_CR_pack;
constant c_amcap : std_logic_vector(63 downto 0) :=
"1111111100000000001100100000000000000000000100001111111100001011";
constant c_amcap0 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000001011101100000000"; --A32
-- "1011101100000000001000100000000100000000000000001011101100000000";
constant c_amcapMBLT : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000100000000";
constant c_amcap1 : std_logic_vector(63 downto 0) :=
"1011101100000000000000000000000000000000000000000000000000001011"; --A24
constant c_amcap2 : std_logic_vector(63 downto 0) :=
"0000000000000000001000100000000000000000000000000000000000000000"; --A16
constant c_amcapA64 : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000000000000000000000000000000001011"; --for modalities A64, A64_BLT, A64_MBLT
constant c_amcap2e : std_logic_vector(63 downto 0) :=
"0000000000000000000000000000000100000000000000000000000000000000"; -- for modalities TWO_edge
constant c_xamcap0 : std_logic_vector(255 downto 0) :=
(others => '0');
constant c_xamcap2 : std_logic_vector(255 downto 0) :=
x"0000000000000000000000000000000000000000000000000000000000060006";
constant c_amb : t_cr_array(0 to 7) :=(
c_amcap(7 downto 0), c_amcap(15 downto 8),
c_amcap(23 downto 16), c_amcap(31 downto 24),
c_amcap(39 downto 32), c_amcap(47 downto 40),
c_amcap(55 downto 48), c_amcap(63 downto 56));
constant c_amb0 : t_cr_array(0 to 7) :=(
c_amcap0(7 downto 0), c_amcap0(15 downto 8),
c_amcap0(23 downto 16), c_amcap0(31 downto 24),
c_amcap0(39 downto 32), c_amcap0(47 downto 40),
c_amcap0(55 downto 48), c_amcap0(63 downto 56));
constant c_amb1 : t_cr_array(0 to 7) :=(
c_amcap1(7 downto 0), c_amcap1(15 downto 8),
c_amcap1(23 downto 16), c_amcap1(31 downto 24),
c_amcap1(39 downto 32), c_amcap1(47 downto 40),
c_amcap1(55 downto 48), c_amcap1(63 downto 56));
constant c_amb2 : t_cr_array(0 to 7) :=(
c_amcap2(7 downto 0), c_amcap2(15 downto 8),
c_amcap2(23 downto 16), c_amcap2(31 downto 24),
c_amcap2(39 downto 32),c_amcap2(47 downto 40),
c_amcap2(55 downto 48), c_amcap2(63 downto 56));
constant c_amb64 : t_cr_array(0 to 7) :=(
c_amcapA64(7 downto 0), c_amcapA64(15 downto 8),
c_amcapA64(23 downto 16), c_amcapA64(31 downto 24),
c_amcapA64(39 downto 32),c_amcapA64(47 downto 40),
c_amcapA64(55 downto 48), c_amcapA64(63 downto 56));
constant c_xam0 : t_cr_array(0 to 31) :=(
c_xamcap0(7 downto 0), c_xamcap0(15 downto 8),c_xamcap0(23 downto 16), c_xamcap0(31 downto 24),
c_xamcap0(39 downto 32), c_xamcap0(47 downto 40), c_xamcap0(55 downto 48),
c_xamcap0(63 downto 56), c_xamcap0(71 downto 64), c_xamcap0(79 downto 72), c_xamcap0(87 downto 80),
c_xamcap0(95 downto 88), c_xamcap0(103 downto 96), c_xamcap0(111 downto 104),
c_xamcap0(119 downto 112),c_xamcap0(127 downto 120),c_xamcap0(135 downto 128),
c_xamcap0(143 downto 136), c_xamcap0(151 downto 144), c_xamcap0(159 downto 152),
c_xamcap0(167 downto 160), c_xamcap0(175 downto 168), c_xamcap0(183 downto 176),
c_xamcap0(191 downto 184), c_xamcap0(199 downto 192), c_xamcap0(207 downto 200),
c_xamcap0(215 downto 208), c_xamcap0(223 downto 216), c_xamcap0(231 downto 224),
c_xamcap0(239 downto 232), c_xamcap0(247 downto 240), c_xamcap0(255 downto 248));
constant c_xam2 : t_cr_array(0 to 31) :=(
c_xamcap2(7 downto 0), c_xamcap2(15 downto 8),c_xamcap2(23 downto 16), c_xamcap2(31 downto 24),
c_xamcap2(39 downto 32), c_xamcap2(47 downto 40), c_xamcap2(55 downto 48), c_xamcap2(63 downto 56),
c_xamcap2(71 downto 64), c_xamcap2(79 downto 72), c_xamcap2(87 downto 80), c_xamcap2(95 downto 88),
c_xamcap2(103 downto 96), c_xamcap2(111 downto 104), c_xamcap2(119 downto 112),
c_xamcap2(127 downto 120), c_xamcap2(135 downto 128), c_xamcap2(143 downto 136),
c_xamcap2(151 downto 144), c_xamcap2(159 downto 152), c_xamcap2(167 downto 160),
c_xamcap2(175 downto 168), c_xamcap2(183 downto 176), c_xamcap2(191 downto 184),
c_xamcap2(199 downto 192), c_xamcap2(207 downto 200), c_xamcap2(215 downto 208),
c_xamcap2(223 downto 216), c_xamcap2(231 downto 224), c_xamcap2(239 downto 232),
c_xamcap2(247 downto 240), c_xamcap2(255 downto 248));
constant c_cr_array : t_cr_array(2**12 downto 0) :=
(
16#00# => (others => '0'),
-- Length of ROM
16#01# => x"01",
16#02# => x"00",
16#03# => x"00",
--Configuration ROM data acces width
16#04# => x"00",
--CSR data acces width
16#05# => x"81", -- it was 01...changed by Davide
--CR/CSR Space Specification ID
16#06# => x"01",
--Ascii "C"
16#07# => x"43",
--Ascii "R"
16#08# => x"52",
--Manufacturer's ID
16#09# => x"01",
16#0A# => x"02",
16#0B# => x"03",
--board id
16#0C# => x"03",
16#0D# => x"04",
16#0E# => x"04",
16#0F# => x"03",
--Rev id
16#10# => x"03",
16#11# => x"04",
16#12# => x"04",
16#13# => x"03",
--Point to ascii null terminatied
16#14# => x"00",
16#15# => x"00",
16#16# => x"00",
--Program Id code
16#1F# => x"01",
--Offset to BEG_USER_CR --Added by Davide
16#20# => x"00",
16#21# => x"00",
16#22# => x"00",
--Offset to END_USER_CR --Added by Davide
16#23# => x"00",
16#24# => x"00",
16#25# => x"00",
--Offset to BEG_CRAM --Added by Davide
16#26# => x"00",
16#27# => x"10", --10
16#28# => x"00", --00
--Offset to END_CRAM --Added by Davide
16#29# => x"07",
16#2A# => x"fb",
16#2B# => x"ff",
--Offset to BEG_USER_CSR --Added by Davide
16#2C# => x"00",
16#2D# => x"00",
16#2E# => x"00", --NB: 0x7fbf0 and NOT 0x7fbf3 because is possible access with D32 mode
--Offset to END_USER_CSR --Added by Davide
16#2F# => x"00",
16#30# => x"00",
16#31# => x"00",
--CRAM_ACCESS_WIDTH
16#39# => x"81",
--Function data access width
16#40# => x"85", -- Fun 0 accepts MD32, D16, D08(EO) cycles
16#41# => x"85", -- Fun 1
16#42# => x"85", -- Fun 2
16#43# => x"85", -- Fun 3
16#44# => x"85", -- Fun 4
16#45# => x"85", -- Fun 5
16#46# => x"85", -- Fun 6
16#47# => x"85", -- Fun 7
--Function AM code Mask
16#48# => c_amb0(7), -- Fun 0
16#49# => c_amb0(6), -- Fun 0
16#4A# => c_amb0(5), -- Fun 0
16#4B# => c_amb0(4), -- Fun 0
16#4C# => c_amb0(3), -- Fun 0
16#4D# => c_amb0(2), -- Fun 0
16#4E# => c_amb0(1), -- Fun 0
16#4F# => c_amb0(0), -- Fun 0
16#50# => c_amb1(7), -- Fun 1
16#51# => c_amb1(6), -- Fun 1
16#52# => c_amb1(5), -- Fun 1
16#53# => c_amb1(4), -- Fun 1
16#54# => c_amb1(3), -- Fun 1
16#55# => c_amb1(2), -- Fun 1
16#56# => c_amb1(1), -- Fun 1
16#57# => c_amb1(0), -- Fun 1
16#58# => c_amb2(7), -- Fun 2
16#59# => c_amb2(6), -- Fun 2
16#5A# => c_amb2(5), -- Fun 2
16#5B# => c_amb2(4), -- Fun 2
16#5C# => c_amb2(3), -- Fun 2
16#5D# => c_amb2(2), -- Fun 2
16#5E# => c_amb2(1), -- Fun 2
16#5F# => c_amb2(0), -- Fun 2
16#60# => c_amb64(7), -- Fun 3
16#61# => c_amb64(6), -- Fun 3
16#62# => c_amb64(5), -- Fun 3
16#63# => c_amb64(4), -- Fun 3
16#64# => c_amb64(3), -- Fun 3
16#65# => c_amb64(2), -- Fun 3
16#66# => c_amb64(1), -- Fun 3
16#67# => c_amb64(0), -- Fun 3
16#68# => x"00", -- Fun 3_b --These are not used because the FUNC 3 decode the access mode: A64 --> 2 ADER, 2 ADEM
16#69# => x"00", -- Fun 3_b
16#6A# => x"00", -- Fun 3_b
16#6B# => x"00", -- Fun 3_b
16#6C# => x"00", -- Fun 3_b
16#6D# => x"00", -- Fun 3_b
16#6E# => x"00", -- Fun 3_b
16#6F# => x"00", -- Fun 3_b
16#70# => c_amb2(7), -- Fun 4
16#71# => c_amb2(6), -- Fun 4
16#72# => c_amb2(5), -- Fun 4
16#73# => c_amb2(4), -- Fun 4
16#74# => c_amb2(3), -- Fun 4
16#75# => c_amb2(2), -- Fun 4
16#76# => c_amb2(1), -- Fun 4
16#77# => c_amb2(0), -- Fun 4
16#78# => x"00", -- Fun 4_b
16#79# => x"00", -- Fun 4_b
16#7A# => x"00", -- Fun 4_b
16#7B# => x"00", -- Fun 4_b
16#7C# => x"00", -- Fun 4_b
16#7D# => x"00", -- Fun 4_b
16#7E# => x"00", -- Fun 4_b
16#7F# => x"00", -- Fun 4_b
--Xamcap
16#88# => c_xam0(31), -- Fun 0 XAMCAP MSB
16#89# => c_xam0(30),
16#8A# => c_xam0(29),
16#8B# => c_xam0(28),
16#8C# => c_xam0(27),
16#8D# => c_xam0(26),
16#8E# => c_xam0(25),
16#8F# => c_xam0(24),
16#90# => c_xam0(23),
16#91# => c_xam0(22),
16#92# => c_xam0(21),
16#93# => c_xam0(20),
16#94# => c_xam0(19),
16#95# => c_xam0(18),
16#96# => c_xam0(17),
16#97# => c_xam0(16),
16#98# => c_xam0(15),
16#99# => c_xam0(14),
16#9A# => c_xam0(13),
16#9B# => c_xam0(12),
16#9C# => c_xam0(11),
16#9D# => c_xam0(10),
16#9E# => c_xam0(9),
16#9F# => c_xam0(8),
16#A0# => c_xam0(7),
16#A1# => c_xam0(6),
16#A2# => c_xam0(5),
16#A3# => c_xam0(4),
16#A4# => c_xam0(3),
16#A5# => c_xam0(2),
16#A6# => c_xam0(1),
16#A7# => c_xam0(0),
16#A8# => c_xam0(31), -- Fun 1 XAMCAP MSB
16#A9# => c_xam0(30),
16#AA# => c_xam0(29),
16#AB# => c_xam0(28),
16#AC# => c_xam0(27),
16#AD# => c_xam0(26),
16#AE# => c_xam0(25),
16#AF# => c_xam0(24),
16#B0# => c_xam0(23),
16#B1# => c_xam0(22),
16#B2# => c_xam0(21),
16#B3# => c_xam0(20),
16#B4# => c_xam0(19),
16#B5# => c_xam0(18),
16#B6# => c_xam0(17),
16#B7# => c_xam0(16),
16#B8# => c_xam0(15),
16#B9# => c_xam0(14),
16#BA# => c_xam0(13),
16#BB# => c_xam0(12),
16#BC# => c_xam0(11),
16#BD# => c_xam0(10),
16#BE# => c_xam0(9),
16#BF# => c_xam0(8),
16#C0# => c_xam0(7),
16#C1# => c_xam0(6),
16#C2# => c_xam0(5),
16#C3# => c_xam0(4),
16#C4# => c_xam0(3),
16#C5# => c_xam0(2),
16#C6# => c_xam0(1),
16#C7# => c_xam0(0),
16#C8# => c_xam0(31), -- Fun 2 XAMCAP MSB
16#C9# => c_xam0(30),
16#CA# => c_xam0(29),
16#CB# => c_xam0(28),
16#CC# => c_xam0(27),
16#CD# => c_xam0(26),
16#CE# => c_xam0(25),
16#CF# => c_xam0(24),
16#D0# => c_xam0(23),
16#D1# => c_xam0(22),
16#D2# => c_xam0(21),
16#D3# => c_xam0(20),
16#D4# => c_xam0(19),
16#D5# => c_xam0(18),
16#D6# => c_xam0(17),
16#D7# => c_xam0(16),
16#D8# => c_xam0(15),
16#D9# => c_xam0(14),
16#DA# => c_xam0(13),
16#DB# => c_xam0(12),
16#DC# => c_xam0(11),
16#DD# => c_xam0(10),
16#DE# => c_xam0(9),
16#DF# => c_xam0(8),
16#E0# => c_xam0(7),
16#E1# => c_xam0(6),
16#E2# => c_xam0(5),
16#E3# => c_xam0(4),
16#E4# => c_xam0(3),
16#E5# => c_xam0(2),
16#E6# => c_xam0(1),
16#E7# => c_xam0(0),
16#E8# => c_xam0(31), -- Fun 3 XAMCAP MSB
16#E9# => c_xam0(30),
16#EA# => c_xam0(29),
16#EB# => c_xam0(28),
16#EC# => c_xam0(27),
16#ED# => c_xam0(26),
16#EE# => c_xam0(25),
16#EF# => c_xam0(24),
16#F0# => c_xam0(23),
16#F1# => c_xam0(22),
16#F2# => c_xam0(21),
16#F3# => c_xam0(20),
16#F4# => c_xam0(19),
16#F5# => c_xam0(18),
16#F6# => c_xam0(17),
16#F7# => c_xam0(16),
16#F8# => c_xam0(15),
16#F9# => c_xam0(14),
16#FA# => c_xam0(13),
16#FB# => c_xam0(12),
16#FC# => c_xam0(11),
16#FD# => c_xam0(10),
16#FE# => c_xam0(9),
16#FF# => c_xam0(8),
16#100# => c_xam0(7),
16#101# => c_xam0(6),
16#102# => c_xam0(5),
16#103# => c_xam0(4),
16#104# => c_xam0(3),
16#105# => c_xam0(2),
16#106# => c_xam0(1),
16#107# => c_xam0(0),
16#108# => c_xam0(31), -- Fun 3_b XAMCAP MSB
16#109# => c_xam0(30),
16#10A# => c_xam0(29),
16#10B# => c_xam0(28),
16#10C# => c_xam0(27),
16#10D# => c_xam0(26),
16#10E# => c_xam0(25),
16#10F# => c_xam0(24),
16#110# => c_xam0(23),
16#111# => c_xam0(22),
16#112# => c_xam0(21),
16#113# => c_xam0(20),
16#114# => c_xam0(19),
16#115# => c_xam0(18),
16#116# => c_xam0(17),
16#117# => c_xam0(16),
16#118# => c_xam0(15),
16#119# => c_xam0(14),
16#11A# => c_xam0(13),
16#11B# => c_xam0(12),
16#11C# => c_xam0(11),
16#11D# => c_xam0(10),
16#11E# => c_xam0(9),
16#11F# => c_xam0(8),
16#120# => c_xam0(7),
16#121# => c_xam0(6),
16#122# => c_xam0(5),
16#123# => c_xam0(4),
16#124# => c_xam0(3),
16#125# => c_xam0(2),
16#126# => c_xam0(1),
16#127# => c_xam0(0),
16#128# => c_xam2(31), -- Fun 4 XAMCAP MSB
16#129# => c_xam2(30),
16#12A# => c_xam2(29),
16#12B# => c_xam2(28),
16#12C# => c_xam2(27),
16#12D# => c_xam2(26),
16#12E# => c_xam2(25),
16#12F# => c_xam2(24),
16#130# => c_xam2(23),
16#131# => c_xam2(22),
16#132# => c_xam2(21),
16#133# => c_xam2(20),
16#134# => c_xam2(19),
16#135# => c_xam2(18),
16#136# => c_xam2(17),
16#137# => c_xam2(16),
16#138# => c_xam2(15),
16#139# => c_xam2(14),
16#13A# => c_xam2(13),
16#13B# => c_xam2(12),
16#13C# => c_xam2(11),
16#13D# => c_xam2(10),
16#13E# => c_xam2(9),
16#13F# => c_xam2(8),
16#140# => c_xam2(7),
16#141# => c_xam2(6),
16#142# => c_xam2(5),
16#143# => c_xam2(4),
16#144# => c_xam2(3),
16#145# => c_xam2(2),
16#146# => c_xam2(1),
16#147# => c_xam2(0),
16#148# => c_xam0(31), -- Fun 4_b XAMCAP MSB
16#149# => c_xam0(30),
16#14A# => c_xam0(29),
16#14B# => c_xam0(28),
16#14C# => c_xam0(27),
16#14D# => c_xam0(26),
16#14E# => c_xam0(25),
16#14F# => c_xam0(24),
16#150# => c_xam0(23),
16#151# => c_xam0(22),
16#152# => c_xam0(21),
16#153# => c_xam0(20),
16#154# => c_xam0(19),
16#155# => c_xam0(18),
16#156# => c_xam0(17),
16#157# => c_xam0(16),
16#158# => c_xam0(15),
16#159# => c_xam0(14),
16#15A# => c_xam0(13),
16#15B# => c_xam0(12),
16#15C# => c_xam0(11),
16#15D# => c_xam0(10),
16#15E# => c_xam0(9),
16#15F# => c_xam0(8),
16#160# => c_xam0(7),
16#161# => c_xam0(6),
16#162# => c_xam0(5),
16#163# => c_xam0(4),
16#164# => c_xam0(3),
16#165# => c_xam0(2),
16#166# => c_xam0(1),
16#167# => c_xam0(0),
16#168# => c_xam0(31), -- Fun 5 XAMCAP MSB
16#169# => c_xam0(30),
16#16A# => c_xam0(29),
16#16B# => c_xam0(28),
16#16C# => c_xam0(27),
16#16D# => c_xam0(26),
16#16E# => c_xam0(25),
16#16F# => c_xam0(24),
16#170# => c_xam0(23),
16#171# => c_xam0(22),
16#172# => c_xam0(21),
16#173# => c_xam0(20),
16#174# => c_xam0(19),
16#175# => c_xam0(18),
16#176# => c_xam0(17),
16#177# => c_xam0(16),
16#178# => c_xam0(15),
16#179# => c_xam0(14),
16#17A# => c_xam0(13),
16#17B# => c_xam0(12),
16#17C# => c_xam0(11),
16#17D# => c_xam0(10),
16#17E# => c_xam0(9),
16#17F# => c_xam0(8),
16#180# => c_xam0(7),
16#181# => c_xam0(6),
16#182# => c_xam0(5),
16#183# => c_xam0(4),
16#184# => c_xam0(3),
16#185# => c_xam0(2),
16#186# => c_xam0(1),
16#187# => c_xam0(0),
--...
--16#C6# => x"00", -- Fun 0 XAMCAP LSB
--16#C7# => x"01", -- Fun 0 XAMCAP LSB
--......
-- Address Decoder Mask ADEM
16#188# => x"f0", -- Fun 0
16#189# => x"00", -- Fun 0
16#18A# => x"00", -- Fun 0
16#18B# => x"00", -- Fun 0 --DFS = '0'
16#18c# => x"00", -- Fun 1
16#18d# => x"f0", -- Fun 1
16#18e# => x"00", -- Fun 1
16#18f# => x"00", -- Fun 1 --DFS = '0'
16#190# => x"00", -- Fun 2
16#191# => x"00", -- Fun 2
16#192# => x"f0", -- Fun 2
16#193# => x"00", -- Fun 2 --DFS = '0'
16#194# => x"00", -- Fun 3
16#195# => x"00", -- Fun 3
16#196# => x"00", -- Fun 3
16#197# => x"01", -- Fun 3
16#198# => x"ff", -- Fun 4 (used for decoding FUNC3)
16#199# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19a# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19b# => x"00", -- Fun 4 (used for decoding FUNC3)
16#19c# => x"ff", -- Fun 5
16#19d# => x"00", -- Fun 5
16#19e# => x"00", -- Fun 5
16#19f# => x"01", -- Fun 5
16#1a0# => x"00", -- Fun 6
16#1a1# => x"00", -- Fun 6
16#1a2# => x"00", -- Fun 6
16#1a3# => x"00", -- Fun 6
others => (others => '0'));
end VME_CR_pack;
......
hdl/vme64x-core/rtl/VME_CSR_pack.vhd
View file @ 2891a297
--________________________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
-- File: VME_CSR_pack.vhd
--________________________________________________________________________________________________
-- Description: This file defines the default configuration of the CSR space after power-up or software reset.
--______________________________________________________________________________
-- Authors: Erik Van der Bij (Erik.Van.der.Bij@cern.ch)
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
--type is array(BAR downto IRQ_level) of unsigned(7 downto 0);
use IEEE.numeric_std.all;
use work.VME_pack.all;
use work.vme64x_pack.all;
package VME_CSR_pack is
constant c_csr_array : t_CSRarray :=
constant c_csr_array : t_CSRarray :=
(
BAR => x"00", --CR/CSR BAR
BIT_SET_CLR_REG => x"10", --Bit set register -- 0x10=module enable
USR_BIT_SET_CLR_REG => x"00", --Bit clear register
CRAM_OWNER => x"00", --CRAM_OWNER
FUNC0_ADER_0 =>x"09", -- it was x"45"
FUNC0_ADER_1 =>x"00",
FUNC0_ADER_2 =>x"00",
FUNC0_ADER_3 =>x"c0", -- it was x"80"
FUNC1_ADER_0 =>x"39",
FUNC1_ADER_1 =>x"00",
FUNC0_ADER_0 =>x"00", --A32_S "24"
FUNC0_ADER_1 =>x"00", -- "00"
FUNC0_ADER_2 =>x"00", -- "00"
FUNC0_ADER_3 =>x"00", -- "c0"
FUNC1_ADER_2 =>x"c0", -- it was x"34"
FUNC1_ADER_3 =>x"00", -- it was x"12"
FUNC1_ADER_0 =>x"00", --A24_S "e4"
FUNC1_ADER_1 =>x"00", -- "00"
FUNC1_ADER_2 =>x"00", -- "c0"
FUNC1_ADER_3 =>x"00", -- "00"
FUNC2_ADER_0 =>x"08", -- it was x"e4"
FUNC2_ADER_1 =>x"00",
FUNC2_ADER_2 =>x"00", -- it was x"80"
FUNC2_ADER_3 =>x"c0",
FUNC2_ADER_0 =>x"00", --A16_S "a4"
FUNC2_ADER_1 =>x"00", -- "c0"
FUNC2_ADER_2 =>x"00", -- "00"
FUNC2_ADER_3 =>x"00", -- "00"
FUNC3_ADER_0 =>x"04", -- A64_S
FUNC3_ADER_0 =>x"00", --A64_S "04"
FUNC3_ADER_1 =>x"00",
FUNC3_ADER_2 =>x"00",
FUNC3_ADER_3 =>x"00",
......@@ -38,60 +62,22 @@ FUNC3_ADER_3 =>x"00",
FUNC4_ADER_0 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_1 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_2 =>x"00", --used for decoding the FUNC3
FUNC4_ADER_3 =>x"c0", --used for decoding the FUNC3
FUNC4_ADER_3 =>x"00", --used for decoding the FUNC3 "c0"
FUNC5_ADER_0 =>x"01",
FUNC5_ADER_0 =>x"00",
FUNC5_ADER_1 =>x"00",
FUNC5_ADER_2 =>x"00",
FUNC5_ADER_3 =>x"c0",
FUNC5_ADER_3 =>x"00",
FUNC6_ADER_0 =>x"00",
FUNC6_ADER_1 =>x"00",
FUNC6_ADER_2 =>x"00",
FUNC6_ADER_3 =>x"00",
IRQ_Vector =>x"86",
IRQ_Vector =>x"00", --"00" because each Slot has a different IRQ Vector
-- and the VME Master should set this value
IRQ_level =>x"02",
others => (others => '0'));
-- constant BAR : integer := 255;
-- constant BIT_SET_CLR_REG : integer := 254;
-- constant USR_BIT_SET_CLR_REG : integer := 253;
-- constant CRAM_OWNER : integer := 252;
--
-- constant FUNC7_ADER_0 : integer := 251;
-- constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
-- constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
-- constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
-- constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
-- constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
-- constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
-- constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
-- constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
-- constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
-- constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
-- constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
-- constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
-- constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
-- constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
-- constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
-- constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
-- constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
-- constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
-- constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
-- constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
-- constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
-- constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
-- constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
-- constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
-- constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
-- constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
-- constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
-- constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
-- constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
-- constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
-- constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
end VME_CSR_pack;
......
hdl/vme64x-core/rtl/VME_DpBlockRam.vhd 0 → 100755
View file @ 2891a297
--==============================================================--
--Design Units : CTX1 Control and Statistics
--Size:
--Speed:
--File Name: MebRam.vhd
--
--Purpose: The dpblockram implements a synthetisable model of a
-- dual port RAM.
-- There are an input data and addr ports to allow the
-- writing at the reception of a GMT frame.
-- The output data and addr ports allow a simultanous
-- reading of the circular buffer by the user, at the
-- same time than it is beeing written.
--
-- The frame and the millisecond stamp are stored in the
-- same ram word. It is the task of the MEB block to
-- separate the frame data from the millisecond stamp data.
--
--Limitations:
--
--Errors:
--
--Libraries:
--
--Dependancies: It instantiates a synthetisable model of a DPRAM
-- See MebRam.vhd
--
--Author: Pablo Antonio Alvarez Sanchez
-- European Organisation for Nuclear Research
-- SL SPS/LHC -- Control -- Timing Division
-- CERN, Geneva, Switzerland, CH-1211
-- Building 864 Room 1 - A24
--
--Simulator: ModelSim XE 5.5e_p1
--==============================================================--
--Revision List
--Version Author Date Changes
--
--1.0 PAAS 30.09.2002 Added comments, tested with the
-- rest of the design
--==============================================================--
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity dpblockram is
generic (dl : integer := 8; -- Length of the data word
al : integer := 19; -- Size of the addr map (10 = 1024 words)
nw : integer := 2**19); -- Number of words
-- 'nw' has to be coherent with 'al'
port (clk : in std_logic; -- Global Clock
we : in std_logic; -- Write Enable
aw : in std_logic_vector(al - 1 downto 0); -- Write Address
ar : in std_logic_vector(al - 1 downto 0); -- Read Address
di : in std_logic_vector(dl - 1 downto 0); -- Data input
dw : out std_logic_vector(dl - 1 downto 0); -- Data write, normaly open
do : out std_logic_vector(dl - 1 downto 0)); -- Data output
end dpblockram;
-- DATA OUTPUT NOT REGISTERED!
--library synplify;
--use synplify.attributes.all;
architecture syn of dpblockram is
type ram_type is array (nw - 1 downto 0) of std_logic_vector (dl - 1 downto 0);
signal CRAM : ram_type;
signal read_a : std_logic_vector(al - 1 downto 0);
signal read_ar : std_logic_vector(al - 1 downto 0);
--attribute syn_ramstyle of RAM : signal is "block_ram";
begin
process (clk)
begin
if (clk'event and clk = '1') then
if (we = '1') then
CRAM(conv_integer(aw)) <= di;
end if;
read_a <= aw;
read_ar <= ar;
end if;
end process;
dw <= CRAM(conv_integer(read_a));
do <= CRAM(conv_integer(read_ar)); -- Notice that the Data Output is not registered
end syn;
hdl/vme64x-core/rtl/VME_Funct_Match.vhd 0 → 100644
View file @ 2891a297
--_________________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--_________________________________________________________________________________________
-- File: VME_Funct_Match.vhd
--_________________________________________________________________________________________
-- Description: this component compares the Address with the ADER using the mask bits and
-- if the base address match asserts the corrisponding bit of the FunctMatch signal and
-- latches the base address that will be subtract at the Address before access the WB bus.
-- FunctMatch /= 0 is necessary but not sufficient to select one function and access the board,
-- indeed also the AM has to be checked (VME_AM_Match.vhd component).
-- For better understanding how this component works here one example:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- ADEMi = 0xffffff04 --> DFS = '1' --> all the mask bits are '1'!!
-- The Master want access at the location 0x08: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00000 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- Now with the same ADEMi the master access with A16 mode:
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- The Master want access at the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[15:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0x0000c0 0x0000c0
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- DFS = '1' --> 1 function --> multiple access mode
-- The Master access with different mode only changing the ADER registers if the
-- DFS bit is asserted but:
-- It is easy to see that if DFS = '1' we can only address 256 bytes, indeed eg:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00040 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- The Master can't access!!
-- Without DFS asserted:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master write the ADERi = 0xc0000024
-- ADEMi = 0xff000000 --> DFS = '0'
-- The Master want access at the location 0x4008: Address= 0xc0004008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEM[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0xc00000 0xc00000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- The Master can access!
-- base address = 0xc0
-- access mode: A16_S --> AM = 0x29
-- The Master write the ADERi = 0x0000c0a4
-- ADEMi = 0xff000000 --> DFS = '0' -- The Master can't change the CR space!!
-- The Master want access at the location 0x08: Address= 0x0000c008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected:
-- ADEM[15:8] = 0 --> FunctMatch(i) <= '0'
-- The Master can't access! this mask is not compatible with A16
--
-- DFS = '0' --> 1 function --> only the access modes with the same
-- address width !!
-- Is it possible initialize all the ADER to 0 ?
-- Yes, it is. Indeed now suppose that we are in this situation:
-- ADERi = 0x00000000
-- ADEMi = 0x0000ff00 --> DFS = '0'
-- A VME Master access to VMEbus for accessing at another board:
-- base address = 0xc0
-- access mode: A32_S --> AM = 0x09
-- The Master want access at the location 0x0008: Address= 0xc0000008
-- For i = 0 to 7 check:
-- Check if the ADEMi is compatible with the AM selected: ADEMi[31:8] /= 0
-- Address[31:8] and ADEMi[31:8] ADERi[31:8] and ADEMi[31:8]
-- | |
-- 0x000000 0x000000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
-- FunctMatch(i) is asserted but our Slave will not be the responding Slave, indeed
-- the AmMatch(i) is zero becouse the Master is accessing with A32_S and if DFS is 0
-- the AMCAPi register has only the A16 or A16_SUP bits asserted!
-- If DFS is '1' AmMatch(i) is zero becouse ADER[7:2] is 0 (see VME_Am_Match.vhd) and
-- also FunctMatch(i) is 0 because ADEMi should has all the mask bits '1'.
--
--Follow an example about A64 access mode:
-- base address = 0xc0
-- access mode: A64_S --> AM = 0x01
-- ADEM(i) = 0x00000001 --> EFM = '1' and DFS = '0'
-- ADEM(i+1) = 0xff000000
-- ADEM64(i) = ADEM(i+1) & ADEM(i)
-- AMCAP(i) = "0000000000000000000000000000000000000000000000000000000000000010";
-- AMCAP(i+1) <= (others => '0')
-- ADER(i) = 0x00000004
-- ADER(i+1) = 0xc0000000
-- ADER64(i) = ADER(i+1) & ADER(i)
-- s_isprev_func64(i+1) --> '1' --> don't check if the function i + 1 is selected
-- because the next ADER and ADEM are used to decode the function i.
-- The Master want access at the location 0x0008: Address= 0xc000000000000008
-- Check if the ADEM64i is compatible with the AM selected: ADEM64(i)[63:10] /= 0
-- Address[63:10] and ADEM64(i)[63:10] ADER64(i)[63:10] and ADEM64(i)[63:10]
-- | |
-- 0xc0000000000000 0xc0000000000000
-- | _______ |
-- |________________| = ? |_______________|
-- |_______|
-- No | |yes
-- FunctMatch(i) <= '0'_____| |______FunctMatch(i) <= '1'
--
-- For the 2e modes is the same, change only the ADER(i)'s XAM bit that must be '1'.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
------------------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
entity VME_Funct_Match is
Port ( clk_i : in std_logic;
s_reset : in std_logic;
s_decode : in std_logic;
s_mainFSMreset : in std_logic;
Addr : in std_logic_vector(63 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
FunctMatch : out std_logic_vector(7 downto 0);
DFS_o : out std_logic_vector(7 downto 0);
Nx_Base_Addr : out std_logic_vector(63 downto 0)
);
end VME_Funct_Match;
architecture Behavioral of VME_Funct_Match is
signal s_FUNC_ADER, s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_ADER_64, s_FUNC_ADEM_64: t_FUNC_64b_array;
signal s_isprev_func64 : std_logic_vector(7 downto 0);
signal s_locAddr : unsigned(63 downto 0);
signal debugfunct : integer;
begin
s_locAddr <= unsigned(Addr);
p_functMatch : process(clk_i)
begin
if rising_edge(clk_i) then
if s_mainFSMreset = '1' or s_reset = '1' then
FunctMatch <= (others => '0');
Nx_Base_Addr <= (others => '0');
debugfunct <= 0;
elsif s_decode = '1' then
for i in FunctMatch'range loop
case AddrWidth is
when "11" =>
if (s_FUNC_ADEM(i)(0) = '1') and (s_isprev_func64(i) = '0') and
(s_FUNC_ADEM_64(i)(63 downto 10) /= 0) then
if (s_FUNC_ADER_64(i)(63 downto 10) and s_FUNC_ADEM_64(i)(63 downto 10)) =
((s_locAddr(63 downto 10)) and s_FUNC_ADEM_64(i)(63 downto 10)) then
debugfunct <= 1;
FunctMatch(i) <= '1';
Nx_Base_Addr(63 downto 10) <= std_logic_vector(s_FUNC_ADER_64(i)(63 downto 10));
Nx_Base_Addr(9 downto 0) <= (others => '0');
end if;
end if;
when "10" =>
if (s_FUNC_ADEM(i)(31 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(31 downto 8) and s_FUNC_ADEM(i)(31 downto 8)) =
((s_locAddr(31 downto 8)) and s_FUNC_ADEM(i)(31 downto 8)) then
FunctMatch(i) <= '1';
Nx_Base_Addr(31 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(31 downto 8));
Nx_Base_Addr(63 downto 32) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 2;
end if;
end if;
when "01" =>
if (s_FUNC_ADEM(i)(23 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(23 downto 8) and s_FUNC_ADEM(i)(23 downto 8)) =
((s_locAddr(23 downto 8)) and s_FUNC_ADEM(i)(23 downto 8)) then
FunctMatch(i) <= '1';
Nx_Base_Addr(23 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(23 downto 8));
Nx_Base_Addr(63 downto 24) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 3;
end if;
end if;
when "00" =>
if (s_FUNC_ADEM(i)(15 downto 8) /=0) and (s_isprev_func64(i) = '0') then
if (s_FUNC_ADER(i)(15 downto 8) and s_FUNC_ADEM(i)(15 downto 8)) =
((s_locAddr(15 downto 8)) and s_FUNC_ADEM(i)(15 downto 8)) then
FunctMatch(i) <= '1';
Nx_Base_Addr(15 downto 8) <= std_logic_vector(s_FUNC_ADER(i)(15 downto 8));
Nx_Base_Addr(63 downto 16) <= (others => '0');
Nx_Base_Addr(7 downto 0) <= (others => '0');
debugfunct <= 4;
end if;
end if;
when others =>
end case;
end loop;
end if;
end if;
end process;
------------------------------------------------------
s_FUNC_ADER(0) <= unsigned(Ader0);
s_FUNC_ADER(1) <= unsigned(Ader1);
s_FUNC_ADER(2) <= unsigned(Ader2);
s_FUNC_ADER(3) <= unsigned(Ader3);
s_FUNC_ADER(4) <= unsigned(Ader4);
s_FUNC_ADER(5) <= unsigned(Ader5);
s_FUNC_ADER(6) <= unsigned(Ader6);
s_FUNC_ADER(7) <= unsigned(Ader7);
s_FUNC_ADEM(0) <= unsigned(Adem0);
s_FUNC_ADEM(1) <= unsigned(Adem1);
s_FUNC_ADEM(2) <= unsigned(Adem2);
s_FUNC_ADEM(3) <= unsigned(Adem3);
s_FUNC_ADEM(4) <= unsigned(Adem4);
s_FUNC_ADEM(5) <= unsigned(Adem5);
s_FUNC_ADEM(6) <= unsigned(Adem6);
s_FUNC_ADEM(7) <= unsigned(Adem7);
GDFS : for i in 0 to 7 generate
DFS_o(i) <= s_FUNC_ADEM(i)(DFS);
end generate GDFS;
GADER_64 : for i in 0 to 6 generate
s_FUNC_ADER_64(i) <= s_FUNC_ADER(i+1)&s_FUNC_ADER(i);
end generate GADER_64;
s_FUNC_ADER_64(7) <= (others => '0');
GADEM_64 : for i in 0 to 6 generate
s_FUNC_ADEM_64(i) <= s_FUNC_ADEM(i+1)&s_FUNC_ADEM(i);
s_isprev_func64(i+1) <= s_FUNC_ADEM(i)(0);
end generate GADEM_64;
s_isprev_func64(0) <= '0';
s_FUNC_ADEM_64(7) <= (others => '0');
end Behavioral;
hdl/vme64x-core/rtl/VME_IRQ_Controller.vhd 0 → 100644
View file @ 2891a297
--_________________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--_________________________________________________________________________________________
-- File: VME_IRQ_Controller.vhd
--_________________________________________________________________________________________
-- Description:
-- This block acts as Interrupter; phases of an interrupt cycle:
-- 1) The Interrupt Controller receives an interrupt request by the WB bus;
-- this request is a pulse on the INT_Req input
-- 2) The Interrupt Controller asserts ('0') one of the 7 VME_IRQ lines; --> request of a service.
-- The Interrupt priority is specificated by the Master writing the INT_Level register
-- in the CR/CSR space
-- 3) The Interrupter Controller wait for the falling edge on the VME_IACKIN line.
-- 4) When detects VME_IACKIN_n_i = '0' and the Interrupt Handler initiates the Interrupt
-- cycle by asserting AS,the Interrupt Controller check if it is the responding interrupter.
-- Indeed before responding to an interrupt acknowledge cycle the interrupter shall have
-- an interrupt request pending, shall check if the level of that request match the level
-- indicated on the address lines A1, A2 and A3,the data transfer width during the interrupt
-- acknowledge cycle should be equal or greater than the size the it can respond with, and
-- it shall receive a falling edge on its IACKIN*.
-- 5) If the it is the responding interrupter should send the source/ID on the VME_DATA lines
-- (in our case the source/ID is the INT_Vector that the Master can write in the corresponding
-- register in the CR/CSR space) and terminates the interrupt cycle with an acknowledge and
-- releases the IRQ line. If it isn't the responding interrupter should pass a falling edge on
-- down the daisy-chain so other interrupters can respond.
--
-- All the output signals are registered
-- To implement the 5 phases before mentioned the follow FSM has been implemented:
-- __________
-- |--| IACKOUT2 |<-|
-- | |__________| |
-- | |
-- | _________ | _________ _________ _________ __________
-- |-->| IDLE |--->| IRQ |-->| WAIT_AS |-->| WAIT_DS |-->| LATCH_DS |-->--|
-- |_________| |_________| |_________| |_________| |__________| |
-- | | |
-- | | _________ _________ |
-- | |---------<------------| IACKOUT1| <--| ACK_INT |<-------|
-- | |_________| |_________|
-- | __________ __________ |
-- |--<-----------------| DTACK |<--| DATA_OUT |---<----|
-- |__________| |__________|
--
-- The interrupter wait the IACKIN falling edge in the IRQ state, so if the interrupter
-- don't have interrupt pending for sure it will not respond because it is in IDLE.
-- Time constraint:
--
-- Time constraint n° 35:
-- Clk _____ _____ _____ _____ _____ _____
-- _____| |_____| |_____| |_____| |_____| |_____| |_____
-- VME_AS1_n_i ______________________________________________________________________
-- ______|
-- VME_AS_n_i __________________________________________________________
-- __________________|
-- AS_RisingEdge ___________
-- __________________| |______________________________________________
-- s_IACKOUT ______________________________________________________________________
-- ______|
-- VME_IACKOUT_o __________________________________________________________
-- __________________|
--
-- ______________________________ _____________________________________________
-- IACKOUT 1/2 \/ IDLE/IRQ
-- ------------------------------/\---------------------------------------------
--
-- To avoid the time constraint indicated with the number 35 fig. 55 pag. 183 in the
-- "VMEbus Specification" ANSI/IEEE STD1014-1987, is necessary generate the VME_AS1_n_i
-- signal who is the AS signal sampled only two times and not 3 times as the VME_AS_n_i signal,
-- and assign this signal to the s_IACKOUT signal when the fsm is in the IACKOUTx state.
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
use work.vme64x_pack.all;
entity VME_IRQ_Controller is
Port ( clk_i : in std_logic;
reset : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector (1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123 : in std_logic_vector (2 downto 0);
INT_Level : in std_logic_vector (7 downto 0);
INT_Vector : in std_logic_vector (7 downto 0);
INT_Req : in std_logic;
VME_IRQ_n_o : out std_logic_vector (6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector (31 downto 0);
DataDir : out std_logic);
end VME_IRQ_Controller;
architecture Behavioral of VME_IRQ_Controller is
--input signals
signal INT_Req_sample : std_logic;
--output signals
signal s_DTACK : std_logic;
signal s_DTACK_OE : std_logic;
signal s_DataDir : std_logic;
signal s_IACKOUT : std_logic;
signal s_IACKOUT_o : std_logic;
signal s_enable : std_logic;
signal s_IRQ : std_logic_vector(6 downto 0);
signal s_Data : std_logic_vector(31 downto 0);
--
signal AS_FallingEdge : std_logic;
signal AS_RisingEdge : std_logic;
type t_MainFSM is (IDLE, IRQ, WAIT_AS, WAIT_DS, LATCH_DS, ACK_INT, DATA_OUT, DTACK,IACKOUT1,IACKOUT2);
signal currs, nexts : t_MainFSM;
signal s_ack_int : std_logic;
signal s_resetIRQ : std_logic;
signal s_enableIRQ : std_logic;
signal VME_ADDR_123_latched : std_logic_vector(2 downto 0);
signal VME_DS_latched : std_logic_vector(1 downto 0);
signal DSlatch : std_logic;
signal ADDRmatch : std_logic;
begin
-- Input sampling and edge detection
ASrisingEdge : RisEdgeDetection
port map (
sig_i => VME_AS1_n_i,
clk_i => clk_i,
RisEdge_o => AS_RisingEdge
);
ASfallingEdge : FallingEdgeDetection
port map (
sig_i => VME_AS_n_i,
clk_i => clk_i,
FallEdge_o => AS_FallingEdge
);
INT_ReqinputSample : FlipFlopD
port map(
sig_i => INT_Req,
sig_o => INT_Req_sample,
clk_i => clk_i,
reset => '0',
enable => s_enable
);
--Output registers:
DTACKOutputSample : FlipFlopD
port map(
sig_i => s_DTACK,
sig_o => VME_DTACK_n_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
DataDirOutputSample : FlipFlopD
port map(
sig_i => s_DataDir,
sig_o => DataDir,
clk_i => clk_i,
reset => '0',
enable => '1'
);
IACKOUTOutputSample : FlipFlopD
port map(
sig_i => s_IACKOUT,
sig_o => s_IACKOUT_o,
clk_i => clk_i,
reset => '0',
enable => '1'
);
process(clk_i)
begin
if rising_edge(clk_i) then
if s_resetIRQ = '1' then
VME_IRQ_n_o <= (others => '1');
elsif s_enableIRQ = '1' then
VME_IRQ_n_o <= s_IRQ;
end if;
end if;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
VME_DATA_o <= s_Data;
end if;
end process;
-- Update current state
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
currs <= IDLE;
else
currs <= nexts;
end if;
end if;
end process;
-- Update next state
process(currs,INT_Req_sample,VME_AS_n_i,VME_DS_n_i,s_ack_int,VME_IACKIN_n_i)
begin
case currs is
when IDLE =>
if INT_Req_sample = '1' and VME_IACKIN_n_i = '1' then
nexts <= IRQ;
elsif VME_IACKIN_n_i = '0' then
nexts <= IACKOUT2;
else
nexts <= IDLE;
end if;
when IRQ =>
if VME_IACKIN_n_i = '0' then -- Each Interrupter who is driving an interrupt request line
-- low waits for a falling edge on IACKIN input -->
-- the IRQ_Controller have to detect a falling edge on the IACKIN.
nexts <= WAIT_AS;
else
nexts <= IRQ;
end if;
when WAIT_AS =>
if VME_AS_n_i = '0' then -- NOT USE FALLING EDGE HERE!
nexts <= WAIT_DS;
else
nexts <= WAIT_AS;
end if;
when WAIT_DS =>
if VME_DS_n_i /= "11" then
nexts <= LATCH_DS;
else
nexts <= WAIT_DS;
end if;
when LATCH_DS =>
nexts <= ACK_INT;
when ACK_INT =>
if s_ack_int = '1' then
nexts <= DATA_OUT; -- The Interrupter send the INT_Vector
else
nexts <= IACKOUT1; -- the Interrupter must pass a falling edge on the IACKOUT output
end if;
when IACKOUT1 =>
if AS_RisingEdge = '1' then
nexts <= IRQ;
else
nexts <= IACKOUT1;
end if;
when DATA_OUT=>
nexts <= DTACK;
when IACKOUT2 =>
if AS_RisingEdge = '1' then
nexts <= IDLE;
else
nexts <= IACKOUT2;
end if;
when DTACK=>
if AS_RisingEdge = '1' then
nexts <= IDLE;
else
nexts <= DTACK;
end if;
end case;
end process;
-- Update Outputs
process(currs,AS_RisingEdge)
begin
case currs is
when IDLE =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '1';
DSlatch <= '0';
s_DTACK_OE <= '0';
when IRQ =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '1';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when WAIT_AS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when WAIT_DS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when LATCH_DS =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '1';
s_DTACK_OE <= '0';
when ACK_INT =>
s_IACKOUT <= '1';
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when IACKOUT1 =>
s_IACKOUT <= VME_AS1_n_i;
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when IACKOUT2 =>
s_IACKOUT <= VME_AS1_n_i;
s_DataDir <= '0';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '0';
when DATA_OUT=>
s_IACKOUT <= '1';
s_DataDir <= '1';
s_DTACK <= '1';
s_enableIRQ <= '0';
s_resetIRQ <= '0';
DSlatch <= '0';
s_DTACK_OE <= '1';
when DTACK=>
s_IACKOUT <= '1';
s_DataDir <= '1';
s_DTACK <= '0';
s_enableIRQ <= '0';
s_resetIRQ <= '1';
DSlatch <= '0';
s_DTACK_OE <= '1';
end case;
end process;
-- This process provides the IRQ vector
process(INT_Level)
begin
case (INT_Level) is
when "00000001" => s_IRQ <= "1111110";
when "00000010" => s_IRQ <= "1111101";
when "00000011" => s_IRQ <= "1111011";
when "00000100" => s_IRQ <= "1110111";
when "00000101" => s_IRQ <= "1101111";
when "00000110" => s_IRQ <= "1011111";
when "00000111" => s_IRQ <= "0111111";
when others => s_IRQ <= "1111111";
end case;
end process;
-- This process sampling the address lines on AS falling edge
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
VME_ADDR_123_latched <= (others => '0');
elsif AS_FallingEdge = '1' then
VME_ADDR_123_latched <= VME_ADDR_123;
end if;
end if;
end process;
-- Data strobo latch
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
VME_DS_latched <= (others => '0');
elsif DSlatch = '1' then
VME_DS_latched <= VME_DS_n_i;
end if;
end if;
end process;
--This process check the A01 A02 A03:
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
ADDRmatch <= '0';
elsif unsigned(INT_Level) = unsigned(VME_ADDR_123_latched) then
ADDRmatch <= '1';
else
ADDRmatch <= '0';
end if;
end if;
end process;
s_ack_int <= (not(VME_DS_latched(0))) and ADDRmatch; --D08 Byte3 access or D32 access
s_Data <= x"000000" & INT_Vector;
s_enable <= VME_IACKIN_n_i and s_IACKOUT_o;
-- the INT_Vector is in the D0:7 lines (byte3 in big endian order)
VME_DTACK_OE_o <= s_DTACK_OE;
VME_IACKOUT_n_o <= s_IACKOUT_o;
end Behavioral;
hdl/vme64x-core/rtl/VME_Init.vhd 0 → 100644
View file @ 2891a297
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
-- File: VME_Init.vhd
--________________________________________________________________________________________________
-- Description: Read important CR data (like FUNC_ADEMs etc.) and store it locally
-- This important CR data will be used in the decoder.
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.vme64x_pack.all;
entity VME_Init is
Port ( clk_i : in std_logic;
RSTedge : inout std_logic;
CRAddr : in std_logic_vector (18 downto 0);
CRdata_i : in std_logic_vector (7 downto 0);
InitReadCount : out std_logic_vector (8 downto 0);
InitInProgress : out std_logic;
BEG_USR_CR_o : out std_logic_vector (23 downto 0);
END_USR_CR_o : out std_logic_vector (23 downto 0);
BEG_USR_CSR_o : out std_logic_vector (23 downto 0);
END_USR_CSR_o : out std_logic_vector (23 downto 0);
BEG_CRAM_o : out std_logic_vector (23 downto 0);
END_CRAM_o : out std_logic_vector (23 downto 0);
FUNC0_ADEM_o : out std_logic_vector (31 downto 0);
FUNC1_ADEM_o : out std_logic_vector (31 downto 0);
FUNC2_ADEM_o : out std_logic_vector (31 downto 0);
FUNC3_ADEM_o : out std_logic_vector (31 downto 0);
FUNC4_ADEM_o : out std_logic_vector (31 downto 0);
FUNC5_ADEM_o : out std_logic_vector (31 downto 0);
FUNC6_ADEM_o : out std_logic_vector (31 downto 0);
FUNC7_ADEM_o : out std_logic_vector (31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector (63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector (255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector (255 downto 0));
end VME_Init;
architecture Behavioral of VME_Init is
signal s_initReadCounter : unsigned(8 downto 0);
signal s_initState : t_initState;
signal s_latchCRdata : std_logic; -- Stores read CR data
signal s_initInProgress : std_logic;
signal s_CRadd_offset : unsigned(18 downto 0);
signal s_CRaddr_base : unsigned(18 downto 0);
signal s_CRaddr : unsigned(18 downto 0);
signal s_latchCRdataPos : std_logic_vector(BEG_USER_CR to FUNC_ADEM);
-- CR image registers
signal s_FUNC_ADEM : t_FUNC_32b_array;
signal s_FUNC_AMCAP : t_FUNC_64b_array;
signal s_FUNC_XAMCAP : t_FUNC_256b_array;
signal s_BEG_USER_CSR : unsigned(23 downto 0);
signal s_END_USER_CSR : unsigned(23 downto 0);
signal s_BEG_USER_CR : unsigned(23 downto 0);
signal s_END_USER_CR : unsigned(23 downto 0);
signal s_BEG_CRAM : unsigned(23 downto 0);
signal s_END_CRAM : unsigned(23 downto 0);
begin
InitReadCount <= std_logic_vector(s_initReadCounter);
s_CRaddr <= unsigned(CRAddr);
p_coreInit : process(clk_i)
begin
if rising_edge(clk_i) then
if RSTedge = '1' then
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
else
case s_initState is
when IDLE =>
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
s_initState <= SET_ADDR;
when SET_ADDR =>
s_initReadCounter <= s_initReadCounter+1;
s_latchCRdata <= '0';
s_initState <= GET_DATA;
when GET_DATA =>
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '1';
if s_initInProgress = '1' then
s_initState <= SET_ADDR;
else
s_initState <= END_INIT;
end if;
when END_INIT => -- will wait in this state until reset
s_initReadCounter <= s_initReadCounter;
s_latchCRdata <= '0';
s_initState <= END_INIT;
when others =>
s_initState <= IDLE;
s_initReadCounter <= to_unsigned(0, s_initReadCounter'length);
s_latchCRdata <= '0';
end case;
end if;
end if;
end process;
s_initInProgress <= '1' when (s_initReadCounter <= (424)) else '0';
InitInProgress <= s_initInProgress;
s_CRadd_offset <= s_CRaddr - s_CRaddr_base;
process(s_latchCRdata, s_initReadCounter)
begin
s_latchCRdataPos <= (others => '0');
s_CRaddr_base <= (others => '0');
for I in c_CRinitAddr'range loop
if (s_initReadCounter >= c_CRinitAddr(I).add) and
(s_initReadCounter <= (c_CRinitAddr(I).add+(c_CRinitAddr(I).len-1))) then
s_CRaddr_base <= to_unsigned(c_CRinitAddr(I).add, s_CRaddr_base'length);
s_latchCRdataPos(I) <= s_latchCRdata;
exit;
end if;
end loop;
end process;
process(clk_i)
begin
if rising_edge(clk_i) then
for I in 0 to 2 loop
if (s_latchCRdataPos(BEG_USER_CR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_USER_CR(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if s_latchCRdataPos(END_USER_CR) = '1' and (unsigned(s_CRadd_offset) = I) then
s_END_USER_CR(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_USER_CSR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_USER_CSR(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_USER_CSR) = '1') and (unsigned(s_CRadd_offset) = I) then
s_END_USER_CSR(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(BEG_CRAM) = '1') and (unsigned(s_CRadd_offset) = I) then
s_BEG_CRAM(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
if (s_latchCRdataPos(END_CRAM) = '1') and (unsigned(s_CRadd_offset) = I) then
s_END_CRAM(((3-I)*8 - 1) downto (2-I)*8) <= unsigned(CRdata_i);
end if;
end loop;
for I in 0 to 7 loop
if (s_latchCRdataPos(FUNC_AMCAP) = '1') and (unsigned(s_CRadd_offset(5 downto 3)) = I) then
for H in 0 to 7 loop
if (unsigned(s_CRadd_offset(2 downto 0)) = H) then
s_FUNC_AMCAP(I)(((8-h)*8 - 1) downto (7-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_ADEM) = '1') and (unsigned(s_CRadd_offset(5 downto 2)) = I) then
for H in 0 to 3 loop
if (unsigned(s_CRadd_offset(1 downto 0)) = H) then
s_FUNC_ADEM(I)(((4-h)*8 - 1) downto (3-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
if (s_latchCRdataPos(FUNC_XAMCAP) = '1') and (unsigned(s_CRadd_offset(7 downto 5)) = I) then
for H in 0 to 31 loop
if (unsigned(s_CRadd_offset(4 downto 0)) = H) then
s_FUNC_XAMCAP(I)(((32-h)*8 - 1) downto (31-h)*8) <= unsigned(CRdata_i);
end if;
end loop;
end if;
end loop;
end if;
end process;
BEG_USR_CR_o <= std_logic_vector(s_BEG_USER_CR);
END_USR_CR_o <= std_logic_vector(s_END_USER_CR);
BEG_USR_CSR_o <= std_logic_vector(s_BEG_USER_CSR);
END_USR_CSR_o <= std_logic_vector(s_END_USER_CSR);
BEG_CRAM_o <= std_logic_vector(s_BEG_CRAM);
END_CRAM_o <= std_logic_vector(s_END_CRAM);
FUNC0_ADEM_o <= std_logic_vector(s_FUNC_ADEM(0));
FUNC1_ADEM_o <= std_logic_vector(s_FUNC_ADEM(1));
FUNC2_ADEM_o <= std_logic_vector(s_FUNC_ADEM(2));
FUNC3_ADEM_o <= std_logic_vector(s_FUNC_ADEM(3));
FUNC4_ADEM_o <= std_logic_vector(s_FUNC_ADEM(4));
FUNC5_ADEM_o <= std_logic_vector(s_FUNC_ADEM(5));
FUNC6_ADEM_o <= std_logic_vector(s_FUNC_ADEM(6));
FUNC7_ADEM_o <= std_logic_vector(s_FUNC_ADEM(7));
FUNC0_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(0));
FUNC1_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(1));
FUNC2_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(2));
FUNC3_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(3));
FUNC4_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(4));
FUNC5_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(5));
FUNC6_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(6));
FUNC7_AMCAP_o <= std_logic_vector(s_FUNC_AMCAP(7));
FUNC0_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(0));
FUNC1_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(1));
FUNC2_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(2));
FUNC3_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(3));
FUNC4_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(4));
FUNC5_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(5));
FUNC6_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(6));
FUNC7_XAMCAP_o <= std_logic_vector(s_FUNC_XAMCAP(7));
end Behavioral;
hdl/vme64x-core/rtl/VME_SharedComps.vhd 0 → 100755
View file @ 2891a297
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- tripple sample sig_i signals to avoid metastable states
entity SigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end SigInputSample;
architecture RTL of SigInputSample is
signal s_1: std_logic;
signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
s_2 <= s_1;
sig_o <= s_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- double sample sig_i signals to avoid metastable states
entity DoubleSigInputSample is
port (
sig_i, clk_i: in std_logic;
sig_o: out std_logic );
end DoubleSigInputSample;
architecture RTL of DoubleSigInputSample is
signal s_1: std_logic;
-- signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
sig_o <= s_1;
end if;
end process;
end RTL;
-- ***************************************************
--FlipFlopD
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity FlipFlopD is
port (
reset, sig_i, clk_i, enable: in std_logic;
sig_o: out std_logic );
end FlipFlopD;
architecture RTL of FlipFlopD is
-- signal s_1: std_logic;
-- signal s_2: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '1' then
sig_o <= '0';
elsif enable = '1' then
sig_o <= sig_i;
--sig_o <= s_1;
end if;
end if;
end process;
end RTL;
--Register 32 bits
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity Reg32bit is
port (
reset, clk_i, enable: in std_logic;
di : in std_logic_vector(31 downto 0);
do: out std_logic_vector(31 downto 0)
);
end Reg32bit;
architecture RTL of Reg32bit is
--signal s_reg : std_logic_vector(31 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if reset = '0' then
do <= (others => '0');
--s_reg <= (others => '0');
elsif enable = '1' then
do <= di;
--s_reg <= di;
end if;
end if;
--do <= s_reg;
end process;
end RTL;
--
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect rising edge
entity RisEdgeDetection is
port (
sig_i, clk_i: in std_logic;
RisEdge_o: out std_logic );
end RisEdgeDetection;
architecture RTL of RisEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '0' and sig_i = '1' then
RisEdge_o <= '1';
else
RisEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- detect falling edge
entity FallingEdgeDetection is
port (
sig_i, clk_i: in std_logic;
FallEdge_o: out std_logic );
end FallingEdgeDetection;
architecture RTL of FallingEdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if s_1 = '1' and sig_i = '0' then
FallEdge_o <= '1';
else
FallEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- give pulse (sigEdge_o) at rising and falling edge
entity EdgeDetection is
port (
sig_i,
clk_i: in std_logic;
sigEdge_o: out std_logic
);
end EdgeDetection;
architecture RTL of EdgeDetection is
signal s_1: std_logic;
begin
process(clk_i)
begin
if rising_edge(clk_i) then
s_1 <= sig_i;
if (s_1 = '0' and sig_i = '1') or (s_1 = '1' and sig_i = '0') then
sigEdge_o <= '1';
else
sigEdge_o <= '0';
end if;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity RegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end RegInputSample;
architecture RTL of RegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_2 <= reg_1;
reg_o <= reg_2;
end if;
end process;
end RTL;
-- ***************************************************
library IEEE;
use IEEE.STD_LOGIC_1164.all;
-- triple sample input register reg_i to avoid metastable states
-- and catching of transition values
entity DoubleRegInputSample is
generic(
width: natural:=8
);
port (
reg_i: in std_logic_vector(width-1 downto 0);
reg_o: out std_logic_vector(width-1 downto 0);
clk_i: in std_logic
);
end DoubleRegInputSample;
architecture RTL of DoubleRegInputSample is
signal reg_1, reg_2: std_logic_vector(width-1 downto 0);
begin
process(clk_i)
begin
if rising_edge(clk_i) then
reg_1 <= reg_i;
reg_o <= reg_1;
end if;
end process;
end RTL;
\ No newline at end of file
hdl/vme64x-core/rtl/VME_Wb_master.vhd 0 → 100644
View file @ 2891a297
--___________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--___________________________________________________________________________________
-- File: Wb_master.vhd
--___________________________________________________________________________________
-- Description:
-- This component implements the WB master side in the vme64x core.
-- Work mode:
-- PIPELINED
-- SINGLE READ/WRITE
--
-- The WB bus is 64 bit wide and the data organization is BIG ENDIAN --> the most
-- significant byte is carried in the lower position of the bus.
-- _______________________________________________________________________
-- | Byte(0)| Byte(1)| Byte(2)| Byte(3)| Byte(4)| Byte(5)| Byte(6)| Byte(7)|
-- |________|________|________|________|________|________|________|________|
-- D[63:56] D[55:48] D[47:40] D[39:32] D[31:24] D[23:16] D[15:8] D[7:0]
--
-- eg of timing diagram with synchronous WB Slave:
--
-- Clk _____ _____ _____ _____ _____ _____ _____
-- _____| |_____| |_____| |_____| |_____| |_____| |_____|
-- cyc_o ____________________________________________________________
-- _____| |________________
-- stb_o ________________________________________________
-- _____| |____________________________
-- __________________________________________
-- stall_i |________________________________________
-- ack_i ___________
-- ______________________________________________________| |________________
--
-- The ack_i can be asserted with some Tclk of delay, not immediately.
-- This component implements the correct shift of the data in input/output from WB bus
--
--______________________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.numeric_std.all;
entity VME_Wb_master is
Port ( s_memReq : in std_logic;
clk_i : in std_logic;
s_cardSel : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
s_BERRcondition : in std_logic;
s_sel : in std_logic_vector (7 downto 0);
s_beatCount : in std_logic_vector (8 downto 0);
s_locDataInSwap : in std_logic_vector (63 downto 0);
s_locDataOut : out std_logic_vector (63 downto 0);
s_rel_locAddr : in std_logic_vector (63 downto 0);
s_AckWithError : out std_logic;
memAckWb : out std_logic;
err : out std_logic;
rty : out std_logic;
s_RW : in std_logic;
psize_o : out std_logic_vector (8 downto 0);
stall_i : in std_logic;
rty_i : in std_logic;
err_i : in std_logic;
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector (63 downto 0);
wbData_i : in std_logic_vector (63 downto 0);
locAddr_o : out std_logic_vector (63 downto 0);
memAckWB_i : in std_logic;
WbSel_o : out std_logic_vector (7 downto 0);
RW_o : out std_logic);
end VME_Wb_master;
architecture Behavioral of VME_Wb_master is
-- stb_o handler
begin
process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' or stall_i = '0' then
memReq_o <= '0';
elsif s_memReq = '1' and s_cardSel = '1' and s_BERRcondition = '0' then
memReq_o <= '1';
end if;
end if;
end process;
-- cyc_o handler
process(clk_i)
begin
if rising_edge(clk_i) then
if s_reset = '1' or s_mainFSMreset = '1' or memAckWB_i = '1' then
cyc_o <= '0';
elsif s_memReq = '1' and s_cardSel = '1' and s_BERRcondition = '0' then
cyc_o <= '1';
end if;
end if;
end process;
-- shift output data to WB
process(clk_i)
begin
if rising_edge(clk_i) then
if s_sel = "10000000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 56);
elsif s_sel = "01000000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 48);
elsif s_sel = "00100000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 40);
elsif s_sel = "00010000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 32);
elsif s_sel = "00001000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 24);
elsif s_sel = "00000100" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 16);
elsif s_sel = "00000010" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 8);
elsif s_sel = "11000000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 48);
elsif s_sel = "00110000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 32);
elsif s_sel = "00001100" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 16);
elsif s_sel = "11110000" then
WBdata_o <= std_logic_vector(unsigned(s_locDataInSwap) sll 32);
else
WBdata_o <= s_locDataInSwap;
end if;
RW_o <= s_RW;
s_AckWithError <=(s_memReq and s_cardSel and s_BERRcondition);
WbSel_o <= std_logic_vector(s_sel);
end if;
end process;
-- shift input data from WB
s_locDataOut <= std_logic_vector(resize(unsigned(wbData_i(15 downto 0)) srl 8,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00000010" else
std_logic_vector(resize(unsigned(wbData_i(23 downto 0)) srl 16,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00000100" else
std_logic_vector(resize(unsigned(wbData_i(31 downto 0)) srl 24,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00001000" else
std_logic_vector(resize(unsigned(wbData_i(39 downto 0)) srl 32,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00010000" else
std_logic_vector(resize(unsigned(wbData_i(47 downto 0)) srl 40,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00100000" else
std_logic_vector(resize(unsigned(wbData_i(55 downto 0)) srl 48,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "01000000" else
std_logic_vector(resize(unsigned(wbData_i) srl 56,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "10000000" else
std_logic_vector(resize(unsigned(wbData_i(31 downto 0)) srl 16,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00001100" else
std_logic_vector(resize(unsigned(wbData_i(47 downto 0)) srl 32,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00110000" else
std_logic_vector(resize(unsigned(wbData_i) srl 48,s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "11000000" else
std_logic_vector(resize(unsigned(wbData_i(7 downto 0)), s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00000001" else
std_logic_vector(resize(unsigned(wbData_i(15 downto 0)), s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00000011" else
std_logic_vector(resize(unsigned(wbData_i(31 downto 0)), s_locDataOut'length)) when
s_cardSel = '1' and s_sel = "00001111" else
std_logic_vector(unsigned(wbData_i) srl 32) when
s_cardSel = '1' and s_sel = "11110000" else
std_logic_vector(unsigned(wbData_i)) when
s_cardSel = '1' and s_sel = "11111111" else
(others => '0');
locAddr_o <= b"000" & s_rel_locAddr(63 downto 3);
err <= err_i;
rty <= rty_i;
memAckWb <= memAckWB_i;
psize_o <= s_beatCount;
end Behavioral;
hdl/vme64x-core/rtl/VME_bus.vhd
View file @ 2891a297
This source diff could not be displayed because it is too large. You can view the blob instead.
hdl/vme64x-core/rtl/VME_swapper.vhd 0 → 100644
View file @ 2891a297
--________________________________________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--________________________________________________________________________________________________
-- File: VME_swapper.vhd
--________________________________________________________________________________________________
-- Description:
--sel= 00 --> No swap
--sel= 01 --> Swap Byte eg: 01234567 became 10325476
--sel= 10 --> Swap Word eg: 01234567 became 23016745
--sel= 11 --> Swap Word+ Swap Byte eg: 01234567 became 32107654
--______________________________________________________________________________
-- Authors:
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--______________________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity VME_swapper is
Port ( d_i : in STD_LOGIC_VECTOR (63 downto 0);
sel : in STD_LOGIC_VECTOR (2 downto 0);
d_o : out STD_LOGIC_VECTOR (63 downto 0));
end VME_swapper;
architecture Behavioral of VME_swapper is
signal Byte0_i : std_logic_vector(7 downto 0);
signal Byte1_i : std_logic_vector(7 downto 0);
signal Byte2_i : std_logic_vector(7 downto 0);
signal Byte3_i : std_logic_vector(7 downto 0);
signal Byte4_i : std_logic_vector(7 downto 0);
signal Byte5_i : std_logic_vector(7 downto 0);
signal Byte6_i : std_logic_vector(7 downto 0);
signal Byte7_i : std_logic_vector(7 downto 0);
signal Byte0_o : std_logic_vector(7 downto 0);
signal Byte1_o : std_logic_vector(7 downto 0);
signal Byte2_o : std_logic_vector(7 downto 0);
signal Byte3_o : std_logic_vector(7 downto 0);
signal Byte4_o : std_logic_vector(7 downto 0);
signal Byte5_o : std_logic_vector(7 downto 0);
signal Byte6_o : std_logic_vector(7 downto 0);
signal Byte7_o : std_logic_vector(7 downto 0);
begin
process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte7_i)
begin
case sel is
when "000" => Byte0_o <= Byte0_i;
when "001" => Byte0_o <= Byte1_i;
when "010" => Byte0_o <= Byte2_i;
when "011" => Byte0_o <= Byte3_i;
when "100" => Byte0_o <= Byte7_i;
when others => Byte0_o <= Byte0_i;
end case;
end process;
process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte6_i)
begin
case sel is
when "000" => Byte1_o <= Byte1_i;
when "001" => Byte1_o <= Byte0_i;
when "010" => Byte1_o <= Byte3_i;
when "011" => Byte1_o <= Byte2_i;
when "100" => Byte1_o <= Byte6_i;
when others => Byte1_o <= Byte1_i;
end case;
end process;
process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte5_i)
begin
case sel is
when "000" => Byte2_o <= Byte2_i;
when "001" => Byte2_o <= Byte3_i;
when "010" => Byte2_o <= Byte0_i;
when "011" => Byte2_o <= Byte1_i;
when "100" => Byte2_o <= Byte5_i;
when others => Byte2_o <= Byte2_i;
end case;
end process;
process (sel,Byte0_i,Byte1_i,Byte2_i,Byte3_i,Byte4_i)
begin
case sel is
when "000" => Byte3_o <= Byte3_i;
when "001" => Byte3_o <= Byte2_i;
when "010" => Byte3_o <= Byte1_i;
when "011" => Byte3_o <= Byte0_i;
when "100" => Byte3_o <= Byte4_i;
when others => Byte3_o <= Byte3_i;
end case;
end process;
process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte3_i)
begin
case sel is
when "000" => Byte4_o <= Byte4_i;
when "001" => Byte4_o <= Byte5_i;
when "010" => Byte4_o <= Byte6_i;
when "011" => Byte4_o <= Byte7_i;
when "100" => Byte4_o <= Byte3_i;
when others => Byte4_o <= Byte4_i;
end case;
end process;
process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte2_i)
begin
case sel is
when "000" => Byte5_o <= Byte5_i;
when "001" => Byte5_o <= Byte4_i;
when "010" => Byte5_o <= Byte7_i;
when "011" => Byte5_o <= Byte6_i;
when "100" => Byte5_o <= Byte2_i;
when others => Byte5_o <= Byte5_i;
end case;
end process;
process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte1_i)
begin
case sel is
when "000" => Byte6_o <= Byte6_i;
when "001" => Byte6_o <= Byte7_i;
when "010" => Byte6_o <= Byte4_i;
when "011" => Byte6_o <= Byte5_i;
when "100" => Byte6_o <= Byte1_i;
when others => Byte6_o <= Byte6_i;
end case;
end process;
process (sel,Byte4_i,Byte5_i,Byte6_i,Byte7_i,Byte0_i)
begin
case sel is
when "000" => Byte7_o <= Byte7_i;
when "001" => Byte7_o <= Byte6_i;
when "010" => Byte7_o <= Byte5_i;
when "011" => Byte7_o <= Byte4_i;
when "100" => Byte7_o <= Byte0_i;
when others => Byte7_o <= Byte7_i;
end case;
end process;
Byte0_i <= d_i(7 downto 0);
Byte1_i <= d_i(15 downto 8);
Byte2_i <= d_i(23 downto 16);
Byte3_i <= d_i(31 downto 24);
Byte4_i <= d_i(39 downto 32);
Byte5_i <= d_i(47 downto 40);
Byte6_i <= d_i(55 downto 48);
Byte7_i <= d_i(63 downto 56);
d_o(7 downto 0) <= Byte0_o;
d_o(15 downto 8) <= Byte1_o;
d_o(23 downto 16) <= Byte2_o;
d_o(31 downto 24) <= Byte3_o;
d_o(39 downto 32) <= Byte4_o;
d_o(47 downto 40) <= Byte5_o;
d_o(55 downto 48) <= Byte6_o;
d_o(63 downto 56) <= Byte7_o;
end Behavioral;
hdl/vme64x-core/rtl/vme64x_pack.vhd 0 → 100644
View file @ 2891a297
--______________________________________________________________________
-- VME TO WB INTERFACE
--
-- CERN,BE/CO-HT
--______________________________________________________________________
-- File: vme64x_pack.vhd
--______________________________________________________________________
-- Authors:
-- Pablo Alvarez Sanchez (Pablo.Alvarez.Sanchez@cern.ch)
-- Davide Pedretti (Davide.Pedretti@cern.ch)
-- Date 06/2012
-- Version v0.01
--_______________________________________________________________________
-- GNU LESSER GENERAL PUBLIC LICENSE
-- ------------------------------------
-- This source file is free software; you can redistribute it and/or modify it under the terms of
-- the GNU Lesser General Public License as published by the Free Software Foundation; either
-- version 2.1 of the License, or (at your option) any later version.
-- This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY;
-- without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details.
-- You should have received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
---------------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all;
package vme64x_pack is
--__________________________________________________________________________________
-- Records:
type t_rom_cell is
record
add : integer;
len : integer;
end record;
type t_cr_add_table is array (natural range <>) of t_rom_cell;
type t_FSM is
record
s_memReq : std_logic;
s_decode : std_logic;
s_dtackOE : std_logic;
s_mainDTACK : std_logic;
s_dataDir : std_logic;
s_dataOE : std_logic;
s_addrDir : std_logic;
s_addrOE : std_logic;
s_DSlatch : std_logic;
s_incrementAddr : std_logic;
s_dataPhase : std_logic;
s_dataToOutput : std_logic;
s_dataToAddrBus : std_logic;
s_transferActive : std_logic;
s_2eLatchAddr : std_logic_vector(1 downto 0);
s_retry : std_logic;
s_berr : std_logic;
s_BERR_out : std_logic;
end record;
--_______________________________________________________________________________
-- Constants:
constant DFS : integer := 2; -- for accessing at the ADEM's bit 2
constant XAM_MODE : integer := 0; -- for accessing at the ADER's bit 0
constant clk_period : std_logic_vector(19 downto 0) := "00000000000000110010";
--AM table:
constant c_A24_S_sup : std_logic_vector(5 downto 0) := "111101";
constant c_A24_S : std_logic_vector(5 downto 0) := "111001";
constant c_A24_BLT : std_logic_vector(5 downto 0) := "111011";
constant c_A24_BLT_sup : std_logic_vector(5 downto 0) := "111111";
constant c_A24_MBLT : std_logic_vector(5 downto 0) := "111000";
constant c_A24_MBLT_sup : std_logic_vector(5 downto 0) := "111100";
constant c_A24_LCK : std_logic_vector(5 downto 0) := "110010";
constant c_CR_CSR : std_logic_vector(5 downto 0) := "101111";
constant c_A16 : std_logic_vector(5 downto 0) := "101001";
constant c_A16_sup : std_logic_vector(5 downto 0) := "101101";
constant c_A16_LCK : std_logic_vector(5 downto 0) := "101100";
constant c_A32 : std_logic_vector(5 downto 0) := "001001";
constant c_A32_sup : std_logic_vector(5 downto 0) := "001101";
constant c_A32_BLT : std_logic_vector(5 downto 0) := "001011";
constant c_A32_BLT_sup : std_logic_vector(5 downto 0) := "001111";
constant c_A32_MBLT : std_logic_vector(5 downto 0) := "001000";
constant c_A32_MBLT_sup : std_logic_vector(5 downto 0) := "001100";
constant c_A32_LCK : std_logic_vector(5 downto 0) := "000101";
constant c_A64 : std_logic_vector(5 downto 0) := "000001";
constant c_A64_BLT : std_logic_vector(5 downto 0) := "000011";
constant c_A64_MBLT : std_logic_vector(5 downto 0) := "000000";
constant c_A64_LCK : std_logic_vector(5 downto 0) := "000100";
constant c_TWOedge : std_logic_vector(5 downto 0) := "100000";
constant c_A32_2eVME : std_logic_vector(7 downto 0) := "00000001";
constant c_A64_2eVME : std_logic_vector(7 downto 0) := "00000010";
constant c_A32_2eSST : std_logic_vector(7 downto 0) := "00010001";
constant c_A64_2eSST : std_logic_vector(7 downto 0) := "00010010";
--CSR array's index:
constant BAR : integer := 255;
constant BIT_SET_CLR_REG : integer := 254;
constant USR_BIT_SET_CLR_REG : integer := 253;
constant CRAM_OWNER : integer := 252;
constant FUNC7_ADER_0 : integer := 251;
constant FUNC7_ADER_1 : integer := FUNC7_ADER_0 - 1;
constant FUNC7_ADER_2 : integer := FUNC7_ADER_0 - 2;
constant FUNC7_ADER_3 : integer := FUNC7_ADER_0 - 3;
constant FUNC6_ADER_0 : integer := FUNC7_ADER_0 - 4;
constant FUNC6_ADER_1 : integer := FUNC7_ADER_0 - 5;
constant FUNC6_ADER_2 : integer := FUNC7_ADER_0 - 6;
constant FUNC6_ADER_3 : integer := FUNC7_ADER_0 - 7;
constant FUNC5_ADER_0 : integer := FUNC7_ADER_0 - 8;
constant FUNC5_ADER_1 : integer := FUNC7_ADER_0 - 9;
constant FUNC5_ADER_2 : integer := FUNC7_ADER_0 - 10;
constant FUNC5_ADER_3 : integer := FUNC7_ADER_0 - 11;
constant FUNC4_ADER_0 : integer := FUNC7_ADER_0 - 12;
constant FUNC4_ADER_1 : integer := FUNC7_ADER_0 - 13;
constant FUNC4_ADER_2 : integer := FUNC7_ADER_0 - 14;
constant FUNC4_ADER_3 : integer := FUNC7_ADER_0 - 15;
constant FUNC3_ADER_0 : integer := FUNC7_ADER_0 - 16;
constant FUNC3_ADER_1 : integer := FUNC7_ADER_0 - 17;
constant FUNC3_ADER_2 : integer := FUNC7_ADER_0 - 18;
constant FUNC3_ADER_3 : integer := FUNC7_ADER_0 - 19;
constant FUNC2_ADER_0 : integer := FUNC7_ADER_0 - 20;
constant FUNC2_ADER_1 : integer := FUNC7_ADER_0 - 21;
constant FUNC2_ADER_2 : integer := FUNC7_ADER_0 - 22;
constant FUNC2_ADER_3 : integer := FUNC7_ADER_0 - 23;
constant FUNC1_ADER_0 : integer := FUNC7_ADER_0 - 24;
constant FUNC1_ADER_1 : integer := FUNC7_ADER_0 - 25;
constant FUNC1_ADER_2 : integer := FUNC7_ADER_0 - 26;
constant FUNC1_ADER_3 : integer := FUNC7_ADER_0 - 27;
constant FUNC0_ADER_0 : integer := FUNC7_ADER_0 - 28;
constant FUNC0_ADER_1 : integer := FUNC7_ADER_0 - 29;
constant FUNC0_ADER_2 : integer := FUNC7_ADER_0 - 30;
constant FUNC0_ADER_3 : integer := FUNC7_ADER_0 - 31;
constant IRQ_Vector : integer := FUNC0_ADER_3 -1;
constant IRQ_level : integer := FUNC0_ADER_3 -2;
constant TIME0_ns : integer := FUNC0_ADER_3 -5;
constant TIME1_ns : integer := FUNC0_ADER_3 -6;
constant TIME2_ns : integer := FUNC0_ADER_3 -7;
constant TIME3_ns : integer := FUNC0_ADER_3 -8;
constant TIME4_ns : integer := FUNC0_ADER_3 -9;
constant BYTES0 : integer := FUNC0_ADER_3 -10;
constant BYTES1 : integer := FUNC0_ADER_3 -11;
constant MBLT_Endian : integer := FUNC0_ADER_3 -4;
-- Initialization CR:
constant BEG_USER_CR : integer := 1;
constant END_USER_CR : integer := 2;
constant BEG_CRAM : integer := 3;
constant END_CRAM : integer := 4;
constant BEG_USER_CSR : integer := 5;
constant END_USER_CSR : integer := 6;
constant FUNC_AMCAP : integer := 7;
constant FUNC_XAMCAP : integer := 8;
constant FUNC_ADEM : integer := 9;
constant c_CRinitAddr : t_cr_add_table(BEG_USER_CR to FUNC_ADEM) := (
BEG_USER_CR => (add => 16#020#, len => 3),
END_USER_CR => (add => 16#023#, len => 3),
BEG_CRAM => (add => 16#26#, len => 3),
END_CRAM => (add => 16#29#, len => 3),
BEG_USER_CSR => (add => 16#02C#, len => 3),
END_USER_CSR => (add => 16#02F#, len => 3),
FUNC_AMCAP => (add => 16#048#, len => 64),
FUNC_XAMCAP => (add => 16#088#, len => 256),
FUNC_ADEM => (add => 16#188#, len => 32));
-- Main Finite State machine signals defoult:
constant c_FSM_default : t_FSM :=(
s_memReq => '0',
s_decode => '0',
s_dtackOE => '0',
s_mainDTACK => '1',
s_dataDir => '0',
s_dataOE => '0',
s_addrDir => '0', -- during IACK cycle the ADDR lines are input
s_addrOE => '0',
s_DSlatch => '0',
s_incrementAddr => '0',
s_dataPhase => '0',
s_dataToOutput => '0',
s_dataToAddrBus => '0',
s_transferActive => '0',
s_2eLatchAddr => "00",
s_retry => '0',
s_berr => '0',
s_BERR_out => '0'
);
-- CSR address:
constant c_BAR_addr : unsigned(19 downto 0) := x"7FFFF"; -- VME64x defined CSR
constant c_BIT_SET_REG_addr : unsigned(19 downto 0) := x"7FFFB";
constant c_BIT_CLR_REG_addr : unsigned(19 downto 0) := x"7FFF7";
constant c_CRAM_OWNER_addr : unsigned(19 downto 0) := x"7FFF3";
constant c_USR_BIT_SET_REG_addr : unsigned(19 downto 0) := x"7FFEF";
constant c_USR_BIT_CLR_REG_addr : unsigned(19 downto 0) := x"7FFEB";
constant c_FUNC7_ADER_0_addr : unsigned(19 downto 0) := x"7FFDF";
constant c_FUNC7_ADER_1_addr : unsigned(19 downto 0) := x"7FFDB";
constant c_FUNC7_ADER_2_addr : unsigned(19 downto 0) := x"7FFD7";
constant c_FUNC7_ADER_3_addr : unsigned(19 downto 0) := x"7FFD3";
constant c_FUNC6_ADER_0_addr : unsigned(19 downto 0) := x"7FFCF";
constant c_FUNC6_ADER_1_addr : unsigned(19 downto 0) := x"7FFCB";
constant c_FUNC6_ADER_2_addr : unsigned(19 downto 0) := x"7FFC7";
constant c_FUNC6_ADER_3_addr : unsigned(19 downto 0) := x"7FFC3";
constant c_FUNC5_ADER_0_addr : unsigned(19 downto 0) := x"7FFBF";
constant c_FUNC5_ADER_1_addr : unsigned(19 downto 0) := x"7FFBB";
constant c_FUNC5_ADER_2_addr : unsigned(19 downto 0) := x"7FFB7";
constant c_FUNC5_ADER_3_addr : unsigned(19 downto 0) := x"7FFB3";
constant c_FUNC4_ADER_0_addr : unsigned(19 downto 0) := x"7FFAF";
constant c_FUNC4_ADER_1_addr : unsigned(19 downto 0) := x"7FFAB";
constant c_FUNC4_ADER_2_addr : unsigned(19 downto 0) := x"7FFA7";
constant c_FUNC4_ADER_3_addr : unsigned(19 downto 0) := x"7FFA3";
constant c_FUNC3_ADER_0_addr : unsigned(19 downto 0) := x"7FF9F";
constant c_FUNC3_ADER_1_addr : unsigned(19 downto 0) := x"7FF9B";
constant c_FUNC3_ADER_2_addr : unsigned(19 downto 0) := x"7FF97";
constant c_FUNC3_ADER_3_addr : unsigned(19 downto 0) := x"7FF93";
constant c_FUNC2_ADER_0_addr : unsigned(19 downto 0) := x"7FF8F";
constant c_FUNC2_ADER_1_addr : unsigned(19 downto 0) := x"7FF8B";
constant c_FUNC2_ADER_2_addr : unsigned(19 downto 0) := x"7FF87";
constant c_FUNC2_ADER_3_addr : unsigned(19 downto 0) := x"7FF83";
constant c_FUNC1_ADER_0_addr : unsigned(19 downto 0) := x"7FF7F";
constant c_FUNC1_ADER_1_addr : unsigned(19 downto 0) := x"7FF7B";
constant c_FUNC1_ADER_2_addr : unsigned(19 downto 0) := x"7FF77";
constant c_FUNC1_ADER_3_addr : unsigned(19 downto 0) := x"7FF73";
constant c_FUNC0_ADER_0_addr : unsigned(19 downto 0) := x"7FF6F";
constant c_FUNC0_ADER_1_addr : unsigned(19 downto 0) := x"7FF6B";
constant c_FUNC0_ADER_2_addr : unsigned(19 downto 0) := x"7FF67";
constant c_FUNC0_ADER_3_addr : unsigned(19 downto 0) := x"7FF63"; -- VME64x defined CSR
constant c_IRQ_Vector_addr : unsigned(19 downto 0) := x"7FF5F"; -- VME64x reserved CSR
constant c_IRQ_level_addr : unsigned(19 downto 0) := x"7FF5B"; -- VME64x reserved CSR
constant c_TIME0_ns_addr : unsigned(19 downto 0) := x"7FF4f"; -- VME64x reserved CSR
constant c_TIME1_ns_addr : unsigned(19 downto 0) := x"7FF4b";
constant c_TIME2_ns_addr : unsigned(19 downto 0) := x"7FF47";
constant c_TIME3_ns_addr : unsigned(19 downto 0) := x"7FF43";
constant c_TIME4_ns_addr : unsigned(19 downto 0) := x"7FF3f";
constant c_BYTES0_addr : unsigned(19 downto 0) := x"7FF3b";
constant c_BYTES1_addr : unsigned(19 downto 0) := x"7FF37";
constant c_MBLT_Endian_addr : unsigned(19 downto 0) := x"7FF53"; -- VME64x reserved CSR
--___________________________________________________________________________________________
-- TYPE:
type t_typeOfDataTransfer is ( D08_0,
D08_1,
D08_2,
D08_3,
D16_01,
D16_23,
D32,
D64,
TypeError
);
type t_addressingType is ( A24,
A24_BLT,
A24_MBLT,
CR_CSR,
A16,
A32,
A32_BLT,
A32_MBLT,
A64,
A64_BLT,
A64_MBLT,
TWOedge,
AM_Error
);
type t_transferType is ( SINGLE,
BLT,
MBLT,
TWOe,
error
);
type t_XAMtype is ( A32_2eVME,
A64_2eVME,
A32_2eSST,
A64_2eSST,
A32_2eSSTb,
A64_2eSSTb,
XAM_error
);
type t_2eType is ( TWOe_VME,
TWOe_SST
);
type t_mainFSMstates is ( IDLE,
DECODE_ACCESS,
WAIT_FOR_DS,
LATCH_DS,
CHECK_TRANSFER_TYPE,
MEMORY_REQ,
DATA_TO_BUS,
DTACK_LOW,
DECIDE_NEXT_CYCLE,
INCREMENT_ADDR,
SET_DATA_PHASE
-- uncomment for using 2e modes:
-- WAIT_FOR_DS_2e,
-- ADDR_PHASE_1,
-- ADDR_PHASE_2,
-- ADDR_PHASE_3,
-- DECODE_ACCESS_2e,
-- DTACK_PHASE_1,
-- DTACK_PHASE_2,
-- DTACK_PHASE_3,
-- TWOeVME_WRITE,
-- TWOeVME_READ,
-- TWOeVME_MREQ_RD,
-- WAIT_WR_1,
-- WAIT_WR_2,
-- WAIT_WB_ACK_WR,
-- WAIT_WB_ACK_RD,
-- TWOeVME_TOGGLE_WR,
-- TWOeVME_TOGGLE_RD,
-- TWOe_FIFO_WRITE,
-- TWOe_TOGGLE_DTACK,
-- TWOeVME_INCR_ADDR,
-- TWOe_WAIT_FOR_DS1,
-- TWOe_FIFO_WAIT_READ,
-- TWOe_FIFO_READ,
-- TWOe_CHECK_BEAT,
-- TWOe_RELEASE_DTACK,
-- TWOe_END_1,
-- TWOe_END_2
);
type t_initState is ( IDLE,
SET_ADDR,
GET_DATA,
END_INIT
);
type t_FUNC_32b_array is array (0 to 7) of unsigned(31 downto 0); -- ADER register array
type t_FUNC_64b_array is array (0 to 7) of unsigned(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array is array (0 to 7) of unsigned(255 downto 0); -- XAMCAP register array
type t_FUNC_32b_array_std is array (0 to 7) of std_logic_vector(31 downto 0); -- ADER register array
type t_FUNC_64b_array_std is array (0 to 7) of std_logic_vector(63 downto 0); -- AMCAP register array
type t_FUNC_256b_array_std is array (0 to 7) of std_logic_vector(255 downto 0); -- XAMCAP register array
type t_CSRarray is array(BAR downto BYTES1) of unsigned(7 downto 0);
type t_cr_array is array (natural range <>) of std_logic_vector(7 downto 0);
--_____________________________________________________________________________________________________
--COMPONENTS:
COMPONENT VME_bus
PORT(
clk_i : in std_logic;
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_b_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_GA_i : in std_logic_vector(5 downto 0);
VME_ADDR_b_i : in std_logic_vector(31 downto 1);
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_BBSY_n_i : in std_logic;
VME_IACK_n_i : in std_logic;
memAckWB_i : in std_logic;
wbData_i : in std_logic_vector(63 downto 0);
err_i : in std_logic;
rty_i : in std_logic;
stall_i : in std_logic;
CRAMdata_i : in std_logic_vector(7 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
CSRData_i : in std_logic_vector(7 downto 0);
reset_flag_i : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
ModuleEnable : in std_logic;
MBLT_Endian_i : in std_logic_vector(2 downto 0);
Sw_Reset : in std_logic;
BAR_i : in std_logic_vector(4 downto 0);
transfer_done_i : in std_logic;
reset_o : out std_logic;
VME_LWORD_n_b_o : out std_logic;
VME_RETRY_n_o : out std_logic;
VME_RETRY_OE_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_BERR_o : out std_logic;
VME_ADDR_b_o : out std_logic_vector(31 downto 1);
VME_ADDR_DIR_o : out std_logic;
VME_ADDR_OE_N_o : out std_logic;
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
memReq_o : out std_logic;
wbData_o : out std_logic_vector(63 downto 0);
locAddr_o : out std_logic_vector(63 downto 0);
wbSel_o : out std_logic_vector(7 downto 0);
RW_o : out std_logic;
cyc_o : out std_logic;
psize_o : out std_logic_vector(8 downto 0);
VMEtoWB : out std_logic;
WBtoVME : out std_logic;
FifoMux : out std_logic;
CRAMaddr_o : out std_logic_vector(18 downto 0);
CRAMdata_o : out std_logic_vector(7 downto 0);
CRAMwea_o : out std_logic;
CRaddr_o : out std_logic_vector(11 downto 0);
VME_GA_oversampled_o : out std_logic_vector(5 downto 0);
en_wr_CSR : out std_logic;
CrCsrOffsetAddr : out std_logic_vector(18 downto 0);
CSRData_o : out std_logic_vector(7 downto 0);
err_flag_o : out std_logic;
numBytes : out std_logic_vector(12 downto 0);
transfTime : out std_logic_vector(39 downto 0);
leds : out std_logic_vector(7 downto 0);
transfer_done_o : out std_logic
);
END COMPONENT;
COMPONENT VME_Access_Decode
PORT (
clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
s_decode : in std_logic;
ModuleEnable : in std_logic;
InitInProgress : in std_logic;
Addr : in std_logic_vector(63 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
BAR : in std_logic_vector(4 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Funct_Sel : out std_logic_vector(7 downto 0);
Base_Addr : out std_logic_vector(63 downto 0);
Confaccess : out std_logic;
CardSel : out std_logic
);
END COMPONENT;
COMPONENT VME_Funct_Match
PORT(
clk_i : in std_logic;
s_reset : in std_logic;
s_decode : in std_logic;
s_mainFSMreset : in std_logic;
Addr : in std_logic_vector(63 downto 0);
AddrWidth : in std_logic_vector(1 downto 0);
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
Adem0 : in std_logic_vector(31 downto 0);
Adem1 : in std_logic_vector(31 downto 0);
Adem2 : in std_logic_vector(31 downto 0);
Adem3 : in std_logic_vector(31 downto 0);
Adem4 : in std_logic_vector(31 downto 0);
Adem5 : in std_logic_vector(31 downto 0);
Adem6 : in std_logic_vector(31 downto 0);
Adem7 : in std_logic_vector(31 downto 0);
FunctMatch : out std_logic_vector(7 downto 0);
DFS_o : out std_logic_vector(7 downto 0);
Nx_Base_Addr : out std_logic_vector(63 downto 0)
);
END COMPONENT;
COMPONENT VME_CR_CSR_Space
PORT(
clk_i : in std_logic;
s_reset : in std_logic;
CR_addr : in std_logic_vector(11 downto 0);
CRAM_addr : in std_logic_vector(18 downto 0);
CRAM_data_i : in std_logic_vector(7 downto 0);
CRAM_Wen : in std_logic;
en_wr_CSR : in std_logic;
CrCsrOffsetAddr : in std_logic_vector(18 downto 0);
VME_GA_oversampled : in std_logic_vector(5 downto 0);
locDataIn : in std_logic_vector(7 downto 0);
s_err_flag : in std_logic;
CR_data : out std_logic_vector(7 downto 0);
CRAM_data_o : out std_logic_vector(7 downto 0);
s_reset_flag : out std_logic;
CSRdata : out std_logic_vector(7 downto 0);
Ader0 : out std_logic_vector(31 downto 0);
Ader1 : out std_logic_vector(31 downto 0);
Ader2 : out std_logic_vector(31 downto 0);
Ader3 : out std_logic_vector(31 downto 0);
Ader4 : out std_logic_vector(31 downto 0);
Ader5 : out std_logic_vector(31 downto 0);
Ader6 : out std_logic_vector(31 downto 0);
Ader7 : out std_logic_vector(31 downto 0);
ModuleEnable : out std_logic;
Sw_Reset : out std_logic;
numBytes : in std_logic_vector(12 downto 0);
transfTime : in std_logic_vector(39 downto 0);
MBLT_Endian_o : out std_logic_vector(2 downto 0);
BAR_o : out std_logic_vector(4 downto 0);
INT_Level : out std_logic_vector(7 downto 0);
INT_Vector : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT VME_Am_Match
PORT(
clk_i : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
Ader0 : in std_logic_vector(31 downto 0);
Ader1 : in std_logic_vector(31 downto 0);
Ader2 : in std_logic_vector(31 downto 0);
Ader3 : in std_logic_vector(31 downto 0);
Ader4 : in std_logic_vector(31 downto 0);
Ader5 : in std_logic_vector(31 downto 0);
Ader6 : in std_logic_vector(31 downto 0);
Ader7 : in std_logic_vector(31 downto 0);
AmCap0 : in std_logic_vector(63 downto 0);
AmCap1 : in std_logic_vector(63 downto 0);
AmCap2 : in std_logic_vector(63 downto 0);
AmCap3 : in std_logic_vector(63 downto 0);
AmCap4 : in std_logic_vector(63 downto 0);
AmCap5 : in std_logic_vector(63 downto 0);
AmCap6 : in std_logic_vector(63 downto 0);
AmCap7 : in std_logic_vector(63 downto 0);
XAmCap0 : in std_logic_vector(255 downto 0);
XAmCap1 : in std_logic_vector(255 downto 0);
XAmCap2 : in std_logic_vector(255 downto 0);
XAmCap3 : in std_logic_vector(255 downto 0);
XAmCap4 : in std_logic_vector(255 downto 0);
XAmCap5 : in std_logic_vector(255 downto 0);
XAmCap6 : in std_logic_vector(255 downto 0);
XAmCap7 : in std_logic_vector(255 downto 0);
Am : in std_logic_vector(5 downto 0);
XAm : in std_logic_vector(7 downto 0);
DFS_i : in std_logic_vector(7 downto 0);
s_decode : in std_logic;
AmMatch : out std_logic_vector(7 downto 0)
);
END COMPONENT;
COMPONENT VME_Wb_master
PORT(
s_memReq : in std_logic;
clk_i : in std_logic;
s_cardSel : in std_logic;
s_reset : in std_logic;
s_mainFSMreset : in std_logic;
s_BERRcondition : in std_logic;
s_sel : in std_logic_vector(7 downto 0);
s_beatCount : in std_logic_vector(8 downto 0);
s_locDataInSwap : in std_logic_vector(63 downto 0);
s_rel_locAddr : in std_logic_vector(63 downto 0);
s_RW : in std_logic;
stall_i : in std_logic;
rty_i : in std_logic;
err_i : in std_logic;
wbData_i : in std_logic_vector(63 downto 0);
memAckWB_i : in std_logic;
s_locDataOut : out std_logic_vector(63 downto 0);
s_AckWithError : out std_logic;
memAckWb : out std_logic;
err : out std_logic;
rty : out std_logic;
psize_o : out std_logic_vector(8 downto 0);
cyc_o : out std_logic;
memReq_o : out std_logic;
WBdata_o : out std_logic_vector(63 downto 0);
locAddr_o : out std_logic_vector(63 downto 0);
WbSel_o : out std_logic_vector(7 downto 0);
RW_o : out std_logic
);
END COMPONENT;
COMPONENT VME_Init
PORT(
clk_i : in std_logic;
CRAddr : in std_logic_vector(18 downto 0);
CRdata_i : in std_logic_vector(7 downto 0);
RSTedge : inout std_logic;
InitReadCount : out std_logic_vector(8 downto 0);
InitInProgress : out std_logic;
BEG_USR_CR_o : out std_logic_vector(23 downto 0);
END_USR_CR_o : out std_logic_vector(23 downto 0);
BEG_USR_CSR_o : out std_logic_vector(23 downto 0);
END_USR_CSR_o : out std_logic_vector(23 downto 0);
BEG_CRAM_o : out std_logic_vector(23 downto 0);
END_CRAM_o : out std_logic_vector(23 downto 0);
FUNC0_ADEM_o : out std_logic_vector(31 downto 0);
FUNC1_ADEM_o : out std_logic_vector(31 downto 0);
FUNC2_ADEM_o : out std_logic_vector(31 downto 0);
FUNC3_ADEM_o : out std_logic_vector(31 downto 0);
FUNC4_ADEM_o : out std_logic_vector(31 downto 0);
FUNC5_ADEM_o : out std_logic_vector(31 downto 0);
FUNC6_ADEM_o : out std_logic_vector(31 downto 0);
FUNC7_ADEM_o : out std_logic_vector(31 downto 0);
FUNC0_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC1_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC2_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC3_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC4_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC5_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC6_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC7_AMCAP_o : out std_logic_vector(63 downto 0);
FUNC0_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC1_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC2_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC3_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC4_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC5_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC6_XAMCAP_o : out std_logic_vector(255 downto 0);
FUNC7_XAMCAP_o : out std_logic_vector(255 downto 0)
);
END COMPONENT;
COMPONENT VME_swapper
PORT(
d_i : in std_logic_vector(63 downto 0);
sel : in std_logic_vector(2 downto 0);
d_o : out std_logic_vector(63 downto 0)
);
END COMPONENT;
component FlipFlopD is
port (
reset,enable,sig_i,clk_i : in std_logic;
sig_o : out std_logic := '0'
);
end component;
component EdgeDetection is
port (
sig_i,clk_i : in std_logic;
sigEdge_o : out std_logic := '0'
);
end component;
component FallingEdgeDetection is
port (
sig_i, clk_i : in std_logic;
FallEdge_o : out std_logic);
end component;
component RisEdgeDetection is
port (
sig_i, clk_i : in std_logic;
RisEdge_o : out std_logic);
end component;
component DoubleSigInputSample is
port (
sig_i, clk_i : in std_logic;
sig_o : out std_logic);
end component;
component SigInputSample is
port (
sig_i, clk_i : in std_logic;
sig_o : out std_logic);
end component;
component DoubleRegInputSample is
generic(
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component;
component RegInputSample is
generic(
width : natural := 8
);
port (
reg_i : in std_logic_vector(width-1 downto 0);
reg_o : out std_logic_vector(width-1 downto 0) := (others => '0');
clk_i : in std_logic
);
end component;
COMPONENT VME_IRQ_Controller
PORT(
clk_i : in std_logic;
reset : in std_logic;
VME_IACKIN_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_AS1_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
VME_LWORD_n_i : in std_logic;
VME_ADDR_123 : in std_logic_vector(2 downto 0);
INT_Level : in std_logic_vector(7 downto 0);
INT_Vector : in std_logic_vector(7 downto 0);
INT_Req : in std_logic;
VME_IRQ_n_o : out std_logic_vector(6 downto 0);
VME_IACKOUT_n_o : out std_logic;
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_o : out std_logic_vector(31 downto 0);
DataDir : out std_logic
);
END COMPONENT;
COMPONENT dpblockram
generic (dl : integer := 8; -- Length of the data word
al : integer := 19; -- Size of the addr map (10 = 1024 words)
nw : integer := 2**19); -- Number of words
PORT(
clk : in std_logic;
we : in std_logic;
aw : in std_logic_vector(al - 1 downto 0);
ar : in std_logic_vector(al - 1 downto 0);
di : in std_logic_vector(dl - 1 downto 0);
dw : out std_logic_vector(dl - 1 downto 0);
do : out std_logic_vector(dl - 1 downto 0)
);
END COMPONENT;
end vme64x_pack;
package body vme64x_pack is
end vme64x_pack;
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