Commit f1fcd338 authored by Dimitris Lampridis's avatar Dimitris Lampridis

Silence Xilinx unisim warnings at 0ps during simulations regarding invalid OPMODE in DSP48A1

parent e03cb487
......@@ -85,6 +85,11 @@ module urv_mult18x18
/// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
// synthesis translate_off
initial force D1.OPMODE_dly = 8'd1;
// synthesis translate_on
endmodule // urv_mult18x18
`endif // `ifdef PLATFORM_SPARTAN6
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