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Last edited by Javier Serrano May 13, 2019
Page history

The uRV core

Project description

The uRV (Micro RISC-V) is a small footprint 32-bit RISC-V processor core intended for embedded real-time applications. uRV is targeted primarily for use as a soft CPU core in FPGAs.

Features

  • Supports RV32IM instruction set. Division and multiply high instructions are optional and can be emulated to lower the FPGA footprint.
  • Target: FPGAs.
  • 4-stage pipeline (FDXW).
  • All instructions except taken branches/division in one clock cycle.
  • Code execution from internal memory block.
  • Wishbone bus (version B.4) for peripheral access.
  • Simple interrupt handling.
  • Verilog RTL code.

Under development:

  • JTAG/Debug unit.
  • Compressed ISA (RV32IMC) extension as it matures.
  • Caches (Wishbone B.4 and AXI4 memory I/F).

Project information

  • Developing Distributed Hard-Real Time Software Systems Using FPGAs and Soft Cores, T. Wlostowski et al., 2016

Contacts

  • Tomasz Włostowski (CERN)

Status

Date Event
19-05-2015 First version.
06-08-2015 CoreMark® works.
13-05-2015 Created the urv-core project on OHWR.org.

13 September 2016

Files

  • logo.png
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  • Documents
  • Getting started
  • Home
  • Lhc instability trigger
  • Documents
    • Orconf 2015 presentation
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