Silence Xilinx unisim warnings at 0ps during simulations regarding invalid OPMODE in DSP48A1

f1fcd338 · Dimitris Lampridis · e03cb487 · f1fcd338
Commit f1fcd338 authored Mar 09, 2018 by Dimitris Lampridis
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urv_multiply.v rtl/urv_multiply.v +5 -0

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--- a/rtl/urv_multiply.v
+++ b/rtl/urv_multiply.v
@@ -85,6 +85,11 @@ module urv_mult18x18
 		   .RSTP(1'b0)
 		   );

+   /// Silence Xilinx unisim DSP48A1 warnings about invalid OPMODE
+   // synthesis translate_off
+   initial force D1.OPMODE_dly = 8'd1;
+   // synthesis translate_on
+
 endmodule // urv_mult18x18
 `endif //  `ifdef PLATFORM_SPARTAN6