Fix svec_base_regs.cheby to allow cheby to generate map in the rest
format.
Signed-off-by: Adam Wujek <dev_public@wujek.eu>

Resolve "Review vaibhav changes"

Closes #6

See merge request be-cem-edl/fec/hardware-modules/svec!4

Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

1- Header-files and Module.symvers from fpga-mgr-backport project should
   only be used for the FEC-OS based on 3.10.0-957.1.3.rt56.913.el7.x86_64
   CentOS kernel.

2- Module.symvers from fmc-sw project were included twice. Thus giving
   warning for duplication.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

For FPGA re-programming, debugfs was used. For this purpose, the
corresponding function was making use of 'device_schedule_callback()'
which was removed in linux-v3.15 at commit:
	33ac1257ff0dee2e9c7f009b1c1914b7990217b2 ("sysfs, driver-core:
	remove unused {sysfs|device}_schedule_callback_owner()")

The similar and better functionality is provided by an sysfs-API
'device_remove_file_self()'. Thus, convert this procedure from debugfs to
sysfs.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

The return type of 'debugfs_create_regset32()' was changed to 'void'
in linux-v5.6 at commit:
	ae91c92565494a37c30ce9a691c87890f800d826 ("debugfs: remove return
	value of debugfs_create_regset32()")
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Variable name 'LINUX' is very ambiguous for its purpose in the makefile.
Also, this project builds as a part of COHT project which uses another
variable name 'KERNELSRC' for the same purpose. Hence, this change makes
this project uniform with others.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Resolve "Add CI support"

Closes #3

See merge request be-cem-edl/fec/hardware-modules/svec!3

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Resolve "Document the CSR registers"

Closes #1

See merge request be-cem-edl/fec/hardware-modules/svec!2

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Resolve "s/SPEC/SVEC -- doc/index.rst"

Closes #2

See merge request be-cem-edl/fec/hardware-modules/svec!1

This documentation is for SVEC project. By mistake it was mentioned as
SPEC.
Signed-off-by: Vaibhav Gupta <vaibhav.gupta@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

this goes together with general-cores release v1.1.2
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

2.0.3 - 2021-03-22
==================
Fixed
-----
- sw: fix SVEC flasher size

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Being stabic is no excuse for not looking twice, David :D.
Reported-by: Rene Geissler <R.Geissler@gsi.de>

Reported-by: Rene Geissler <R.Geissler@gsi.de>

2.0.2 - 2021-03-16
==================
Changed
-------
- sw: better version validation implementation

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

The code was checking for the exact match MAJ.MIN, but what we want
is:

REAL CMP EXPECTED
---- --- --------
MAJ  ==   MAJ
MIN  >=   MIN
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

2.0.1 - 2021-02-08
==================
Added
-----
- sw: dynamically set the compatibility version between software and
FPGA
- sw: added the possibility to ignore the version check

Changed
-------
- hdl: the DMA interface changed to support BLT and MBLT acquisitions

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

The memory map of the svec base is therefore changed.