relicense

Signed-off-by: Federico Vaga <federico.vaga@cern.ch>

relicense
Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
c8734a37 · Federico Vaga · 22b5ca88 · c8734a37 · c8734a37 · c8734a37
Commit c8734a37 authored Nov 09, 2022 by Federico Vaga
79 changed files
--- a/.gitignore
+++ b/.gitignore
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+
 *.o
 *.ko
 *.mod.c

--- a/.gitmodules
+++ b/.gitmodules
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: LGPL-2.1-or-later
+
 [submodule "hdl/ip_cores/general-cores"]
 	path = hdl/ip_cores/general-cores
 	url = https://ohwr.org/project/general-cores.git

--- a/CHANGELOG.rst
+++ b/CHANGELOG.rst
+.. SPDX-FileCopyrightText: 2022 CERN (home.cern)
+..
+.. SPDX-License-Identifier: CC-BY-SA-4.0+
+
 ==========
 Change Log
 ==========

--- a/LICENSES/CC-BY-SA-4.0.txt
+++ b/LICENSES/CC-BY-SA-4.0.txt
--- a/LICENSES/CERN-OHL-W-2.0.txt
+++ b/LICENSES/CERN-OHL-W-2.0.txt
--- a/LICENCES/GPL-2.0.txt
+++ b/LICENCES/GPL-2.0.txt
--- a/LICENSES/GPL-2.0.txt
+++ b/LICENSES/GPL-2.0.txt
--- a/LICENSES/LGPL-2.1-or-later.txt
+++ b/LICENSES/LGPL-2.1-or-later.txt
--- a/README.rst
+++ b/README.rst
+.. SPDX-FileCopyrightText: 2022 CERN (home.cern)
+..
+.. SPDX-License-Identifier: CC-BY-SA-4.0+
+
 =============================
 Simple VME FMC Carrier - SVEC
 =============================

--- a/doc/Makefile
+++ b/doc/Makefile
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC-BY-SA-4.0+
+
 # Minimal makefile for Sphinx documentation
 #


--- a/doc/conf.py
+++ b/doc/conf.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CC-BY-SA-4.0+
+
 # -*- coding: utf-8 -*-
 #
 # Configuration file for the Sphinx documentation builder.

--- a/hdl/platform/Manifest.py
+++ b/hdl/platform/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files =["chipscope_icon.ngc",  "chipscope_ila.ngc" ]
--- a/hdl/rtl/.gitignore
+++ b/hdl/rtl/.gitignore
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 sourceid_svec_base_pkg.vhd
--- a/hdl/rtl/Manifest.py
+++ b/hdl/rtl/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = [
    "svec_base_regs.vhd",
    "svec_base_wr.vhd",

--- a/hdl/rtl/bootloader/Manifest.py
+++ b/hdl/rtl/bootloader/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = [ "flash_boot.vhd",
          "m25p_flash.vhd",
          "mini_vme.vhd",

--- a/hdl/rtl/bootloader/flash_boot.vhd
+++ b/hdl/rtl/bootloader/flash_boot.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -----------------------------------------------------------------------------
 -- Title      : Flash-to-Xilinx FPGA bitstream loader
 -- Project    : Simple VME64x FMC Carrier (SVEC)
@@ -6,7 +10,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-01-24
-- Last update: 2014-01-15
+-- Last update: 2022-11-09
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -15,26 +19,6 @@
 -- resides at a fixed location (defined in svec_bootloader_pkg) and the flash
 -- is assumed to be formatted with SDB filesystem.
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/hdl/rtl/bootloader/m25p_flash.vhd
+++ b/hdl/rtl/bootloader/m25p_flash.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -----------------------------------------------------------------------------
 -- Title      : M25Pxxx Flash Controller
 -- Project    : Simple VME64x FMC Carrier (SVEC)
@@ -6,7 +10,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2013-01-24
-- Last update: 2013-01-25
+-- Last update: 2022-11-09
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -15,26 +19,6 @@
 -- can execute any kind of operations, and a simple memory bus which can only read
 -- blocks of bytes starting at a given address.
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/hdl/rtl/bootloader/mini_vme.vhd
+++ b/hdl/rtl/bootloader/mini_vme.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -------------------------------------------------------------------------------
 -- Title      : Minimalistic VME64x Core
 -- Project    : Simple VME64x FMC Carrier (SVEC)
@@ -6,7 +10,7 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2012-01-20
-- Last update: 2014-01-13
+-- Last update: 2022-11-09
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
@@ -14,26 +18,6 @@
 -- accesses to a range of addresses specified in g_user_csr_start/end. Matching
 -- transactions are executed through a Wishbone master.
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------


 library ieee;

--- a/hdl/rtl/bootloader/sfpga_bootloader.vhd
+++ b/hdl/rtl/bootloader/sfpga_bootloader.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -------------------------------------------------------------------------------
 -- Title        : SVEC Bootloader Core
 -- Project      : Simple VME64x FMC Carrier (SVEC)
@@ -17,26 +21,6 @@
 -- - provides raw access to the Flash SPI controller from the host (for
 --   in-system reprogramming of the Flash)
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

 library ieee;
 use ieee.STD_LOGIC_1164.all;

--- a/hdl/rtl/bootloader/svec_bootloader_pkg.vhd
+++ b/hdl/rtl/bootloader/svec_bootloader_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -------------------------------------------------------------------------------
 -- Title      : SVEC FPGA Bootloader main package
 -- Project    : Simple VME64x FMC Carrier (SVEC)
@@ -6,33 +10,13 @@
 -- Author     : Tomasz Wlostowski
 -- Company    : CERN
 -- Created    : 2011-01-24
-- Last update: 2014-01-13
+-- Last update: 2022-11-09
 -- Platform   : FPGA-generic
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Contains definitions of the bootloader's parameters (base
 -- addresses and timing).
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------


 library ieee;

--- a/hdl/rtl/bootloader/svec_xloader_wb.vhd
+++ b/hdl/rtl/bootloader/svec_xloader_wb.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for SVEC FPGA loader
 ---------------------------------------------------------------------------------------

--- a/hdl/rtl/bootloader/sxldr_registers_pkg.vhd
+++ b/hdl/rtl/bootloader/sxldr_registers_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for SVEC FPGA loader
 ---------------------------------------------------------------------------------------

--- a/hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
+++ b/hdl/rtl/bootloader/sxldr_wbgen2_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for SVEC FPGA loader
 ---------------------------------------------------------------------------------------

--- a/hdl/rtl/bootloader/xilinx_loader.vhd
+++ b/hdl/rtl/bootloader/xilinx_loader.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -------------------------------------------------------------------------------
 -- Title        : Xilinx FPGA Loader
 -- Project      : Simple VME64x FMC Carrier (SVEC)
@@ -15,26 +19,6 @@
 -- bitstream loader from general-cores library. Does not have Wishbone interface,
 -- but it is driven direclty by the flash booting FSM.
 -------------------------------------------------------------------------------
--
-- Copyright (c) 2012 - 2013 CERN
--
-- This source file is free software; you can redistribute it   
-- and/or modify it under the terms of the GNU Lesser General   
-- Public License as published by the Free Software Foundation; 
-- either version 2.1 of the License, or (at your option) any   
-- later version.                                               
--
-- This source is distributed in the hope that it will be       
-- useful, but WITHOUT ANY WARRANTY; without even the implied   
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      
-- PURPOSE.  See the GNU Lesser General Public License for more 
-- details.                                                     
--
-- You should have received a copy of the GNU Lesser General    
-- Public License along with this source; if not, download it   
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------

 library ieee;
 use ieee.STD_LOGIC_1164.all;

--- a/hdl/rtl/golden/Manifest.py
+++ b/hdl/rtl/golden/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = ["golden_core.vhd", "golden_wbgen2_pkg.vhd", "golden_wb.vhd", "golden_core_pkg.vhd"];
--- a/hdl/rtl/golden/golden_core.vhd
+++ b/hdl/rtl/golden/golden_core.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 library ieee;
 use ieee.STD_LOGIC_1164.all;
 use ieee.numeric_std.all;

--- a/hdl/rtl/golden/golden_core_pkg.vhd
+++ b/hdl/rtl/golden/golden_core_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 library ieee;
 use ieee.STD_LOGIC_1164.all;


--- a/hdl/rtl/golden/golden_wb.vhd
+++ b/hdl/rtl/golden/golden_wb.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for Golden Bitstream WB Slave
 ---------------------------------------------------------------------------------------

--- a/hdl/rtl/golden/golden_wbgen2_pkg.vhd
+++ b/hdl/rtl/golden/golden_wbgen2_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for Golden Bitstream WB Slave
 ---------------------------------------------------------------------------------------

--- a/hdl/rtl/svec_base_regs.cheby
+++ b/hdl/rtl/svec_base_regs.cheby
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 memory-map:
  name: svec_base_regs
  bus: wb-32-be

--- a/hdl/rtl/svec_base_regs.vhd
+++ b/hdl/rtl/svec_base_regs.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 -- Do not edit.  Generated on Fri Jan 29 13:36:51 2021 by tgingold
 -- With Cheby 1.4.dev0 and these options:
 --  --gen-hdl=svec_base_regs.vhd -i svec_base_regs.cheby

--- a/hdl/rtl/svec_base_wr.vhd
+++ b/hdl/rtl/svec_base_wr.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 -- CERN BE-CO-HT
 -- SVEC
@@ -9,18 +13,6 @@
 -- description: SVEC carrier base, with WR.
 --
 --------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------

 library ieee;
 use ieee.std_logic_1164.all;

--- a/hdl/sim/ddr_test/Manifest.py
+++ b/hdl/sim/ddr_test/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 target = "xilinx"
 action = "simulation"


--- a/hdl/sim/ddr_test/sim_models/2048Mb_ddr3/Manifest.py
+++ b/hdl/sim/ddr_test/sim_models/2048Mb_ddr3/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = ["ddr3.v"]

 vlog_opt = "+incdir+sim_models/2048Mb_ddr3 +define+sg15E +define+x16"
--- a/hdl/sim/ddr_test/testbench/Manifest.py
+++ b/hdl/sim/ddr_test/testbench/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = [ "VME64x_Package.vhd",
          "VME64x_SIM_Package.vhd",
          "vme64x_ddr_tb.vhd" ]
--- a/hdl/sim/ddr_test/testbench/VME64x_Package.vhd
+++ b/hdl/sim/ddr_test/testbench/VME64x_Package.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+

 --------------------------------------------------------------------------------------
 ---------------------------VME64x_Package-----------------------------------------

--- a/hdl/sim/ddr_test/testbench/VME64x_SIM_Package.vhd
+++ b/hdl/sim/ddr_test/testbench/VME64x_SIM_Package.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+

 --------------------------------------------------------------------------------------
 ---------------------------VME64x_SIM_Package-----------------------------------------

--- a/hdl/sim/ddr_test/testbench/VME64x_TB.vhd
+++ b/hdl/sim/ddr_test/testbench/VME64x_TB.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
 --------------------------------------------------------------------------------



--- a/hdl/sim/ddr_test/testbench/vme64x_ddr_tb.vhd
+++ b/hdl/sim/ddr_test/testbench/vme64x_ddr_tb.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------



--- a/hdl/syn/common/Manifest.py
+++ b/hdl/syn/common/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 # User should define the variable svec_base_ucf

 files = [ "svec_base_common.ucf" ]

--- a/hdl/syn/golden/Manifest.py
+++ b/hdl/syn/golden/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 target = "xilinx"
 action = "synthesis"


--- a/hdl/syn/golden_wr/Manifest.py
+++ b/hdl/syn/golden_wr/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 target = "xilinx"
 action = "synthesis"


--- a/hdl/syn/sfpga_bootloader/Manifest.py
+++ b/hdl/syn/sfpga_bootloader/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 target = "xilinx"
 action = "synthesis"


--- a/hdl/testbench/golden/Manifest.py
+++ b/hdl/testbench/golden/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 action = "simulation"
 target = "xilinx"
 fetchto = "../../ip_cores"

--- a/hdl/testbench/sfpga_bootloader/Manifest.py
+++ b/hdl/testbench/sfpga_bootloader/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 action = "simulation"
 target = "xilinx"
 fetchto = "../../ip_cores"

--- a/hdl/testbench/template/Manifest.py
+++ b/hdl/testbench/template/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 action = "simulation"
 target = "xilinx"
 sim_tool = "modelsim"

--- a/hdl/top/bicolor_led_test/Manifest.py
+++ b/hdl/top/bicolor_led_test/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = ["bicolor_led_ctrl_pkg.vhd",
         "bicolor_led_ctrl.vhd",
         "wb_addr_decoder.vhd",

--- a/hdl/top/bicolor_led_test/bicolor_led_ctrl.vhd
+++ b/hdl/top/bicolor_led_test/bicolor_led_ctrl.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
 -- Bi-color LED controller
@@ -39,18 +43,6 @@
 -- dependencies:
 --
 --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
 -- last changes: see log.
 --------------------------------------------------------------------------------
 -- TODO: - 

--- a/hdl/top/bicolor_led_test/bicolor_led_ctrl_pkg.vhd
+++ b/hdl/top/bicolor_led_test/bicolor_led_ctrl_pkg.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
 -- Bi-color LED controller package
@@ -17,18 +21,6 @@
 -- dependencies:
 --
 --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
 -- last changes: see log.
 --------------------------------------------------------------------------------
 -- TODO: - 

--- a/hdl/top/bicolor_led_test/sim/bicolor_led_ctrl_tb.vhd
+++ b/hdl/top/bicolor_led_test/sim/bicolor_led_ctrl_tb.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
 -- Bi-color LED controller testbench
@@ -17,18 +21,6 @@
 -- dependencies:
 --
 --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
 -- last changes: see log.
 --------------------------------------------------------------------------------
 -- TODO: - 

--- a/hdl/top/ddr_test/Manifest.py
+++ b/hdl/top/ddr_test/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)
+#
+# SPDX-License-Identifier: CERN-OHL-W-2.0
+
 files = [ "svec_afpga_top.vhd",
          "svec_v1_afpga.ucf",
          "csr.vhd",

--- a/hdl/top/ddr_test/csr.vhd
+++ b/hdl/top/ddr_test/csr.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 ---------------------------------------------------------------------------------------
 -- Title          : Wishbone slave core for Control and status registers
 ---------------------------------------------------------------------------------------

--- a/hdl/top/ddr_test/svec_afpga_top.vhd
+++ b/hdl/top/ddr_test/svec_afpga_top.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 -- CERN (BE-CO-HT)
 -- Top level entity for Simple VME FMC Carrier (SVEC) Application FPGA
@@ -18,18 +22,6 @@
 -- dependencies:
 --
 --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
 -- last changes: see log.
 --------------------------------------------------------------------------------
 -- TODO: - 

--- a/hdl/top/ddr_test/wb_addr_decoder.vhd
+++ b/hdl/top/ddr_test/wb_addr_decoder.vhd
+-- SPDX-FileCopyrightText: 2022 CERN (home.cern)
+--
+-- SPDX-License-Identifier: CERN-OHL-W-2.0+
+
 --------------------------------------------------------------------------------
 --                                                                            --
 -- CERN BE-CO-HT         GN4124 core for PCIe FMC carrier                     --
@@ -18,19 +22,7 @@
 -- dependencies:
 --
 --------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--------------------------------------------------------------------------------
-- This source file is free software; you can redistribute it and/or modify it
-- under the terms of the GNU Lesser General Public License as published by the
-- Free Software Foundation; either version 2.1 of the License, or (at your
-- option) any later version. This source is distributed in the hope that it
-- will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty
-- of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
-- See the GNU Lesser General Public License for more details. You should have
-- received a copy of the GNU Lesser General Public License along with this
-- source; if not, download it from http://www.gnu.org/licenses/lgpl-2.1.html
--------------------------------------------------------------------------------
-- last changes: 
+-- last changes:
 --------------------------------------------------------------------------------
 -- TODO: 
 --------------------------------------------------------------------------------

--- a/hdl/top/golden/Manifest.py
+++ b/hdl/top/golden/Manifest.py
+# SPDX-FileCopyrightText: 2022 CERN (home.cern)