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Simple VME FMC Carrier SVEC
Commit 46bd7e78 authored by Tristan Gingold's avatar Tristan Gingold
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Rename template -> base

parent 3da89c5c
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Showing with 628 additions and 33 deletions
hdl/rtl/Manifest.py
View file @ 46bd7e78
files = [ files = [
"svec_template_regs.vhd", "svec_base_regs.vhd",
"svec_template_wr.vhd", "svec_base_wr.vhd",
] ]
hdl/rtl/svec_template_regs.cheby → hdl/rtl/svec_base_regs.cheby
View file @ 46bd7e78
memory-map: memory-map:
name: svec_template_regs name: svec_base_regs
bus: wb-32-be bus: wb-32-be
size: 0x2000 size: 0x2000
children: children:
......
hdl/rtl/svec_template_wr.vhd → hdl/rtl/svec_base_wr.vhd
View file @ 46bd7e78
...@@ -4,9 +4,9 @@ ...@@ -4,9 +4,9 @@
-- https://ohwr.org/projects/svec -- https://ohwr.org/projects/svec
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- --
-- unit name: svec_template_wr -- unit name: svec_base_wr
-- --
-- description: SVEC carrier template, with WR. -- description: SVEC carrier base, with WR.
-- --
-------------------------------------------------------------------------------- --------------------------------------------------------------------------------
-- Copyright CERN 2019 -- Copyright CERN 2019
...@@ -40,7 +40,7 @@ use work.streamers_pkg.all; ...@@ -40,7 +40,7 @@ use work.streamers_pkg.all;
library unisim; library unisim;
use unisim.vcomponents.all; use unisim.vcomponents.all;
entity svec_template_wr is entity svec_base_wr is
generic ( generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA. -- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True; g_WITH_VIC : boolean := True;
...@@ -324,9 +324,9 @@ entity svec_template_wr is ...@@ -324,9 +324,9 @@ entity svec_template_wr is
app_wb_o : out t_wishbone_master_out; app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in app_wb_i : in t_wishbone_master_in
); );
end entity svec_template_wr; end entity svec_base_wr;
architecture top of svec_template_wr is architecture top of svec_base_wr is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock -- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := ( constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3), 0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
...@@ -531,7 +531,7 @@ begin -- architecture top ...@@ -531,7 +531,7 @@ begin -- architecture top
master_o (1) => app_wb_o master_o (1) => app_wb_o
); );
inst_carrier: entity work.svec_template_regs inst_carrier: entity work.svec_base_regs
port map ( port map (
rst_n_i => rst_sys_62m5_n, rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5, clk_i => clk_sys_62m5,
......
hdl/syn/common/Manifest.py
View file @ 46bd7e78
# User should define the variable svec_template_ucf # User should define the variable svec_base_ucf
files = [ "svec_template_common.ucf" ] files = [ "svec_base_common.ucf" ]
ucf_dict = { ucf_dict = {
'ddr4': "svec_template_ddr4.ucf", 'ddr4': "svec_base_ddr4.ucf",
'ddr5': "svec_template_ddr5.ucf", 'ddr5': "svec_base_ddr5.ucf",
'wr': "svec_template_wr.ucf", 'wr': "svec_base_wr.ucf",
'led': "svec_template_led.ucf", 'led': "svec_base_led.ucf",
'gpio': "svec_template_gpio.ucf", 'gpio': "svec_base_gpio.ucf",
} }
for p in svec_template_ucf: for p in svec_base_ucf:
f = ucf_dict.get(p, None) f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'svec_template_ucf'".format(p) assert f is not None, "unknown name {} in 'svec_base_ucf'".format(p)
if p == 'ddr4' or p == 'ddr5': if p == 'ddr4' or p == 'ddr5':
files.append('svec_template_ddr_common.ucf') files.append('svec_base_ddr_common.ucf')
files.append(f) files.append(f)
hdl/syn/common/svec_template_common.ucf → hdl/syn/common/svec_base_common.ucf
View file @ 46bd7e78
...@@ -219,7 +219,7 @@ TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%; ...@@ -219,7 +219,7 @@ TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "*/gc_reset_async_in" TIG; NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller # Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst; NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#---------------------------------------- #----------------------------------------
...@@ -228,8 +228,8 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; ...@@ -228,8 +228,8 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Declaration of domains # Declaration of domains
NET "inst_svec_template/clk_sys_62m5" TNM_NET = sys_clk; NET "inst_svec_base/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_svec_template/clk_ref_125m" TNM_NET = ref_clk; NET "inst_svec_base/clk_ref_125m" TNM_NET = ref_clk;
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk"; TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk"; TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
......
hdl/syn/common/svec_template_ddr_common.ucf → hdl/syn/common/svec_base_ddr_common.ucf
View file @ 46bd7e78
...@@ -4,27 +4,27 @@ ...@@ -4,27 +4,27 @@
# These are suggested by the Xilinx-generated MCB. # These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core. # More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG; NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG; NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG; NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG; #NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#---------------------------------------- #----------------------------------------
# Asynchronous resets # Asynchronous resets
#---------------------------------------- #----------------------------------------
# Ignore async reset to DDR controller # Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst; NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG; TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#---------------------------------------- #----------------------------------------
# Cross-clock domain sync # Cross-clock domain sync
#---------------------------------------- #----------------------------------------
NET "inst_svec_template/clk_ddr_333m" TNM_NET = ddr_clk; NET "inst_svec_base/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk; NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk; NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules # DDR does not use any sync modules
......
hdl/syn/common/svec_template_wr.ucf → hdl/syn/common/svec_base_wr.ucf
View file @ 46bd7e78
...@@ -80,7 +80,7 @@ NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo"; ...@@ -80,7 +80,7 @@ NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%; TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk; NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%; TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
...@@ -100,8 +100,8 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY; ...@@ -100,8 +100,8 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
# Declaration of domains # Declaration of domains
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd; NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk; NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
# Exceptions for crossings via gc_sync_ffs # Exceptions for crossings via gc_sync_ffs
......
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