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Simple VME FMC Carrier SVEC
Commit 46bd7e78 authored by Tristan Gingold's avatar Tristan Gingold
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Rename template -> base

parent 3da89c5c
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Showing with 628 additions and 33 deletions
hdl/rtl/Manifest.py
View file @ 46bd7e78
files = [
"svec_template_regs.vhd",
"svec_template_wr.vhd",
"svec_base_regs.vhd",
"svec_base_wr.vhd",
]
hdl/rtl/svec_template_regs.cheby → hdl/rtl/svec_base_regs.cheby
View file @ 46bd7e78
memory-map:
name: svec_template_regs
name: svec_base_regs
bus: wb-32-be
size: 0x2000
children:
......
hdl/rtl/svec_template_regs.vhd → hdl/rtl/svec_base_regs.vhd
View file @ 46bd7e78
-- Do not edit; this file was generated by Cheby using these options:
-- --gen-hdl=svec_template_regs.vhd -i svec_template_regs.cheby
-- --gen-hdl=svec_base_regs.vhd -i svec_base_regs.cheby
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.wishbone_pkg.all;
entity svec_template_regs is
entity svec_base_regs is
port (
rst_n_i : in std_logic;
clk_i : in std_logic;
......@@ -82,11 +82,11 @@ entity svec_template_regs is
wrc_regs_i : in t_wishbone_master_in;
wrc_regs_o : out t_wishbone_master_out
);
end svec_template_regs;
end svec_base_regs;
architecture syn of svec_template_regs is
signal rd_int : std_logic;
signal wr_int : std_logic;
architecture syn of svec_base_regs is
signal rd_req_int : std_logic;
signal wr_req_int : std_logic;
signal rd_ack_int : std_logic;
signal wr_ack_int : std_logic;
signal wb_en : std_logic;
......@@ -97,25 +97,37 @@ architecture syn of svec_template_regs is
signal metadata_re : std_logic;
signal csr_resets_global_reg : std_logic;
signal csr_resets_appl_reg : std_logic;
signal csr_resets_wreq : std_logic;
signal csr_resets_wack : std_logic;
signal csr_resets_rint : std_logic_vector(31 downto 0);
signal csr_unused0_rint : std_logic_vector(31 downto 0);
signal csr_ddr_status_rint : std_logic_vector(31 downto 0);
signal csr_pcb_rev_rint : std_logic_vector(31 downto 0);
signal csr_ddr4_addr_wreq : std_logic;
signal csr_ddr4_data_wreq : std_logic;
signal therm_id_re : std_logic;
signal therm_id_we : std_logic;
signal therm_id_wt : std_logic;
signal therm_id_rt : std_logic;
signal therm_id_tr : std_logic;
signal therm_id_wack : std_logic;
signal therm_id_rack : std_logic;
signal fmc_i2c_re : std_logic;
signal fmc_i2c_we : std_logic;
signal fmc_i2c_wt : std_logic;
signal fmc_i2c_rt : std_logic;
signal fmc_i2c_tr : std_logic;
signal fmc_i2c_wack : std_logic;
signal fmc_i2c_rack : std_logic;
signal flash_spi_re : std_logic;
signal flash_spi_we : std_logic;
signal flash_spi_wt : std_logic;
signal flash_spi_rt : std_logic;
signal flash_spi_tr : std_logic;
signal flash_spi_wack : std_logic;
signal flash_spi_rack : std_logic;
signal vic_re : std_logic;
signal vic_we : std_logic;
signal vic_wt : std_logic;
signal vic_rt : std_logic;
signal vic_tr : std_logic;
......@@ -124,35 +136,43 @@ architecture syn of svec_template_regs is
signal buildinfo_rack : std_logic;
signal buildinfo_re : std_logic;
signal wrc_regs_re : std_logic;
signal wrc_regs_we : std_logic;
signal wrc_regs_wt : std_logic;
signal wrc_regs_rt : std_logic;
signal wrc_regs_tr : std_logic;
signal wrc_regs_wack : std_logic;
signal wrc_regs_rack : std_logic;
signal reg_rdat_int : std_logic_vector(31 downto 0);
signal rd_ack1_int : std_logic;
signal rd_ack_d0 : std_logic;
signal rd_dat_d0 : std_logic_vector(31 downto 0);
signal wr_req_d0 : std_logic;
signal wr_adr_d0 : std_logic_vector(12 downto 2);
signal wr_dat_d0 : std_logic_vector(31 downto 0);
begin
-- WB decode signals
wb_en <= wb_cyc_i and wb_stb_i;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_rip <= '0';
elsif rising_edge(clk_i) then
wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_rip <= '0';
else
wb_rip <= (wb_rip or (wb_en and not wb_we_i)) and not rd_ack_int;
end if;
end if;
end process;
rd_int <= (wb_en and not wb_we_i) and not wb_rip;
rd_req_int <= (wb_en and not wb_we_i) and not wb_rip;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wb_wip <= '0';
elsif rising_edge(clk_i) then
wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wb_wip <= '0';
else
wb_wip <= (wb_wip or (wb_en and wb_we_i)) and not wr_ack_int;
end if;
end if;
end process;
wr_int <= (wb_en and wb_we_i) and not wb_wip;
wr_req_int <= (wb_en and wb_we_i) and not wb_wip;
ack_int <= rd_ack_int or wr_ack_int;
wb_ack_o <= ack_int;
......@@ -160,26 +180,90 @@ begin
wb_rty_o <= '0';
wb_err_o <= '0';
-- Assign outputs
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
metadata_rack <= '0';
elsif rising_edge(clk_i) then
metadata_rack <= metadata_re and not metadata_rack;
-- pipelining for wr-in+rd-out
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
rd_ack_int <= '0';
wr_req_d0 <= '0';
else
rd_ack_int <= rd_ack_d0;
wb_dat_o <= rd_dat_d0;
wr_req_d0 <= wr_req_int;
wr_adr_d0 <= wb_adr_i;
wr_dat_d0 <= wb_dat_i;
end if;
end if;
end process;
metadata_data_o <= wb_dat_i;
metadata_addr_o <= wb_adr_i(5 downto 2);
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
metadata_rack <= '0';
else
metadata_rack <= metadata_re and not metadata_rack;
end if;
end if;
end process;
metadata_data_o <= wr_dat_d0;
metadata_addr_o <= wr_adr_d0(5 downto 2);
-- Register csr_app_offset
-- Register csr_resets
csr_resets_global_o <= csr_resets_global_reg;
csr_resets_appl_o <= csr_resets_appl_reg;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
csr_resets_wack <= '0';
else
if csr_resets_wreq = '1' then
csr_resets_global_reg <= wr_dat_d0(0);
csr_resets_appl_reg <= wr_dat_d0(1);
end if;
csr_resets_wack <= csr_resets_wreq;
end if;
end if;
end process;
csr_resets_rint(0) <= csr_resets_global_reg;
csr_resets_rint(1) <= csr_resets_appl_reg;
csr_resets_rint(31 downto 2) <= (others => '0');
-- Register csr_fmc_presence
-- Register csr_unused0
csr_unused0_rint(31 downto 0) <= "00000000000000000000000000000000";
-- Register csr_ddr_status
csr_ddr_status_rint(0) <= csr_ddr_status_ddr4_calib_done_i;
csr_ddr_status_rint(1) <= csr_ddr_status_ddr5_calib_done_i;
csr_ddr_status_rint(31 downto 2) <= (others => '0');
-- Register csr_pcb_rev
csr_pcb_rev_rint(4 downto 0) <= csr_pcb_rev_rev_i;
csr_pcb_rev_rint(31 downto 5) <= (others => '0');
-- Register csr_ddr4_addr
csr_ddr4_addr_o <= wr_dat_d0;
csr_ddr4_addr_wr_o <= csr_ddr4_addr_wreq;
-- Register csr_ddr4_data
csr_ddr4_data_o <= wr_dat_d0;
csr_ddr4_data_wr_o <= csr_ddr4_data_wreq;
-- Assignments for submap therm_id
therm_id_tr <= therm_id_wt or therm_id_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
therm_id_rt <= '0';
elsif rising_edge(clk_i) then
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
therm_id_rt <= '0';
therm_id_wt <= '0';
else
therm_id_rt <= (therm_id_rt or therm_id_re) and not therm_id_rack;
therm_id_wt <= (therm_id_wt or therm_id_we) and not therm_id_wack;
end if;
end if;
end process;
therm_id_o.cyc <= therm_id_tr;
......@@ -189,15 +273,19 @@ begin
therm_id_o.adr <= ((27 downto 0 => '0') & wb_adr_i(3 downto 2)) & (1 downto 0 => '0');
therm_id_o.sel <= (others => '1');
therm_id_o.we <= therm_id_wt;
therm_id_o.dat <= wb_dat_i;
therm_id_o.dat <= wr_dat_d0;
-- Assignments for submap fmc_i2c
fmc_i2c_tr <= fmc_i2c_wt or fmc_i2c_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
elsif rising_edge(clk_i) then
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
fmc_i2c_rt <= '0';
fmc_i2c_wt <= '0';
else
fmc_i2c_rt <= (fmc_i2c_rt or fmc_i2c_re) and not fmc_i2c_rack;
fmc_i2c_wt <= (fmc_i2c_wt or fmc_i2c_we) and not fmc_i2c_wack;
end if;
end if;
end process;
fmc_i2c_o.cyc <= fmc_i2c_tr;
......@@ -207,15 +295,19 @@ begin
fmc_i2c_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
fmc_i2c_o.sel <= (others => '1');
fmc_i2c_o.we <= fmc_i2c_wt;
fmc_i2c_o.dat <= wb_dat_i;
fmc_i2c_o.dat <= wr_dat_d0;
-- Assignments for submap flash_spi
flash_spi_tr <= flash_spi_wt or flash_spi_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
flash_spi_rt <= '0';
elsif rising_edge(clk_i) then
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
flash_spi_rt <= '0';
flash_spi_wt <= '0';
else
flash_spi_rt <= (flash_spi_rt or flash_spi_re) and not flash_spi_rack;
flash_spi_wt <= (flash_spi_wt or flash_spi_we) and not flash_spi_wack;
end if;
end if;
end process;
flash_spi_o.cyc <= flash_spi_tr;
......@@ -225,15 +317,19 @@ begin
flash_spi_o.adr <= ((26 downto 0 => '0') & wb_adr_i(4 downto 2)) & (1 downto 0 => '0');
flash_spi_o.sel <= (others => '1');
flash_spi_o.we <= flash_spi_wt;
flash_spi_o.dat <= wb_dat_i;
flash_spi_o.dat <= wr_dat_d0;
-- Assignments for submap vic
vic_tr <= vic_wt or vic_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
vic_rt <= '0';
elsif rising_edge(clk_i) then
vic_rt <= (vic_rt or vic_re) and not vic_rack;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
vic_rt <= '0';
vic_wt <= '0';
else
vic_rt <= (vic_rt or vic_re) and not vic_rack;
vic_wt <= (vic_wt or vic_we) and not vic_wack;
end if;
end if;
end process;
vic_o.cyc <= vic_tr;
......@@ -243,24 +339,30 @@ begin
vic_o.adr <= ((23 downto 0 => '0') & wb_adr_i(7 downto 2)) & (1 downto 0 => '0');
vic_o.sel <= (others => '1');
vic_o.we <= vic_wt;
vic_o.dat <= wb_dat_i;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
buildinfo_rack <= '0';
elsif rising_edge(clk_i) then
buildinfo_rack <= buildinfo_re and not buildinfo_rack;
vic_o.dat <= wr_dat_d0;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
buildinfo_rack <= '0';
else
buildinfo_rack <= buildinfo_re and not buildinfo_rack;
end if;
end if;
end process;
buildinfo_data_o <= wb_dat_i;
buildinfo_addr_o <= wb_adr_i(7 downto 2);
buildinfo_data_o <= wr_dat_d0;
buildinfo_addr_o <= wr_adr_d0(7 downto 2);
-- Assignments for submap wrc_regs
wrc_regs_tr <= wrc_regs_wt or wrc_regs_rt;
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wrc_regs_rt <= '0';
elsif rising_edge(clk_i) then
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
process (clk_i) begin
if rising_edge(clk_i) then
if rst_n_i = '0' then
wrc_regs_rt <= '0';
wrc_regs_wt <= '0';
else
wrc_regs_rt <= (wrc_regs_rt or wrc_regs_re) and not wrc_regs_rack;
wrc_regs_wt <= (wrc_regs_wt or wrc_regs_we) and not wrc_regs_wack;
end if;
end if;
end process;
wrc_regs_o.cyc <= wrc_regs_tr;
......@@ -270,223 +372,117 @@ begin
wrc_regs_o.adr <= ((19 downto 0 => '0') & wb_adr_i(11 downto 2)) & (1 downto 0 => '0');
wrc_regs_o.sel <= (others => '1');
wrc_regs_o.we <= wrc_regs_wt;
wrc_regs_o.dat <= wb_dat_i;
wrc_regs_o.dat <= wr_dat_d0;
-- Process for write requests.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_resets_global_reg <= '0';
csr_resets_appl_reg <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
elsif rising_edge(clk_i) then
wr_ack_int <= '0';
metadata_wr_o <= '0';
csr_ddr4_addr_wr_o <= '0';
csr_ddr4_data_wr_o <= '0';
therm_id_wt <= '0';
fmc_i2c_wt <= '0';
flash_spi_wt <= '0';
vic_wt <= '0';
buildinfo_wr_o <= '0';
wrc_regs_wt <= '0';
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
process (wr_adr_d0, wr_req_d0, csr_resets_wack, csr_ddr4_data_wack_i, therm_id_wack, fmc_i2c_wack, flash_spi_wack, vic_wack, wrc_regs_wack) begin
metadata_wr_o <= '0';
csr_resets_wreq <= '0';
csr_ddr4_addr_wreq <= '0';
csr_ddr4_data_wreq <= '0';
therm_id_we <= '0';
fmc_i2c_we <= '0';
flash_spi_we <= '0';
vic_we <= '0';
buildinfo_wr_o <= '0';
wrc_regs_we <= '0';
case wr_adr_d0(12 downto 12) is
when "0" =>
case wr_adr_d0(11 downto 8) is
when "0000" =>
case wr_adr_d0(7 downto 6) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "01" =>
case wr_adr_d0(5 downto 4) is
when "00" =>
-- Submap metadata
metadata_wr_o <= wr_int;
wr_ack_int <= wr_int;
when "01" =>
case wb_adr_i(5 downto 4) is
case wr_adr_d0(3 downto 2) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_app_offset
when "01" =>
-- Register csr_resets
if wr_int = '1' then
csr_resets_global_reg <= wb_dat_i(0);
csr_resets_appl_reg <= wb_dat_i(1);
end if;
wr_ack_int <= wr_int;
when "10" =>
-- Register csr_fmc_presence
when "11" =>
-- Register csr_unused0
when others =>
wr_ack_int <= wr_int;
end case;
-- csr_app_offset
wr_ack_int <= wr_req_d0;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- Register csr_ddr_status
when "01" =>
-- Register csr_pcb_rev
when "10" =>
-- Register csr_ddr4_addr
csr_ddr4_addr_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_addr_o <= wb_dat_i;
end if;
wr_ack_int <= wr_int;
when "11" =>
-- Register csr_ddr4_data
csr_ddr4_data_wr_o <= wr_int;
if wr_int = '1' then
csr_ddr4_data_o <= wb_dat_i;
end if;
wr_ack_int <= csr_ddr4_data_wack_i;
when others =>
wr_ack_int <= wr_int;
end case;
-- csr_resets
csr_resets_wreq <= wr_req_d0;
wr_ack_int <= csr_resets_wack;
when "10" =>
-- csr_fmc_presence
wr_ack_int <= wr_req_d0;
when "11" =>
-- Submap therm_id
therm_id_wt <= (therm_id_wt or wr_int) and not therm_id_wack;
wr_ack_int <= therm_id_wack;
when others =>
wr_ack_int <= wr_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_wt <= (fmc_i2c_wt or wr_int) and not fmc_i2c_wack;
wr_ack_int <= fmc_i2c_wack;
when "1" =>
-- Submap flash_spi
flash_spi_wt <= (flash_spi_wt or wr_int) and not flash_spi_wack;
wr_ack_int <= flash_spi_wack;
-- csr_unused0
wr_ack_int <= wr_req_d0;
when others =>
wr_ack_int <= wr_int;
wr_ack_int <= wr_req_d0;
end case;
when others =>
wr_ack_int <= wr_int;
end case;
when "0001" =>
-- Submap vic
vic_wt <= (vic_wt or wr_int) and not vic_wack;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_int;
wr_ack_int <= wr_int;
when others =>
wr_ack_int <= wr_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_wt <= (wrc_regs_wt or wr_int) and not wrc_regs_wack;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_int;
end case;
end if;
end process;
-- Process for registers read.
process (clk_i, rst_n_i) begin
if rst_n_i = '0' then
rd_ack1_int <= '0';
reg_rdat_int <= (others => 'X');
csr_ddr4_data_rd_o <= '0';
elsif rising_edge(clk_i) then
csr_ddr4_data_rd_o <= '0';
reg_rdat_int <= (others => '0');
case wb_adr_i(12 downto 12) is
when "0" =>
case wb_adr_i(11 downto 8) is
when "0000" =>
case wb_adr_i(7 downto 6) is
when "00" =>
when "01" =>
case wb_adr_i(5 downto 4) is
case wr_adr_d0(3 downto 2) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
reg_rdat_int <= csr_app_offset_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_resets
reg_rdat_int(0) <= csr_resets_global_reg;
reg_rdat_int(1) <= csr_resets_appl_reg;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_fmc_presence
reg_rdat_int <= csr_fmc_presence_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_unused0
reg_rdat_int <= "00000000000000000000000000000000";
rd_ack1_int <= rd_int;
when others =>
rd_ack1_int <= rd_int;
end case;
-- csr_ddr_status
wr_ack_int <= wr_req_d0;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
reg_rdat_int(0) <= csr_ddr_status_ddr4_calib_done_i;
reg_rdat_int(1) <= csr_ddr_status_ddr5_calib_done_i;
rd_ack1_int <= rd_int;
when "01" =>
-- csr_pcb_rev
reg_rdat_int(4 downto 0) <= csr_pcb_rev_rev_i;
rd_ack1_int <= rd_int;
when "10" =>
-- csr_ddr4_addr
reg_rdat_int <= csr_ddr4_addr_i;
rd_ack1_int <= rd_int;
when "11" =>
-- csr_ddr4_data
reg_rdat_int <= csr_ddr4_data_i;
csr_ddr4_data_rd_o <= rd_int;
rd_ack1_int <= csr_ddr4_data_rack_i;
when others =>
rd_ack1_int <= rd_int;
end case;
-- csr_pcb_rev
wr_ack_int <= wr_req_d0;
when "10" =>
-- csr_ddr4_addr
csr_ddr4_addr_wreq <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when "11" =>
-- csr_ddr4_data
csr_ddr4_data_wreq <= wr_req_d0;
wr_ack_int <= csr_ddr4_data_wack_i;
when others =>
rd_ack1_int <= rd_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
when "1" =>
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
when "11" =>
-- Submap therm_id
therm_id_we <= wr_req_d0;
wr_ack_int <= therm_id_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
when "10" =>
case wr_adr_d0(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_we <= wr_req_d0;
wr_ack_int <= fmc_i2c_wack;
when "1" =>
-- Submap flash_spi
flash_spi_we <= wr_req_d0;
wr_ack_int <= flash_spi_wack;
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
when "0001" =>
when "0010" =>
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
when "1" =>
when "0001" =>
-- Submap vic
vic_we <= wr_req_d0;
wr_ack_int <= vic_wack;
when "0010" =>
-- Submap buildinfo
buildinfo_wr_o <= wr_req_d0;
wr_ack_int <= wr_req_d0;
when others =>
rd_ack1_int <= rd_int;
wr_ack_int <= wr_req_d0;
end case;
end if;
when "1" =>
-- Submap wrc_regs
wrc_regs_we <= wr_req_d0;
wr_ack_int <= wrc_regs_wack;
when others =>
wr_ack_int <= wr_req_d0;
end case;
end process;
-- Process for read requests.
process (wb_adr_i, reg_rdat_int, rd_ack1_int, rd_int, rd_int, metadata_data_i, metadata_rack, rd_int, therm_id_i.dat, therm_id_rack, therm_id_rt, rd_int, fmc_i2c_i.dat, fmc_i2c_rack, fmc_i2c_rt, rd_int, flash_spi_i.dat, flash_spi_rack, flash_spi_rt, rd_int, vic_i.dat, vic_rack, vic_rt, rd_int, buildinfo_data_i, buildinfo_rack, rd_int, wrc_regs_i.dat, wrc_regs_rack, wrc_regs_rt) begin
process (wb_adr_i, rd_req_int, rd_req_int, metadata_data_i, metadata_rack, csr_app_offset_i, csr_resets_rint, csr_fmc_presence_i, csr_unused0_rint, csr_ddr_status_rint, csr_pcb_rev_rint, csr_ddr4_addr_i, csr_ddr4_data_rack_i, csr_ddr4_data_i, therm_id_i.dat, therm_id_rack, fmc_i2c_i.dat, fmc_i2c_rack, flash_spi_i.dat, flash_spi_rack, vic_i.dat, vic_rack, rd_req_int, buildinfo_data_i, buildinfo_rack, wrc_regs_i.dat, wrc_regs_rack) begin
-- By default ack read requests
wb_dat_o <= (others => '0');
rd_dat_d0 <= (others => 'X');
metadata_re <= '0';
csr_ddr4_data_rd_o <= '0';
therm_id_re <= '0';
fmc_i2c_re <= '0';
flash_spi_re <= '0';
......@@ -500,99 +496,100 @@ begin
case wb_adr_i(7 downto 6) is
when "00" =>
-- Submap metadata
wb_dat_o <= metadata_data_i;
rd_ack_int <= metadata_rack;
metadata_re <= rd_int;
rd_dat_d0 <= metadata_data_i;
rd_ack_d0 <= metadata_rack;
metadata_re <= rd_req_int;
when "01" =>
case wb_adr_i(5 downto 4) is
when "00" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_app_offset
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_app_offset_i;
when "01" =>
-- csr_resets
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_resets_rint;
when "10" =>
-- csr_fmc_presence
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_fmc_presence_i;
when "11" =>
-- csr_unused0
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_unused0_rint;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "01" =>
case wb_adr_i(3 downto 2) is
when "00" =>
-- csr_ddr_status
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_ddr_status_rint;
when "01" =>
-- csr_pcb_rev
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_pcb_rev_rint;
when "10" =>
-- csr_ddr4_addr
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
rd_ack_d0 <= rd_req_int;
rd_dat_d0 <= csr_ddr4_addr_i;
when "11" =>
-- csr_ddr4_data
wb_dat_o <= reg_rdat_int;
rd_ack_int <= rd_ack1_int;
csr_ddr4_data_rd_o <= rd_req_int;
rd_ack_d0 <= csr_ddr4_data_rack_i;
rd_dat_d0 <= csr_ddr4_data_i;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "11" =>
-- Submap therm_id
therm_id_re <= rd_int;
wb_dat_o <= therm_id_i.dat;
rd_ack_int <= therm_id_rack;
therm_id_re <= rd_req_int;
rd_dat_d0 <= therm_id_i.dat;
rd_ack_d0 <= therm_id_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "10" =>
case wb_adr_i(5 downto 5) is
when "0" =>
-- Submap fmc_i2c
fmc_i2c_re <= rd_int;
wb_dat_o <= fmc_i2c_i.dat;
rd_ack_int <= fmc_i2c_rack;
fmc_i2c_re <= rd_req_int;
rd_dat_d0 <= fmc_i2c_i.dat;
rd_ack_d0 <= fmc_i2c_rack;
when "1" =>
-- Submap flash_spi
flash_spi_re <= rd_int;
wb_dat_o <= flash_spi_i.dat;
rd_ack_int <= flash_spi_rack;
flash_spi_re <= rd_req_int;
rd_dat_d0 <= flash_spi_i.dat;
rd_ack_d0 <= flash_spi_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "0001" =>
-- Submap vic
vic_re <= rd_int;
wb_dat_o <= vic_i.dat;
rd_ack_int <= vic_rack;
vic_re <= rd_req_int;
rd_dat_d0 <= vic_i.dat;
rd_ack_d0 <= vic_rack;
when "0010" =>
-- Submap buildinfo
wb_dat_o <= buildinfo_data_i;
rd_ack_int <= buildinfo_rack;
buildinfo_re <= rd_int;
rd_dat_d0 <= buildinfo_data_i;
rd_ack_d0 <= buildinfo_rack;
buildinfo_re <= rd_req_int;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
when "1" =>
-- Submap wrc_regs
wrc_regs_re <= rd_int;
wb_dat_o <= wrc_regs_i.dat;
rd_ack_int <= wrc_regs_rack;
wrc_regs_re <= rd_req_int;
rd_dat_d0 <= wrc_regs_i.dat;
rd_ack_d0 <= wrc_regs_rack;
when others =>
rd_ack_int <= rd_int;
rd_ack_d0 <= rd_req_int;
end case;
end process;
end syn;
hdl/rtl/svec_template_wr.vhd → hdl/rtl/svec_base_wr.vhd
View file @ 46bd7e78
......@@ -4,9 +4,9 @@
-- https://ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: svec_template_wr
-- unit name: svec_base_wr
--
-- description: SVEC carrier template, with WR.
-- description: SVEC carrier base, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
......@@ -40,7 +40,7 @@ use work.streamers_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec_template_wr is
entity svec_base_wr is
generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True;
......@@ -324,9 +324,9 @@ entity svec_template_wr is
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in
);
end entity svec_template_wr;
end entity svec_base_wr;
architecture top of svec_template_wr is
architecture top of svec_base_wr is
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
......@@ -531,7 +531,7 @@ begin -- architecture top
master_o (1) => app_wb_o
);
inst_carrier: entity work.svec_template_regs
inst_carrier: entity work.svec_base_regs
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
......
hdl/syn/common/Manifest.py
View file @ 46bd7e78
# User should define the variable svec_template_ucf
# User should define the variable svec_base_ucf
files = [ "svec_template_common.ucf" ]
files = [ "svec_base_common.ucf" ]
ucf_dict = {
'ddr4': "svec_template_ddr4.ucf",
'ddr5': "svec_template_ddr5.ucf",
'wr': "svec_template_wr.ucf",
'led': "svec_template_led.ucf",
'gpio': "svec_template_gpio.ucf",
'ddr4': "svec_base_ddr4.ucf",
'ddr5': "svec_base_ddr5.ucf",
'wr': "svec_base_wr.ucf",
'led': "svec_base_led.ucf",
'gpio': "svec_base_gpio.ucf",
}
for p in svec_template_ucf:
for p in svec_base_ucf:
f = ucf_dict.get(p, None)
assert f is not None, "unknown name {} in 'svec_template_ucf'".format(p)
assert f is not None, "unknown name {} in 'svec_base_ucf'".format(p)
if p == 'ddr4' or p == 'ddr5':
files.append('svec_template_ddr_common.ucf')
files.append('svec_base_ddr_common.ucf')
files.append(f)
hdl/syn/common/svec_template_common.ucf → hdl/syn/common/svec_base_common.ucf
View file @ 46bd7e78
......@@ -219,7 +219,7 @@ TIMESPEC TS_clk_125m_pllref = PERIOD "clk_125m_ref" 8 ns HIGH 50%;
NET "*/gc_reset_async_in" TIG;
# Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst;
NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
......@@ -228,8 +228,8 @@ TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
# Declaration of domains
NET "inst_svec_template/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_svec_template/clk_ref_125m" TNM_NET = ref_clk;
NET "inst_svec_base/clk_sys_62m5" TNM_NET = sys_clk;
NET "inst_svec_base/clk_ref_125m" TNM_NET = ref_clk;
TIMEGRP "ref_sync_ffs" = "sync_ffs" EXCEPT "ref_clk";
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_clk";
......
hdl/syn/common/svec_template_ddr_common.ucf → hdl/syn/common/svec_base_ddr_common.ucf
View file @ 46bd7e78
......@@ -4,27 +4,27 @@
# These are suggested by the Xilinx-generated MCB.
# More info in the UCF file found in the "user_design/par" of the generated core.
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/c?_pll_lock" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/selfrefresh_mcb_mode" TIG;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/DONE_SOFTANDHARD_CAL" TIG;
#NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/mcb_soft_calibration_inst/SELFREFRESH_MCB_REQ" TIG;
#----------------------------------------
# Asynchronous resets
#----------------------------------------
# Ignore async reset to DDR controller
NET "inst_svec_template/ddr_rst" TPTHRU = ddr_rst;
NET "inst_svec_base/ddr_rst" TPTHRU = ddr_rst;
TIMESPEC TS_ddr_rst_tig = FROM FFS THRU ddr_rst TIG;
#----------------------------------------
# Cross-clock domain sync
#----------------------------------------
NET "inst_svec_template/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_svec_base/clk_ddr_333m" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_svec_template/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_svec_base/gen_with_ddr?.cmp_ddr_ctrl_bank/*/memc?_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# DDR does not use any sync modules
......
hdl/syn/common/svec_template_wr.ucf → hdl/syn/common/svec_base_wr.ucf
View file @ 46bd7e78
......@@ -80,7 +80,7 @@ NET "clk_20m_vcxo_i" TNM_NET = "clk_20m_vcxo";
TIMESPEC TS_clk_20m_vcxo = PERIOD "clk_20m_vcxo" 50 ns HIGH 50%;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/cmp_xwrc_platform/gen_phy_spartan6.cmp_gtp/ch1_gtp_clkout_int<1>" TNM_NET = wrc_gtp_clk;
TIMESPEC TS_wrc_gtp_clk = PERIOD "wrc_gtp_clk" 8 ns HIGH 50%;
......@@ -100,8 +100,8 @@ TIMESPEC TS_dmtd_skew = FROM "skew_limit" TO "FFS" 1.25 ns DATAPATHONLY;
# Declaration of domains
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "inst_svec_template/gen_wr.cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/clk_pll_dmtd" TNM_NET = clk_dmtd;
NET "inst_svec_base/gen_wr.cmp_xwrc_board_svec/phy8_to_wrc_rx_clk" TNM_NET = phy_clk;
# Exceptions for crossings via gc_sync_ffs
......
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