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Simple VME FMC Carrier SVEC
Commit 29b98259 authored by Tomasz Wlostowski's avatar Tomasz Wlostowski
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bridge testing

parent 90348ce2
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.gitmodules
View file @ 29b98259
......@@ -4,3 +4,6 @@
[submodule "hdl/ip_cores/vme64x-core"]
path = hdl/ip_cores/vme64x-core
url = https://ohwr.org/project/vme64x-core.git
[submodule "hdl/ip_cores/wr-cores"]
path = hdl/ip_cores/wr-cores
url = https://ohwr.org/project/wr-cores.git
general-cores @ 90b33ae3
Subproject commit 5dde6da558083312cfd98d721e14b36a03e2a0bc
Subproject commit 90b33ae38bd152f9e4f665602e4e033f47f221b4
vme64x-core @ 6f359655
Subproject commit 1204aeca29ec3c72b6fa615976f000c664c7d152
Subproject commit 6f359655ae8e9f1cab3f85d673f430b80692ed7b
wr-cores @ 4482c478
Subproject commit 4482c478f29185f81dd45312f4f1ae2f28494957
hdl/rtl/bootloader/mini_vme.vhd
View file @ 29b98259
......@@ -6,7 +6,7 @@
-- Author : Tomasz Wlostowski
-- Company : CERN
-- Created : 2012-01-20
-- Last update: 2014-01-13
-- Last update: 2019-11-22
-- Platform : FPGA-generic
-- Standard : VHDL'93
-------------------------------------------------------------------------------
......@@ -42,6 +42,7 @@ use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.VME64x_pkg.all;
entity xmini_vme is
generic (
......@@ -52,27 +53,9 @@ entity xmini_vme is
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
-- Stripped-down VME bus.
VME_RST_n_i : in std_logic;
VME_AS_n_i : in std_logic;
VME_LWORD_n_i : in std_logic;
VME_WRITE_n_i : in std_logic;
VME_DS_n_i : in std_logic_vector(1 downto 0);
-- Geographical Address. Bit 5 is GA parity.
VME_GA_i : in std_logic_vector(5 downto 0);
VME_AM_i : in std_logic_vector(5 downto 0);
VME_ADDR_i : in std_logic_vector(31 downto 1);
-- Bidirectional/tristate driver signals: please put the tristates in the
-- top level entity of your design.
VME_DTACK_n_o : out std_logic;
VME_DTACK_OE_o : out std_logic;
VME_DATA_b_i : in std_logic_vector(31 downto 0);
VME_DATA_b_o : out std_logic_vector(31 downto 0);
VME_DATA_DIR_o : out std_logic;
VME_DATA_OE_N_o : out std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out;
-- Wishbone master
master_o : out t_wishbone_master_out;
master_i : in t_wishbone_master_in;
......@@ -116,11 +99,11 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_AS_n_i,
data_i => VME_i.as_n,
npulse_o => as_p1,
synced_o => as_synced);
ds_a <= VME_DS_n_i(0) and VME_DS_n_i(1);
ds_a <= VME_i.ds_n(0) and VME_i.ds_n(1);
U_Sync_DS : gc_sync_ffs
port map (
......@@ -134,7 +117,7 @@ begin -- rtl
port map (
clk_i => clk_sys_i,
rst_n_i => rst_n_i,
data_i => VME_WRITE_n_i,
data_i => VME_i.write_n,
synced_o => write_n);
......@@ -146,11 +129,11 @@ begin -- rtl
if(rst_n_i = '0') then
addr_valid <= '0';
elsif(as_p1 = '1') then
addr_latched <= VME_ADDR_i;
addr_latched <= VME_i.ADDR;
addr_valid <= '1';
am_latched <= VME_AM_i;
ga_latched <= VME_GA_i;
lword_latched <= VME_LWORD_n_i;
am_latched <= VME_i.AM;
ga_latched <= VME_i.GA;
lword_latched <= VME_i.LWORD_n;
elsif(as_synced = '1') then
addr_valid <= '0';
end if;
......@@ -163,8 +146,8 @@ begin -- rtl
if rst_n_i = '0' then
data_valid <= '0';
elsif(ds_p1 = '1') then
data_latched <= VME_DATA_b_i;
ds_latched <= VME_DS_n_i;
data_latched <= VME_i.DATA;
ds_latched <= vme_i.ds_n;
data_valid <= '1';
elsif(ds_synced = '1') then
data_valid <= '0';
......@@ -211,17 +194,17 @@ begin -- rtl
if rst_n_i = '0' then
state <= IDLE;
idle_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DATA_OE_N_o <= '0';
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '0';
VME_o.DATA_DIR <= '0';
VME_o.DATA_OE_N <= '0';
VME_o.DTACK_n <= '0';
VME_o.DTACK_OE <= '0';
else
case state is
when IDLE =>
idle_o <= '1';
VME_DATA_DIR_o <= '0';
VME_DTACK_n_o <= '1';
VME_DTACK_OE_o <= '0';
VME_o.DATA_DIR <= '0';
VME_o.DTACK_n <= '1';
VME_o.DTACK_OE <= '0';
dtack_counter <= (others => '0');
if(addr_valid = '1' and data_valid = '1') then
......@@ -265,11 +248,11 @@ begin -- rtl
end if;
when DTACK =>
VME_DATA_b_o <= readback_data;
VME_o.DATA <= readback_data;
VME_DTACK_n_o <= '0';
VME_DTACK_OE_o <= '1';
VME_DATA_DIR_o <= not is_write;
VME_o.DTACK_n <= '0';
VME_o.DTACK_OE <= '1';
VME_o.DATA_DIR <= not is_write;
dtack_counter <= dtack_counter + 1;
......
hdl/rtl/bootloader/sfpga_bootloader.vhd
View file @ 29b98259
......@@ -400,7 +400,7 @@ begin -- behavioral
wb_out.err <= '0';
wb_out.rty <= '0';
wb_out.stall <= '0';
wb_out.int <= '0';
-- wb_out.int <= '0';
regs_out <= regs_out_local or regs_out_flash;
U_WB_SLAVE : svec_xloader_wb
......
hdl/rtl/svec7a/Manifest.py 0 → 100644
View file @ 29b98259
files = [
"../svec_base_regs.vhd",
"svec7_base_wr.vhd",
"litedram_core.v"
]
hdl/rtl/svec7a/svec7_base_wr.vhd 0 → 100644
View file @ 29b98259
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SVEC
-- https://ohwr.org/projects/svec
--------------------------------------------------------------------------------
--
-- unit name: svec_base_wr
--
-- description: SVEC carrier base, with WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pkg.all;
use work.wr_xilinx_pkg.all;
use work.wr_board_pkg.all;
use work.wr_svec_pkg.all;
use work.buildinfo_pkg.all;
use work.wr_fabric_pkg.all;
use work.streamers_pkg.all;
use work.axi4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec7_base_wr is
generic (
-- If true, instantiate a VIC/ONEWIRE/SPI/WR/DDRAM+DMA.
g_WITH_VIC : boolean := True;
g_WITH_ONEWIRE : boolean := True;
g_WITH_SPI : boolean := True;
g_WITH_WR : boolean := False;
g_WITH_DDR : boolean := True;
-- Address of the application meta-data. 0 if none.
g_APP_OFFSET : std_logic_vector(31 downto 0) := x"0000_0000";
-- Number of user interrupts
g_NUM_USER_IRQ : natural := 1;
-- WR PTP firmware.
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy16.bram";
-- Number of aux clocks syntonized by WRPC to WR timebase
g_AUX_CLKS : integer := 0;
-- Fabric interface selection for WR Core:
-- plain = expose WRC fabric interface
-- streamers = attach WRC streamers to fabric interface
-- etherbone = attach Etherbone slave to fabric interface
g_FABRIC_IFACE : t_board_fabric_iface := plain;
-- parameters configuration when g_fabric_iface = "streamers" (otherwise ignored)
g_STREAMERS_OP_MODE : t_streamers_op_mode := TX_AND_RX;
g_TX_STREAMER_PARAMS : t_tx_streamer_params := c_TX_STREAMER_PARAMS_DEFAUT;
g_RX_STREAMER_PARAMS : t_rx_streamer_params := c_RX_STREAMER_PARAMS_DEFAUT;
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : integer := 0;
-- Increase information messages during simulation
g_VERBOSE : boolean := False;
g_DDR_CONTROLLER : string := "MIG"
);
port (
---------------------------------------------------------------------------
-- Clocks/resets
---------------------------------------------------------------------------
-- Reset from system fpga
rst_n_i : in std_logic;
-- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
-- 20MHz VCXO clock (for WR)
clk_20m_vcxo_i : in std_logic := '0';
-- 125 MHz GTP reference
clk_125m_gtp_p_i : in std_logic := '0';
clk_125m_gtp_n_i : in std_logic := '0';
-- Aux clocks, which can be disciplined by the WR Core
clk_aux_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
-- 10MHz ext ref clock input
clk_10m_ext_i : in std_logic := '0';
-- External PPS input
pps_ext_i : in std_logic := '0';
---------------------------------------------------------------------------
-- VME interface
---------------------------------------------------------------------------
vme_sysreset_n_i : in std_logic;
sfpga_clk_o : out std_logic;
sfpga_rst_n_o : out std_logic;
sfpga_frame_o : out std_logic;
sfpga_d_o : out std_logic_vector(7 downto 0);
sfpga_frame_i : in std_logic := '0';
sfpga_d_i : in std_logic_vector(7 downto 0) := x"00";
---------------------------------------------------------------------------
-- FMC interface
---------------------------------------------------------------------------
-- I2C interface for accessing FMC EEPROM.
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
fmc1_scl_b : inout std_logic;
fmc1_sda_b : inout std_logic;
-- Presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
fmc1_prsnt_m2c_n_i: in std_logic;
---------------------------------------------------------------------------
-- Carrier
---------------------------------------------------------------------------
-- Onewire interface
onewire_b : inout std_logic;
-- Carrier I2C eeprom
carrier_scl_b : inout std_logic;
carrier_sda_b : inout std_logic;
---------------------------------------------------------------------------
-- Flash memory SPI interface
---------------------------------------------------------------------------
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic := '1';
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll20dac_din_o : out std_logic;
pll20dac_sclk_o : out std_logic;
pll20dac_sync_n_o : out std_logic;
pll25dac_din_o : out std_logic;
pll25dac_sclk_o : out std_logic;
pll25dac_sync_n_o : out std_logic;
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic := '0';
sfp_rxn_i : in std_logic := '0';
sfp_mod_def0_i : in std_logic := '0'; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic := '0';
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic := '0';
------------------------------------------
-- DDR
------------------------------------------
ddr_a_o : out std_logic_vector(14 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(63 downto 0);
ddr_dqs_n_b : inout std_logic_vector(7 downto 0);
ddr_dqs_p_b : inout std_logic_vector(7 downto 0);
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_dm_o : out std_logic_vector(7 downto 0);
ddr_we_n_o : out std_logic;
ddr_cs_n_o : out std_logic;
-- PCB revision
pcbrev_i : in std_logic_vector(4 downto 0);
------------------------------------------
-- User part
------------------------------------------
-- Direct access to the DDR-3
-- Classic wishbone
ddr_clk_i : in std_logic := '0';
ddr_clk_o : out std_logic;
ddr_rst_n_i : in std_logic := '1';
ddr_axi4_i : in t_axi4_full_master_out_512;
ddr_axi4_o : out t_axi4_full_master_in_512;
-- Clocks and reset.
clk_sys_62m5_o : out std_logic;
rst_sys_62m5_n_o : out std_logic;
clk_ref_125m_o : out std_logic;
rst_ref_125m_n_o : out std_logic;
-- 125 MHz DDMTD clock output
clk_dmtd_125m_o : out std_logic;
-- Interrupts
irq_user_i : in std_logic_vector(g_NUM_USER_IRQ + 5 downto 6) := (others => '0');
-- WR fabric interface (when g_fabric_iface = "plain")
wrf_src_o : out t_wrf_source_out;
wrf_src_i : in t_wrf_source_in := c_DUMMY_SRC_IN;
wrf_snk_o : out t_wrf_sink_out;
wrf_snk_i : in t_wrf_sink_in := c_DUMMY_SNK_IN;
-- WR streamers (when g_fabric_iface = "streamers")
wrs_tx_data_i : in std_logic_vector(g_TX_STREAMER_PARAMS.DATA_WIDTH-1 downto 0) := (others => '0');
wrs_tx_valid_i : in std_logic := '0';
wrs_tx_dreq_o : out std_logic;
wrs_tx_last_i : in std_logic := '1';
wrs_tx_flush_i : in std_logic := '0';
wrs_tx_cfg_i : in t_tx_streamer_cfg := c_TX_STREAMER_CFG_DEFAULT;
wrs_rx_first_o : out std_logic;
wrs_rx_last_o : out std_logic;
wrs_rx_data_o : out std_logic_vector(g_rx_streamer_params.data_width-1 downto 0);
wrs_rx_valid_o : out std_logic;
wrs_rx_dreq_i : in std_logic := '0';
wrs_rx_cfg_i : in t_rx_streamer_cfg := c_RX_STREAMER_CFG_DEFAULT;
-- Etherbone WB master interface (when g_fabric_iface = "etherbone")
wb_eth_master_o : out t_wishbone_master_out;
wb_eth_master_i : in t_wishbone_master_in := cc_dummy_master_in;
-- Timecode I/F
tm_link_up_o : out std_logic;
tm_time_valid_o : out std_logic;
tm_tai_o : out std_logic_vector(39 downto 0);
tm_cycles_o : out std_logic_vector(27 downto 0);
-- Aux clocks control
tm_dac_value_o : out std_logic_vector(23 downto 0);
tm_dac_wr_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
tm_clk_aux_lock_en_i : in std_logic_vector(g_AUX_CLKS-1 downto 0) := (others => '0');
tm_clk_aux_locked_o : out std_logic_vector(g_AUX_CLKS-1 downto 0);
-- PPS output
pps_p_o : out std_logic;
pps_led_o : out std_logic;
-- Link ok indication
link_ok_o : out std_logic;
-- WR leds
led_link_o : out std_logic;
led_act_o : out std_logic;
-- The wishbone bus from the gennum/host to the application
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in
);
end entity svec7_base_wr;
architecture top of svec7_base_wr is
component svec7_ddr3_controller is
port (
app_ref_ack : out std_logic;
app_ref_req : in std_logic;
app_sr_active : out std_logic;
app_sr_req : in std_logic;
app_zq_ack : out std_logic;
app_zq_req : in std_logic;
aresetn : in std_logic;
clk_ref_i : in std_logic;
ddr3_addr : out std_logic_vector(13 downto 0);
ddr3_ba : out std_logic_vector(2 downto 0);
ddr3_cas_n : out std_logic;
ddr3_ck_n : out std_logic;
ddr3_ck_p : out std_logic;
ddr3_cke : out std_logic;
ddr3_cs_n : out std_logic;
ddr3_dm : out std_logic_vector(7 downto 0);
ddr3_dq : inout std_logic_vector(63 downto 0);
ddr3_dqs_n : inout std_logic_vector(7 downto 0);
ddr3_dqs_p : inout std_logic_vector(7 downto 0);
ddr3_odt : out std_logic;
ddr3_ras_n : out std_logic;
ddr3_reset_n : out std_logic;
ddr3_we_n : out std_logic;
device_temp : out std_logic_vector(11 downto 0);
init_calib_complete : out std_logic;
mmcm_locked : out std_logic;
s_axi_araddr : in std_logic_vector(29 downto 0);
s_axi_arburst : in std_logic_vector(1 downto 0);
s_axi_arcache : in std_logic_vector(3 downto 0);
s_axi_arid : in std_logic_vector(3 downto 0);
s_axi_arlen : in std_logic_vector(7 downto 0);
s_axi_arlock : in std_logic;
s_axi_arprot : in std_logic_vector(2 downto 0);
s_axi_arqos : in std_logic_vector(3 downto 0);
s_axi_arready : out std_logic;
s_axi_arsize : in std_logic_vector(2 downto 0);
s_axi_arvalid : in std_logic;
s_axi_awaddr : in std_logic_vector(29 downto 0);
s_axi_awburst : in std_logic_vector(1 downto 0);
s_axi_awcache : in std_logic_vector(3 downto 0);
s_axi_awid : in std_logic_vector(3 downto 0);
s_axi_awlen : in std_logic_vector(7 downto 0);
s_axi_awlock : in std_logic;
s_axi_awprot : in std_logic_vector(2 downto 0);
s_axi_awqos : in std_logic_vector(3 downto 0);
s_axi_awready : out std_logic;
s_axi_awsize : in std_logic_vector(2 downto 0);
s_axi_awvalid : in std_logic;
s_axi_bid : out std_logic_vector(3 downto 0);
s_axi_bready : in std_logic;
s_axi_bresp : out std_logic_vector(1 downto 0);
s_axi_bvalid : out std_logic;
s_axi_rdata : out std_logic_vector(511 downto 0);
s_axi_rid : out std_logic_vector(3 downto 0);
s_axi_rlast : out std_logic;
s_axi_rready : in std_logic;
s_axi_rresp : out std_logic_vector(1 downto 0);
s_axi_rvalid : out std_logic;
s_axi_wdata : in std_logic_vector(511 downto 0);
s_axi_wlast : in std_logic;
s_axi_wready : out std_logic;
s_axi_wstrb : in std_logic_vector(63 downto 0);
s_axi_wvalid : in std_logic;
sys_clk_i : in std_logic;
sys_rst : in std_logic;
ui_clk : out std_logic;
ui_clk_sync_rst : out std_logic);
end component svec7_ddr3_controller;
-- WRPC Xilinx platform auxiliary clock configuration, used for DDR clock
constant c_WRPC_PLL_CONFIG : t_auxpll_cfg_array := (
0 => (enabled => TRUE, bufg_en => TRUE, divide => 3),
others => c_AUXPLL_CFG_DEFAULT);
signal clk_sys_62m5 : std_logic; -- 62.5Mhz
signal clk_pll_aux : std_logic_vector(3 downto 0);
signal rst_pll_aux_n : std_logic_vector(3 downto 0) := (others => '0');
-- DDR
signal ddr_rst : std_logic := '1';
signal vme_wb_out : t_wishbone_master_out;
signal vme_wb_in : t_wishbone_master_in;
-- The wishbone bus to the carrier part.
signal carrier_wb_out : t_wishbone_slave_out;
signal carrier_wb_in : t_wishbone_slave_in;
signal metadata_addr : std_logic_vector(5 downto 2);
signal metadata_data : std_logic_vector(31 downto 0);
signal buildinfo_addr : std_logic_vector(7 downto 2);
signal buildinfo_data : std_logic_vector(31 downto 0);
signal therm_id_in : t_wishbone_master_in;
signal therm_id_out : t_wishbone_master_out;
-- i2c controllers to the fmcs
signal fmc_i2c_in : t_wishbone_master_in;
signal fmc_i2c_out : t_wishbone_master_out;
-- spi controller to the flash
signal flash_spi_in : t_wishbone_master_in;
signal flash_spi_out : t_wishbone_master_out;
-- vector interrupt controller
signal vic_in : t_wishbone_master_in;
signal vic_out : t_wishbone_master_out;
-- white-rabbit core
signal wrc_in : t_wishbone_master_in;
signal wrc_out : t_wishbone_master_out;
signal wrc_out_sh : t_wishbone_master_out;
signal csr_rst_gbl : std_logic;
signal csr_rst_app : std_logic;
signal rst_csr_app_n : std_logic;
signal rst_csr_app_sync_n : std_logic;
signal rst_gbl_n : std_logic;
signal fmc0_scl_out, fmc0_sda_out : std_logic;
signal fmc0_scl_oen, fmc0_sda_oen : std_logic;
signal fmc1_scl_out, fmc1_sda_out : std_logic;
signal fmc1_scl_oen, fmc1_sda_oen : std_logic;
signal fmc_presence : std_logic_vector(31 downto 0);
signal irq_master : std_logic;
constant num_interrupts : natural := 6 + g_NUM_USER_IRQ;
signal irqs : std_logic_vector(num_interrupts - 1 downto 0);
-- clock and reset
signal rst_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal rst_ref_125m_n : std_logic;
signal clk_ref_125m : std_logic;
-- I2C EEPROM
signal eeprom_sda_in : std_logic;
signal eeprom_sda_out : std_logic;
signal eeprom_scl_in : std_logic;
signal eeprom_scl_out : std_logic;
-- SFP
signal sfp_sda_in : std_logic;
signal sfp_sda_out : std_logic;
signal sfp_scl_in : std_logic;
signal sfp_scl_out : std_logic;
signal clk_dmtd_125m : std_logic;
signal ddr_init_done : std_logic;
attribute keep : string;
attribute keep of clk_sys_62m5 : signal is "TRUE";
attribute keep of clk_ref_125m : signal is "TRUE";
attribute keep of ddr_rst : signal is "TRUE";
begin -- architecture top
rst_sys_62m5 <= not rst_sys_62m5_n;
------------------------------------------------------------------------------
-- VME interface
------------------------------------------------------------------------------
cmp_vme_core : entity work.xvme64x_core_slave
generic map (
g_CLOCK_PERIOD => 16,
g_DECODE_AM => TRUE,
g_USER_CSR_EXT => FALSE,
g_WB_GRANULARITY => BYTE,
-- g_WB_MODE => PIPELINED,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_SVEC_PROGRAM_ID)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
wb_o => vme_wb_out,
wb_i => vme_wb_in,
bridge_clk_o => sfpga_clk_o,
bridge_rst_n_o => sfpga_rst_n_o,
bridge_d_i => sfpga_d_i,
bridge_d_o => sfpga_d_o,
bridge_frame_i => sfpga_frame_i,
bridge_frame_o => sfpga_frame_o,
int_i => irq_master);
-- Mini-crossbar from vme to carrier and application bus.
inst_split: entity work.xwb_split
generic map (
g_mask => x"ffff_e000"
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_sys_62m5_n,
slave_i => vme_wb_out,
slave_o => vme_wb_in,
master_i (0) => carrier_wb_out,
master_i (1) => app_wb_i,
master_o (0) => carrier_wb_in,
master_o (1) => app_wb_o
);
inst_carrier: entity work.svec_base_regs
port map (
rst_n_i => rst_sys_62m5_n,
clk_i => clk_sys_62m5,
wb_cyc_i => carrier_wb_in.cyc,
wb_stb_i => carrier_wb_in.stb,
wb_adr_i => carrier_wb_in.adr (12 downto 2), -- Bytes address from vme64x core
wb_sel_i => carrier_wb_in.sel,
wb_we_i => carrier_wb_in.we,
wb_dat_i => carrier_wb_in.dat,
wb_ack_o => carrier_wb_out.ack,
wb_err_o => carrier_wb_out.err,
wb_rty_o => carrier_wb_out.rty,
wb_stall_o => carrier_wb_out.stall,
wb_dat_o => carrier_wb_out.dat,
-- a ROM containing the carrier metadata
metadata_addr_o => metadata_addr,
metadata_data_i => metadata_data,
metadata_data_o => open,
-- offset to the application metadata
csr_app_offset_i => g_APP_OFFSET,
csr_resets_global_o => csr_rst_gbl,
csr_resets_appl_o => csr_rst_app,
-- presence lines for the fmcs
csr_fmc_presence_i => fmc_presence,
csr_ddr_status_ddr4_calib_done_i => ddr_init_done,
csr_ddr_status_ddr5_calib_done_i => '1',
csr_pcb_rev_rev_i => pcbrev_i,
csr_ddr4_addr_i => (others => '0'),
csr_ddr4_data_i => (others => '0'),
csr_ddr4_data_wack_i => '0',
csr_ddr4_data_rack_i => '0',
-- csr_ddr4_addr_i => csr_ddr4_addr,
-- csr_ddr4_addr_o => csr_ddr4_addr_out,
-- csr_ddr4_addr_wr_o => csr_ddr4_addr_wr,
--
-- data to read or to write in ddr4
-- csr_ddr4_data_i => csr_ddr4_data_in,
-- csr_ddr4_data_o => csr_ddr4_data_out,
-- csr_ddr4_data_wr_o => csr_ddr4_data_wr,
-- csr_ddr4_data_rd_o => csr_ddr4_data_rd,
-- csr_ddr4_data_wack_i => csr_ddr4_data_wack,
-- csr_ddr4_data_rack_i => csr_ddr4_data_rack,
-- Thermometer and unique id
therm_id_i => therm_id_in,
therm_id_o => therm_id_out,
-- i2c controllers to the fmcs
fmc_i2c_i => fmc_i2c_in,
fmc_i2c_o => fmc_i2c_out,
-- spi controller to the flash
flash_spi_i => flash_spi_in,
flash_spi_o => flash_spi_out,
-- vector interrupt controller
vic_i => vic_in,
vic_o => vic_out,
-- a ROM containing build info
buildinfo_addr_o => buildinfo_addr,
buildinfo_data_i => buildinfo_data,
buildinfo_data_o => open,
-- white-rabbit core
wrc_regs_i => wrc_in,
wrc_regs_o => wrc_out
);
fmc_presence (0) <= not fmc0_prsnt_m2c_n_i;
fmc_presence (1) <= not fmc1_prsnt_m2c_n_i;
fmc_presence (31 downto 2) <= (others => '0');
-- Metadata
p_metadata: process (clk_sys_62m5) is
begin
if rising_edge(clk_sys_62m5) then
case metadata_addr is
when x"0" =>
-- Vendor ID
metadata_data <= x"000010dc";
when x"1" =>
-- Device ID
metadata_data <= x"53564543";
when x"2" =>
-- Version
metadata_data <= x"01040000";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
when x"4" | x"5" | x"6" | x"7" =>
-- source id
metadata_data <= x"00000000";
when x"8" =>
-- capability mask
metadata_data <= x"00000000";
if g_WITH_VIC then
metadata_data(0) <= '1';
end if;
if g_WITH_ONEWIRE and not g_WITH_WR then
metadata_data(1) <= '1';
end if;
if g_WITH_SPI then
metadata_data(2) <= '1';
end if;
if g_WITH_WR then
metadata_data(3) <= '1';
end if;
-- Buildinfo
metadata_data(4) <= '1';
if g_WITH_DDR then
metadata_data(5) <= '1';
end if;
if g_WITH_DDR then
metadata_data(6) <= '1';
end if;
when others =>
metadata_data <= x"00000000";
end case;
end if;
end process;
-- Build information
p_buildinfo: process (clk_sys_62m5) is
variable addr : natural;
variable b : std_logic_vector(7 downto 0);
begin
if rising_edge(clk_sys_62m5) then
addr := to_integer(unsigned(buildinfo_addr)) * 4;
for i in 0 to 3 loop
if addr + i < buildinfo'length then
b := std_logic_vector(to_unsigned(character'pos(
buildinfo(buildinfo'left + addr + i)), 8));
else
b := x"00";
end if;
buildinfo_data (7 + i * 8 downto i * 8) <= b;
end loop;
end if;
end process;
rst_gbl_n <= rst_sys_62m5_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= csr_rst_gbl;
rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
rst_sys_62m5_n_o <= rst_sys_62m5_n and rst_csr_app_n;
clk_sys_62m5_o <= clk_sys_62m5;
i_rst_csr_app_sync : gc_sync_ffs
port map (
clk_i => clk_ref_125m,
rst_n_i => '1',
data_i => rst_csr_app_n,
synced_o => rst_csr_app_sync_n);
rst_ref_125m_n_o <= rst_ref_125m_n and rst_csr_app_sync_n;
clk_ref_125m_o <= clk_ref_125m;
inst_i2c: entity work.xwb_i2c_master
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_num_interfaces => 2)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => fmc_i2c_out,
slave_o => fmc_i2c_in,
desc_o => open,
int_o => irqs(0),
scl_pad_i (0) => fmc0_scl_b,
scl_pad_i (1) => fmc1_scl_b,
scl_pad_o (0) => fmc0_scl_out,
scl_pad_o (1) => fmc1_scl_out,
scl_padoen_o (0) => fmc0_scl_oen,
scl_padoen_o (1) => fmc1_scl_oen,
sda_pad_i (0) => fmc0_sda_b,
sda_pad_i (1) => fmc1_sda_b,
sda_pad_o (0) => fmc0_sda_out,
sda_pad_o (1) => fmc1_sda_out,
sda_padoen_o (0) => fmc0_sda_oen,
sda_padoen_o (1) => fmc1_sda_oen
);
fmc0_scl_b <= fmc0_scl_out when fmc0_scl_oen = '0' else 'Z';
fmc0_sda_b <= fmc0_sda_out when fmc0_sda_oen = '0' else 'Z';
fmc1_scl_b <= fmc1_scl_out when fmc1_scl_oen = '0' else 'Z';
fmc1_sda_b <= fmc1_sda_out when fmc1_sda_oen = '0' else 'Z';
gen_user_irq: if g_NUM_USER_IRQ > 0 generate
irqs(irq_user_i'range) <= irq_user_i;
end generate gen_user_irq;
gen_vic: if g_with_vic generate
i_vic: entity work.xwb_vic
generic map (
g_address_granularity => BYTE,
g_num_interrupts => num_interrupts
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => vic_out,
slave_o => vic_in,
irqs_i => irqs,
irq_master_o => irq_master
);
end generate;
gen_no_vic: if not g_with_vic generate
vic_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irq_master <= '0';
end generate;
irqs(4) <= '0';
irqs(5) <= '0';
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master #2 (Etherbone))
-----------------------------------------------------------------------------
gen_wr: if g_WITH_WR generate
-- OneWire
signal onewire_data : std_logic;
signal onewire_oe : std_logic;
begin
-- Remap WR registers.
wrc_out_sh <= (cyc => wrc_out.cyc, stb => wrc_out.stb,
adr => wrc_out.adr or x"00020000",
sel => wrc_out.sel, we => wrc_out.we, dat => wrc_out.dat);
cmp_xwrc_board_svec : entity work.xwrc_board_svec7
generic map (
g_simulation => g_SIMULATION,
g_VERBOSE => g_VERBOSE,
g_with_external_clock_input => TRUE,
g_dpram_initf => g_DPRAM_INITF,
g_AUX_CLKS => g_AUX_CLKS,
g_AUX_PLL_CFG => c_WRPC_PLL_CONFIG,
g_STREAMERS_OP_MODE => g_STREAMERS_OP_MODE,
g_TX_STREAMER_PARAMS => g_TX_STREAMER_PARAMS,
g_RX_STREAMER_PARAMS => g_RX_STREAMER_PARAMS,
g_FABRIC_IFACE => g_FABRIC_IFACE)
port map (
areset_n_i => rst_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_aux_i => clk_aux_i,
clk_10m_ext_i => clk_10m_ext_i,
pps_ext_i => pps_ext_i,
clk_sys_62m5_o => clk_sys_62m5,
clk_ref_125m_o => clk_ref_125m,
clk_pll_aux_o => clk_pll_aux,
clk_dmtd_125m_o => clk_dmtd_125m,
rst_sys_62m5_n_o => rst_sys_62m5_n,
rst_ref_125m_n_o => rst_ref_125m_n,
rst_pll_aux_n_o => rst_pll_aux_n,
pll20dac_din_o => pll20dac_din_o,
pll20dac_sclk_o => pll20dac_sclk_o,
pll20dac_sync_n_o => pll20dac_sync_n_o,
pll25dac_din_o => pll25dac_din_o,
pll25dac_sclk_o => pll25dac_sclk_o,
pll25dac_sync_n_o => pll25dac_sync_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_det_i => sfp_mod_def0_i,
sfp_sda_i => sfp_sda_in,
sfp_sda_o => sfp_sda_out,
sfp_scl_i => sfp_scl_in,
sfp_scl_o => sfp_scl_out,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i,
eeprom_sda_i => eeprom_sda_in,
eeprom_sda_o => eeprom_sda_out,
eeprom_scl_i => eeprom_scl_in,
eeprom_scl_o => eeprom_scl_out,
onewire_i => onewire_data,
onewire_oen_o => onewire_oe,
-- Uart
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
-- SPI Flash (not used)
spi_ncs_o => open,
spi_mosi_o => open,
spi_miso_i => '0',
wb_slave_o => wrc_in,
wb_slave_i => wrc_out_sh,
wrf_src_o => wrf_src_o,
wrf_src_i => wrf_src_i,
wrf_snk_o => wrf_snk_o,
wrf_snk_i => wrf_snk_i,
wrs_tx_data_i => wrs_tx_data_i,
wrs_tx_valid_i => wrs_tx_valid_i,
wrs_tx_dreq_o => wrs_tx_dreq_o,
wrs_tx_last_i => wrs_tx_last_i,
wrs_tx_flush_i => wrs_tx_flush_i,
wrs_tx_cfg_i => wrs_tx_cfg_i,
wrs_rx_first_o => wrs_rx_first_o,
wrs_rx_last_o => wrs_rx_last_o,
wrs_rx_data_o => wrs_rx_data_o,
wrs_rx_valid_o => wrs_rx_valid_o,
wrs_rx_dreq_i => wrs_rx_dreq_i,
wrs_rx_cfg_i => wrs_rx_cfg_i,
wb_eth_master_o => wb_eth_master_o,
wb_eth_master_i => wb_eth_master_i,
tm_link_up_o => tm_link_up_o,
tm_time_valid_o => tm_time_valid_o,
tm_tai_o => tm_tai_o,
tm_cycles_o => tm_cycles_o,
tm_dac_value_o => tm_dac_value_o,
tm_dac_wr_o => tm_dac_wr_o,
tm_clk_aux_lock_en_i => tm_clk_aux_lock_en_i,
tm_clk_aux_locked_o => tm_clk_aux_locked_o,
pps_p_o => pps_p_o,
pps_led_o => pps_led_o,
link_ok_o => link_ok_o,
led_link_o => led_link_o,
led_act_o => led_act_o);
-- Tristates for SFP EEPROM
sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
sfp_scl_in <= sfp_mod_def1_b;
sfp_sda_in <= sfp_mod_def2_b;
-- Tristates for Carrier EEPROM
carrier_scl_b <= '0' when (eeprom_scl_out = '0') else 'Z';
carrier_sda_b <= '0' when (eeprom_sda_out = '0') else 'Z';
eeprom_scl_in <= carrier_scl_b;
eeprom_sda_in <= carrier_sda_b;
-- tri-state onewire access
onewire_b <= '0' when (onewire_oe = '1') else 'Z';
onewire_data <= onewire_b;
-- WR means neither onewire nor spi.
assert not g_WITH_ONEWIRE report "WR is not yet compatible with ONEWIRE"
severity failure;
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0',
dat => (others => '0'));
end generate;
gen_no_wr: if not g_WITH_WR generate
signal clk_125m_pllref : std_logic;
signal pllout_clk_fb_pllref : std_logic;
signal pllout_clk_sys_62m5 : std_logic;
signal pllout_clk_ref_125m : std_logic;
signal pllout_locked : std_logic;
signal rstlogic_arst : std_logic;
begin
-- Input clock
cmp_pllrefclk_buf : IBUFGDS
generic map (
DIFF_TERM => true, -- Differential Termination
IBUF_LOW_PWR => true, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standard
IOSTANDARD => "DEFAULT")
port map (
O => clk_125m_pllref, -- Buffer output
I => clk_125m_pllref_p_i, -- Diff_p buffer input (connect directly to top-level port)
IB => clk_125m_pllref_n_i -- Diff_n buffer input (connect directly to top-level port)
);
-- fixme: port to kintex7
-- cmp_sys_clk_pll : PLLE2_ADV
-- generic map (
-- BANDWIDTH => "OPTIMIZED",
-- CLK_FEEDBACK => "CLKFBOUT",
-- COMPENSATION => "INTERNAL",
-- DIVCLK_DIVIDE => 1,
-- CLKFBOUT_MULT => 16,
-- CLKFBOUT_PHASE => 0.000,
-- CLKOUT0_DIVIDE => 16, -- 62.5 MHz
-- CLKOUT0_PHASE => 0.000,
-- CLKOUT0_DUTY_CYCLE => 0.500,
-- CLKOUT1_DIVIDE => 16, -- 125 MHz
-- CLKOUT1_PHASE => 0.000,
-- CLKOUT1_DUTY_CYCLE => 0.500,
-- CLKOUT2_DIVIDE => 3, -- 333 MHz
-- CLKOUT2_PHASE => 0.000,
-- CLKOUT2_DUTY_CYCLE => 0.500,
-- CLKIN_PERIOD => 8.0,
-- REF_JITTER => 0.016)
-- port map (
-- CLKFBOUT => pllout_clk_fb_pllref,
-- CLKOUT0 => pllout_clk_sys_62m5,
-- CLKOUT1 => pllout_clk_ref_62m5,
-- CLKOUT2 => open,
-- CLKOUT3 => open,
-- CLKOUT4 => open,
-- CLKOUT5 => open,
-- LOCKED => pllout_locked,
-- RST => '0',
-- CLKFBIN => pllout_clk_fb_pllref,
-- CLKIN => clk_62m5_pllref);
cmp_clk_62m5_buf : BUFG
port map (
O => clk_sys_62m5,
I => pllout_clk_sys_62m5);
cmp_clk_125m_buf : BUFG
port map (
O => clk_ref_125m,
I => pllout_clk_ref_125m);
-- logic AND of all async reset sources (active high)
rstlogic_arst <= (not pllout_locked) and (not rst_n_i);
-- Clocks required to have synced resets
cmp_rstlogic_reset : gc_reset_multi_aasd
generic map (
g_CLOCKS => 2,
g_RST_LEN => 16) -- 16 clock cycles
port map (
arst_i => rstlogic_arst,
clks_i (0) => clk_sys_62m5,
clks_i (1) => clk_ref_125m,
rst_n_o (0) => rst_sys_62m5_n,
rst_n_o (1) => rst_ref_125m_n);
-- Not used.
wrc_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
end generate;
gen_onewire: if g_WITH_ONEWIRE and not g_WITH_WR generate
i_onewire: entity work.xwb_ds182x_readout
generic map (
g_CLOCK_FREQ_KHZ => 62_500,
g_USE_INTERNAL_PPS => True)
port map (
clk_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
wb_i => therm_id_out,
wb_o => therm_id_in,
pps_p_i => '0',
onewire_b => onewire_b
);
end generate;
gen_no_onewire: if not g_WITH_ONEWIRE and not g_WITH_WR generate
therm_id_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
onewire_b <= 'Z';
end generate;
gen_spi: if g_WITH_SPI generate
signal spi_sclk : std_logic;
begin
i_spi: entity work.xwb_spi
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_divider_len => open,
g_max_char_len => open,
g_num_slaves => 1
)
port map (
clk_sys_i => clk_sys_62m5,
rst_n_i => rst_gbl_n,
slave_i => flash_spi_out,
slave_o => flash_spi_in,
desc_o => open,
int_o => irqs(1),
pad_cs_o(0) => spi_ncs_o,
pad_sclk_o => spi_sclk,
pad_mosi_o => spi_mosi_o,
pad_miso_i => spi_miso_i
);
U_Kintex7_Startup : STARTUPE2
generic map (
PROG_USR => "FALSE",
SIM_CCLK_FREQ => 0.0)
port map (
CFGCLK => open,
CFGMCLK => open,
EOS => open,
PREQ => open,
CLK => '0',
GSR => '0',
GTS => '0',
KEYCLEARB => '1',
PACK => '1',
USRCCLKO => spi_sclk,
USRCCLKTS => '0', -- always out
USRDONEO => '1',
USRDONETS => '1');
end generate;
gen_no_spi : if not g_WITH_SPI generate
flash_spi_in <= (ack => '1', err => '0', rty => '0', stall => '0', dat => x"00000000");
irqs(1) <= '0';
spi_ncs_o <= '1';
spi_mosi_o <= '0';
end generate;
-- DDR3 controller
gen_with_ddr: if g_WITH_DDR and g_DDR_CONTROLLER = "LITEDRAM" generate
signal pllout_ddr_clk_fb : std_logic;
signal pllout_ddr_clk_fb_bufg : std_logic;
signal pllout_clk_ddr_iodelay : std_logic;
signal pllout_ddr_locked : std_logic;
signal clk_ddr_sys4x : std_logic;
signal clk_ddr_sys4x_dqs : std_logic;
signal clk_ddr_iodelay : std_logic;
begin
cmp_ddr_clk_pll : PLLE2_ADV
generic map (
BANDWIDTH => ("HIGH"),
COMPENSATION => ("ZHOLD"),
STARTUP_WAIT => ("FALSE"),
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 16,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 2, -- 500 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 2, -- 500 MHz / 90 deg
CLKOUT1_PHASE => 90.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 5, -- 200 MHz
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN1_PERIOD => 16.0 )
port map (
CLKFBOUT => pllout_ddr_clk_fb,
CLKOUT0 => clk_ddr_sys4x,
CLKOUT1 => clk_ddr_sys4x_dqs,
CLKOUT2 => pllout_clk_ddr_iodelay,
LOCKED => pllout_ddr_locked,
RST => '0',
CLKFBIN => pllout_ddr_clk_fb_bufg,
CLKIN1 => ddr_clk_i,
CLKIN2 => '0',
CLKINSEL => '1',
DADDR => (others => '0'),
dwe => '0',
di => (others => '0'),
dclk => '0',
den => '0',
PWRDWN => '0'
);
cmp_clk_ddr_iodelay : BUFG
port map (
O => clk_ddr_iodelay,
I => pllout_clk_ddr_iodelay);
cmp_clk_ddr_fb : BUFG
port map (
O => pllout_ddr_clk_fb_bufg,
I => pllout_ddr_clk_fb);
cmp_ddr_idelayctrl : IDELAYCTRL
port map (
RDY => open,
REFCLK => clk_ddr_iodelay,
RST => '0'
);
gen_use_litedram : if g_DDR_CONTROLLER = "LITEDRAM" generate
cmp_litedram_ctrl : entity work.litedram_core
port map (
-- serial_tx => open, --litedram_serial_tx,
-- serial_rx => '1', --litedram_serial_rx,
rst => ddr_rst,
clk_sys => ddr_clk_i,
clk_sys_4x => clk_ddr_sys4x,
clk_sys_4x_dqs => clk_ddr_sys4x_dqs,
ddram_a => ddr_a_o,
ddram_ba => ddr_ba_o,
ddram_ras_n => ddr_ras_n_o,
ddram_cas_n => ddr_cas_n_o,
ddram_we_n => ddr_we_n_o,
ddram_cs_n => ddr_cs_n_o,
ddram_dm => ddr_dm_o,
ddram_dq => ddr_dq_b,
ddram_dqs_p => ddr_dqs_p_b,
ddram_dqs_n => ddr_dqs_n_b,
ddram_clk_p => ddr_ck_p_o,
ddram_clk_n => ddr_ck_n_o,
ddram_cke => ddr_cke_o,
ddram_odt => ddr_odt_o,
ddram_reset_n => ddr_reset_n_o,
init_done => open,
init_error => open,
user_port0_aw_valid => ddr_axi4_i.AWVALID,
user_port0_aw_ready => ddr_axi4_o.AWREADY,
user_port0_aw_addr=> ddr_axi4_i.AWADDR,
user_port0_aw_burst=> ddr_axi4_i.AWBURST,
user_port0_aw_len=> ddr_axi4_i.AWLEN,
user_port0_aw_size=> ddr_axi4_i.AWSIZE,
user_port0_aw_id=> ddr_axi4_i.AWID,
user_port0_w_valid => ddr_axi4_i.WVALID,
user_port0_w_ready=> ddr_axi4_o.WREADY,
user_port0_w_last=> ddr_axi4_i.WLAST,
user_port0_w_strb=> ddr_axi4_i.WSTRB,
user_port0_w_data=> ddr_axi4_i.WDATA,
user_port0_b_valid=> ddr_axi4_o.BVALID,
user_port0_b_ready=> ddr_axi4_i.BREADY,
user_port0_b_resp=> ddr_axi4_o.BRESP,
user_port0_b_id=> ddr_axi4_o.BID,
user_port0_ar_valid=> ddr_axi4_i.ARVALID,
user_port0_ar_ready=> ddr_axi4_o.ARREADY,
user_port0_ar_addr=> ddr_axi4_i.ARADDR,
user_port0_ar_burst=> ddr_axi4_i.ARBURST,
user_port0_ar_len=> ddr_axi4_i.ARLEN,
user_port0_ar_size=> ddr_axi4_i.ARSIZE,
user_port0_ar_id=> ddr_axi4_i.ARID,
user_port0_r_valid=> ddr_axi4_o.RVALID,
user_port0_r_ready=> ddr_axi4_i.RREADY,
user_port0_r_last=> ddr_axi4_o.RLAST,
user_port0_r_resp=> ddr_axi4_o.RRESP,
user_port0_r_data=> ddr_axi4_o.RDATA,
user_port0_r_id=> ddr_axi4_o.RID);
end generate gen_use_litedram;
gen_use_mig: if g_DDR_CONTROLLER = "MIG" generate
U_MIG: svec7_ddr3_controller
port map (
ddr3_dq => ddr_dq_b,
ddr3_dqs_n => ddr_dqs_n_b,
ddr3_dqs_p => ddr_dqs_p_b,
ddr3_addr => ddr_a_o(13 downto 0),
ddr3_ba => ddr_ba_o,
ddr3_ras_n => ddr_ras_n_o,
ddr3_cas_n => ddr_cas_n_o,
ddr3_we_n => ddr_we_n_o,
ddr3_reset_n => ddr_reset_n_o,
ddr3_ck_p => ddr_ck_p_o,
ddr3_ck_n => ddr_ck_n_o,
ddr3_cke => ddr_cke_o,
ddr3_cs_n => ddr_cs_n_o,
ddr3_dm => ddr_dm_o,
ddr3_odt => ddr_odt_o,
sys_rst => rst_sys_62m5,
sys_clk_i => clk_sys_62m5,
clk_ref_i => clk_sys_62m5,
ui_clk => ddr_clk_o,
ui_clk_sync_rst => open,
mmcm_locked => open,
aresetn => ddr_rst_n_i,
app_sr_req => '0',
app_ref_req => '0',
app_zq_req => '0',
s_axi_awid => ddr_axi4_i.AWID(3 downto 0),
s_axi_awaddr => ddr_axi4_i.AWADDR(29 downto 0),
s_axi_awlen => ddr_axi4_i.AWLEN,
s_axi_awsize => ddr_axi4_i.AWSIZE(2 downto 0),
s_axi_awburst => ddr_axi4_i.AWBURST,
s_axi_awlock => ddr_axi4_i.awlock(0),
s_axi_awcache => ddr_axi4_i.AWCACHE,
s_axi_awprot => ddr_axi4_i.AWPROT,
s_axi_awqos => ddr_axi4_i.AWQOS,
s_axi_awvalid => ddr_axi4_i.AWVALID,
s_axi_awready => ddr_axi4_o.AWREADY,
s_axi_wdata => ddr_axi4_i.WDATA,
s_axi_wstrb => ddr_axi4_i.WSTRB,
s_axi_wlast => ddr_axi4_i.WLAST,
s_axi_wvalid => ddr_axi4_i.WVALID,
s_axi_wready => ddr_axi4_o.WREADY,
s_axi_bready => ddr_axi4_i.BREADY,
s_axi_bid => ddr_axi4_o.BID(3 downto 0),
s_axi_bresp => ddr_axi4_o.BRESP,
s_axi_bvalid => ddr_axi4_o.BVALID,
s_axi_arid => ddr_axi4_i.ARID(3 downto 0),
s_axi_araddr => ddr_axi4_i.ARADDR(29 downto 0),
s_axi_arlen => ddr_axi4_i.ARLEN,
s_axi_arsize => ddr_axi4_i.ARSIZE(2 downto 0),
s_axi_arburst => ddr_axi4_i.ARBURST,
s_axi_arlock => ddr_axi4_i.ARLOCK(0),
s_axi_arcache => ddr_axi4_i.ARCACHE,
s_axi_arprot => ddr_axi4_i.ARPROT,
s_axi_arqos => ddr_axi4_i.ARQOS,
s_axi_arvalid => ddr_axi4_i.ARVALID,
s_axi_arready => ddr_axi4_o.ARREADY,
s_axi_rready => ddr_axi4_i.RREADY,
s_axi_rid => ddr_axi4_o.RID(3 downto 0),
s_axi_rdata => ddr_axi4_o.RDATA,
s_axi_rresp => ddr_axi4_o.RRESP,
s_axi_rlast => ddr_axi4_o.RLAST,
s_axi_rvalid => ddr_axi4_o.RVALID,
init_calib_complete => open
);
end generate gen_use_mig;
end generate gen_with_ddr;
gen_without_ddr : if not g_WITH_DDR generate
ddr_a_o <= (others => '0');
ddr_ba_o <= (others => '0');
ddr_dq_b <= (others => 'Z');
ddr_cas_n_o <= '0';
ddr_ck_p_o <= '0';
ddr_ck_n_o <= '0';
ddr_cke_o <= '0';
ddr_odt_o <= '0';
ddr_dm_o <= (others => '0');
ddr_ras_n_o <= '0';
ddr_reset_n_o <= '0';
ddr_we_n_o <= '0';
ddr_cs_n_o <= '1';
ddr_rzq_b <= 'Z';
end generate gen_without_ddr;
clk_dmtd_125m_o <= clk_dmtd_125m;
end architecture top;
hdl/sim/vme64x_bfm/vme64x_bfm.svh
View file @ 29b98259
......@@ -8,6 +8,7 @@
`define assert_wait(name, condition, timeout) \
begin\
time t=$time;\
$display("Cond: %b", condition);\
while(!(condition)) begin\
#1ns;\
if($time - t > timeout) begin\
......@@ -19,9 +20,6 @@ begin\
end
interface IVME64X ( input sys_rst_n_i );
wire as_n;
......
hdl/syn/svec7_test/Manifest.py
View file @ 29b98259
target = "xilinx"
action = "synthesis"
syn_device = "xc7k325t"
syn_grade = "-2"
syn_package = "ffg900"
syn_device = "xc7a200t"
syn_grade = "-3"
syn_package = "ffg1156"
syn_top = "svec7_test_top"
syn_project = "svec7_test_top"
syn_tool = "vivado"
board = "svec7a"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
"." ]
files = [ "../../platform/xilinx/artix7/vivado/svec7_ip/svec7_ip.srcs/sources_1/ip/svec7_ddr3_controller/svec7_ddr3_controller.xci", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7",
"local" : [ "../../rtl/svec7a",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core",
],
}
try:
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/syn/svec7_test/pins.xdc deleted 100644 → 0
View file @ 90348ce2
set_property PACKAGE_PIN AG29 [get_ports {clk_20m_vcxo_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {clk_20m_vcxo_i}]
set_property PACKAGE_PIN AD23 [get_ports {clk_62m5_pllref_p_i}]
set_property IOSTANDARD LVDS [get_ports {clk_62m5_pllref_p_i}]
set_property PACKAGE_PIN AE24 [get_ports {clk_62m5_pllref_n_i}]
set_property IOSTANDARD LVDS [get_ports {clk_62m5_pllref_n_i}]
set_property PACKAGE_PIN R7 [get_ports {clk_125m_gtx_n_i}]
set_property PACKAGE_PIN R8 [get_ports {clk_125m_gtx_p_i}]
set_property PACKAGE_PIN AF22 [get_ports {clk_fpga2_p_i}]
set_property IOSTANDARD LVDS [get_ports {clk_fpga2_p_i}]
set_property PACKAGE_PIN AG23 [get_ports {clk_fpga2_n_i}]
set_property IOSTANDARD LVDS [get_ports {clk_fpga2_n_i}]
set_property PACKAGE_PIN AB27 [get_ports {clk_si57x_p_i}]
set_property IOSTANDARD LVDS [get_ports {clk_si57x_p_i}]
set_property PACKAGE_PIN AC27 [get_ports {clk_si57x_n_i}]
set_property IOSTANDARD LVDS [get_ports {clk_si57x_n_i}]
set_property PACKAGE_PIN L25 [get_ports {fmc0_clk_m2c_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[0]}]
set_property PACKAGE_PIN K25 [get_ports {fmc0_clk_m2c_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[0]}]
set_property PACKAGE_PIN K28 [get_ports {fmc0_clk_m2c_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_p_i[1]}]
set_property PACKAGE_PIN K29 [get_ports {fmc0_clk_m2c_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc0_clk_m2c_n_i[1]}]
set_property PACKAGE_PIN C25 [get_ports {fmc1_clk_m2c_p_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[0]}]
set_property PACKAGE_PIN B25 [get_ports {fmc1_clk_m2c_n_i[0]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[0]}]
set_property PACKAGE_PIN D27 [get_ports {fmc1_clk_m2c_p_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_p_i[1]}]
set_property PACKAGE_PIN D27 [get_ports {fmc1_clk_m2c_n_i[1]}]
set_property IOSTANDARD LVDS_25 [get_ports {fmc1_clk_m2c_n_i[1]}]
set_property PACKAGE_PIN P24 [get_ports {fmc0_la_p_b[0]}]
set_property PACKAGE_PIN R20 [get_ports {fmc0_la_p_b[1]}]
set_property PACKAGE_PIN R23 [get_ports {fmc0_la_p_b[2]}]
set_property PACKAGE_PIN T20 [get_ports {fmc0_la_p_b[3]}]
set_property PACKAGE_PIN T22 [get_ports {fmc0_la_p_b[4]}]
set_property PACKAGE_PIN U19 [get_ports {fmc0_la_p_b[5]}]
set_property PACKAGE_PIN P29 [get_ports {fmc0_la_p_b[6]}]
set_property PACKAGE_PIN P27 [get_ports {fmc0_la_p_b[7]}]
set_property PACKAGE_PIN R30 [get_ports {fmc0_la_p_b[8]}]
set_property PACKAGE_PIN P26 [get_ports {fmc0_la_p_b[9]}]
set_property PACKAGE_PIN R28 [get_ports {fmc0_la_p_b[10]}]
set_property PACKAGE_PIN T26 [get_ports {fmc0_la_p_b[11]}]
set_property PACKAGE_PIN U27 [get_ports {fmc0_la_p_b[12]}]
set_property PACKAGE_PIN T25 [get_ports {fmc0_la_p_b[13]}]
set_property PACKAGE_PIN U29 [get_ports {fmc0_la_p_b[14]}]
set_property PACKAGE_PIN V26 [get_ports {fmc0_la_p_b[15]}]
set_property PACKAGE_PIN V29 [get_ports {fmc0_la_p_b[16]}]
set_property PACKAGE_PIN V25 [get_ports {fmc0_la_p_b[17]}]
set_property PACKAGE_PIN V19 [get_ports {fmc0_la_p_b[18]}]
set_property PACKAGE_PIN W23 [get_ports {fmc0_la_p_b[19]}]
set_property PACKAGE_PIN U22 [get_ports {fmc0_la_p_b[20]}]
set_property PACKAGE_PIN V21 [get_ports {fmc0_la_p_b[21]}]
set_property PACKAGE_PIN U24 [get_ports {fmc0_la_p_b[22]}]
set_property PACKAGE_PIN W21 [get_ports {fmc0_la_p_b[23]}]
set_property PACKAGE_PIN J23 [get_ports {fmc0_la_p_b[24]}]
set_property PACKAGE_PIN L22 [get_ports {fmc0_la_p_b[25]}]
set_property PACKAGE_PIN K23 [get_ports {fmc0_la_p_b[26]}]
set_property PACKAGE_PIN L21 [get_ports {fmc0_la_p_b[27]}]
set_property PACKAGE_PIN J21 [get_ports {fmc0_la_p_b[28]}]
set_property PACKAGE_PIN M20 [get_ports {fmc0_la_p_b[29]}]
set_property PACKAGE_PIN J29 [get_ports {fmc0_la_p_b[30]}]
set_property PACKAGE_PIN J27 [get_ports {fmc0_la_p_b[31]}]
set_property PACKAGE_PIN L30 [get_ports {fmc0_la_p_b[32]}]
set_property PACKAGE_PIN K26 [get_ports {fmc0_la_p_b[33]}]
set_property PACKAGE_PIN R25 [get_ports {fmc0_la_n_b[0]}]
set_property PACKAGE_PIN R21 [get_ports {fmc0_la_n_b[1]}]
set_property PACKAGE_PIN R24 [get_ports {fmc0_la_n_b[2]}]
set_property PACKAGE_PIN T21 [get_ports {fmc0_la_n_b[3]}]
set_property PACKAGE_PIN T23 [get_ports {fmc0_la_n_b[4]}]
set_property PACKAGE_PIN U20 [get_ports {fmc0_la_n_b[5]}]
set_property PACKAGE_PIN R29 [get_ports {fmc0_la_n_b[6]}]
set_property PACKAGE_PIN P28 [get_ports {fmc0_la_n_b[7]}]
set_property PACKAGE_PIN T30 [get_ports {fmc0_la_n_b[8]}]
set_property PACKAGE_PIN R26 [get_ports {fmc0_la_n_b[9]}]
set_property PACKAGE_PIN T28 [get_ports {fmc0_la_n_b[10]}]
set_property PACKAGE_PIN T27 [get_ports {fmc0_la_n_b[11]}]
set_property PACKAGE_PIN U28 [get_ports {fmc0_la_n_b[12]}]
set_property PACKAGE_PIN U25 [get_ports {fmc0_la_n_b[13]}]
set_property PACKAGE_PIN U30 [get_ports {fmc0_la_n_b[14]}]
set_property PACKAGE_PIN V27 [get_ports {fmc0_la_n_b[15]}]
set_property PACKAGE_PIN V30 [get_ports {fmc0_la_n_b[16]}]
set_property PACKAGE_PIN W26 [get_ports {fmc0_la_n_b[17]}]
set_property PACKAGE_PIN V20 [get_ports {fmc0_la_n_b[18]}]
set_property PACKAGE_PIN W24 [get_ports {fmc0_la_n_b[19]}]
set_property PACKAGE_PIN U23 [get_ports {fmc0_la_n_b[20]}]
set_property PACKAGE_PIN V22 [get_ports {fmc0_la_n_b[21]}]
set_property PACKAGE_PIN V24 [get_ports {fmc0_la_n_b[22]}]
set_property PACKAGE_PIN W22 [get_ports {fmc0_la_n_b[23]}]
set_property PACKAGE_PIN J24 [get_ports {fmc0_la_n_b[24]}]
set_property PACKAGE_PIN L23 [get_ports {fmc0_la_n_b[25]}]
set_property PACKAGE_PIN K24 [get_ports {fmc0_la_n_b[26]}]
set_property PACKAGE_PIN K21 [get_ports {fmc0_la_n_b[27]}]
set_property PACKAGE_PIN J22 [get_ports {fmc0_la_n_b[28]}]
set_property PACKAGE_PIN L20 [get_ports {fmc0_la_n_b[29]}]
set_property PACKAGE_PIN H29 [get_ports {fmc0_la_n_b[30]}]
set_property PACKAGE_PIN J28 [get_ports {fmc0_la_n_b[31]}]
set_property PACKAGE_PIN K30 [get_ports {fmc0_la_n_b[32]}]
set_property PACKAGE_PIN J26 [get_ports {fmc0_la_n_b[33]}]
set_property PACKAGE_PIN L26 [get_ports {fmc1_la_p_b[0]}]
set_property PACKAGE_PIN L25 [get_ports {fmc1_la_p_b[1]}]
set_property PACKAGE_PIN K28 [get_ports {fmc1_la_p_b[2]}]
set_property PACKAGE_PIN M28 [get_ports {fmc1_la_p_b[3]}]
set_property PACKAGE_PIN M29 [get_ports {fmc1_la_p_b[4]}]
set_property PACKAGE_PIN N27 [get_ports {fmc1_la_p_b[5]}]
set_property PACKAGE_PIN N29 [get_ports {fmc1_la_p_b[6]}]
set_property PACKAGE_PIN N25 [get_ports {fmc1_la_p_b[7]}]
set_property PACKAGE_PIN N19 [get_ports {fmc1_la_p_b[8]}]
set_property PACKAGE_PIN N21 [get_ports {fmc1_la_p_b[9]}]
set_property PACKAGE_PIN P23 [get_ports {fmc1_la_p_b[10]}]
set_property PACKAGE_PIN P21 [get_ports {fmc1_la_p_b[11]}]
set_property PACKAGE_PIN M24 [get_ports {fmc1_la_p_b[12]}]
set_property PACKAGE_PIN M22 [get_ports {fmc1_la_p_b[13]}]
set_property PACKAGE_PIN B23 [get_ports {fmc1_la_p_b[14]}]
set_property PACKAGE_PIN E23 [get_ports {fmc1_la_p_b[15]}]
set_property PACKAGE_PIN F25 [get_ports {fmc1_la_p_b[16]}]
set_property PACKAGE_PIN E24 [get_ports {fmc1_la_p_b[17]}]
set_property PACKAGE_PIN F26 [get_ports {fmc1_la_p_b[18]}]
set_property PACKAGE_PIN G23 [get_ports {fmc1_la_p_b[19]}]
set_property PACKAGE_PIN B27 [get_ports {fmc1_la_p_b[20]}]
set_property PACKAGE_PIN C24 [get_ports {fmc1_la_p_b[21]}]
set_property PACKAGE_PIN B28 [get_ports {fmc1_la_p_b[22]}]
set_property PACKAGE_PIN A25 [get_ports {fmc1_la_p_b[23]}]
set_property PACKAGE_PIN D26 [get_ports {fmc1_la_p_b[24]}]
set_property PACKAGE_PIN C25 [get_ports {fmc1_la_p_b[25]}]
set_property PACKAGE_PIN D27 [get_ports {fmc1_la_p_b[26]}]
set_property PACKAGE_PIN E28 [get_ports {fmc1_la_p_b[27]}]
set_property PACKAGE_PIN C29 [get_ports {fmc1_la_p_b[28]}]
set_property PACKAGE_PIN D29 [get_ports {fmc1_la_p_b[29]}]
set_property PACKAGE_PIN B30 [get_ports {fmc1_la_p_b[30]}]
set_property PACKAGE_PIN E29 [get_ports {fmc1_la_p_b[31]}]
set_property PACKAGE_PIN H24 [get_ports {fmc1_la_p_b[32]}]
set_property PACKAGE_PIN G28 [get_ports {fmc1_la_p_b[33]}]
set_property PACKAGE_PIN L27 [get_ports {fmc1_la_n_b[0]}]
set_property PACKAGE_PIN K25 [get_ports {fmc1_la_n_b[1]}]
set_property PACKAGE_PIN K29 [get_ports {fmc1_la_n_b[2]}]
set_property PACKAGE_PIN L28 [get_ports {fmc1_la_n_b[3]}]
set_property PACKAGE_PIN M30 [get_ports {fmc1_la_n_b[4]}]
set_property PACKAGE_PIN M27 [get_ports {fmc1_la_n_b[5]}]
set_property PACKAGE_PIN N30 [get_ports {fmc1_la_n_b[6]}]
set_property PACKAGE_PIN N26 [get_ports {fmc1_la_n_b[7]}]
set_property PACKAGE_PIN N20 [get_ports {fmc1_la_n_b[8]}]
set_property PACKAGE_PIN N22 [get_ports {fmc1_la_n_b[9]}]
set_property PACKAGE_PIN N24 [get_ports {fmc1_la_n_b[10]}]
set_property PACKAGE_PIN P22 [get_ports {fmc1_la_n_b[11]}]
set_property PACKAGE_PIN M25 [get_ports {fmc1_la_n_b[12]}]
set_property PACKAGE_PIN M23 [get_ports {fmc1_la_n_b[13]}]
set_property PACKAGE_PIN A23 [get_ports {fmc1_la_n_b[14]}]
set_property PACKAGE_PIN D23 [get_ports {fmc1_la_n_b[15]}]
set_property PACKAGE_PIN E25 [get_ports {fmc1_la_n_b[16]}]
set_property PACKAGE_PIN D24 [get_ports {fmc1_la_n_b[17]}]
set_property PACKAGE_PIN E26 [get_ports {fmc1_la_n_b[18]}]
set_property PACKAGE_PIN G24 [get_ports {fmc1_la_n_b[19]}]
set_property PACKAGE_PIN A27 [get_ports {fmc1_la_n_b[20]}]
set_property PACKAGE_PIN B24 [get_ports {fmc1_la_n_b[21]}]
set_property PACKAGE_PIN A28 [get_ports {fmc1_la_n_b[22]}]
set_property PACKAGE_PIN A26 [get_ports {fmc1_la_n_b[23]}]
set_property PACKAGE_PIN C26 [get_ports {fmc1_la_n_b[24]}]
set_property PACKAGE_PIN B25 [get_ports {fmc1_la_n_b[25]}]
set_property PACKAGE_PIN C27 [get_ports {fmc1_la_n_b[26]}]
set_property PACKAGE_PIN D28 [get_ports {fmc1_la_n_b[27]}]
set_property PACKAGE_PIN B29 [get_ports {fmc1_la_n_b[28]}]
set_property PACKAGE_PIN C30 [get_ports {fmc1_la_n_b[29]}]
set_property PACKAGE_PIN A30 [get_ports {fmc1_la_n_b[30]}]
set_property PACKAGE_PIN E30 [get_ports {fmc1_la_n_b[31]}]
set_property PACKAGE_PIN H25 [get_ports {fmc1_la_n_b[32]}]
set_property PACKAGE_PIN F28 [get_ports {fmc1_la_n_b[33]}]
set_property PACKAGE_PIN Y23 [get_ports {p2_p_b[0]}]
set_property PACKAGE_PIN Y21 [get_ports {p2_p_b[1]}]
set_property PACKAGE_PIN AB22 [get_ports {p2_p_b[2]}]
set_property PACKAGE_PIN AA22 [get_ports {p2_p_b[3]}]
set_property PACKAGE_PIN AC20 [get_ports {p2_p_b[4]}]
set_property PACKAGE_PIN AA20 [get_ports {p2_p_b[5]}]
set_property PACKAGE_PIN AB24 [get_ports {p2_p_b[6]}]
set_property PACKAGE_PIN AC22 [get_ports {p2_p_b[7]}]
set_property PACKAGE_PIN AC24 [get_ports {p2_p_b[8]}]
set_property PACKAGE_PIN AD21 [get_ports {p2_p_b[9]}]
set_property PACKAGE_PIN Y24 [get_ports {p2_n_b[0]}]
set_property PACKAGE_PIN AA21 [get_ports {p2_n_b[1]}]
set_property PACKAGE_PIN AB23 [get_ports {p2_n_b[2]}]
set_property PACKAGE_PIN AA23 [get_ports {p2_n_b[3]}]
set_property PACKAGE_PIN AC21 [get_ports {p2_n_b[4]}]
set_property PACKAGE_PIN AB20 [get_ports {p2_n_b[5]}]
set_property PACKAGE_PIN AC25 [get_ports {p2_n_b[6]}]
set_property PACKAGE_PIN AD22 [get_ports {p2_n_b[7]}]
set_property PACKAGE_PIN AD24 [get_ports {p2_n_b[8]}]
set_property PACKAGE_PIN AE21 [get_ports {p2_n_b[9]}]
set_property PACKAGE_PIN G27 [get_ports {p2_p_b[10]}]
set_property PACKAGE_PIN G29 [get_ports {p2_p_b[11]}]
set_property PACKAGE_PIN H26 [get_ports {p2_p_b[12]}]
set_property PACKAGE_PIN H30 [get_ports {p2_p_b[13]}]
set_property PACKAGE_PIN L16 [get_ports {p2_p_b[14]}]
set_property PACKAGE_PIN L15 [get_ports {p2_p_b[15]}]
set_property PACKAGE_PIN L12 [get_ports {p2_p_b[16]}]
set_property PACKAGE_PIN K13 [get_ports {p2_p_b[17]}]
set_property PACKAGE_PIN K14 [get_ports {p2_p_b[18]}]
set_property PACKAGE_PIN L11 [get_ports {p2_p_b[19]}]
set_property PACKAGE_PIN G15 [get_ports {p2_n_b[10]}]
set_property PACKAGE_PIN J12 [get_ports {p2_n_b[11]}]
set_property PACKAGE_PIN H16 [get_ports {p2_n_b[12]}]
set_property PACKAGE_PIN H12 [get_ports {p2_n_b[13]}]
set_property PACKAGE_PIN G14 [get_ports {p2_n_b[14]}]
set_property PACKAGE_PIN F13 [get_ports {p2_n_b[15]}]
set_property PACKAGE_PIN D13 [get_ports {p2_n_b[16]}]
set_property PACKAGE_PIN E13 [get_ports {p2_n_b[17]}]
set_property PACKAGE_PIN B12 [get_ports {p2_n_b[18]}]
set_property PACKAGE_PIN E11 [get_ports {p2_n_b[19]}]
set_property PACKAGE_PIN Y20 [get_ports {rst_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {rst_n_i}]
set_property PACKAGE_PIN AE23 [get_ports {vme_write_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_write_n_i}]
set_property PACKAGE_PIN AF23 [get_ports {vme_sysreset_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_sysreset_n_i}]
set_property PACKAGE_PIN AD23 [get_ports {vme_retry_oe_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_retry_oe_o}]
set_property PACKAGE_PIN AE24 [get_ports {vme_retry_n_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_retry_n_o}]
set_property PACKAGE_PIN AF22 [get_ports {vme_lword_n_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_lword_n_b}]
set_property PACKAGE_PIN AG23 [get_ports {vme_iackout_n_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_iackout_n_o}]
set_property PACKAGE_PIN AG24 [get_ports {vme_iackin_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_iackin_n_i}]
set_property PACKAGE_PIN AH24 [get_ports {vme_iack_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_iack_n_i}]
set_property PACKAGE_PIN AJ24 [get_ports {vme_gap_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_gap_i}]
set_property PACKAGE_PIN AK25 [get_ports {vme_dtack_oe_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_dtack_oe_o}]
set_property PACKAGE_PIN AE25 [get_ports {vme_dtack_n_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_dtack_n_o}]
set_property PACKAGE_PIN AF25 [get_ports {vme_ds_n_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ds_n_i[0]}]
set_property PACKAGE_PIN AK23 [get_ports {vme_ds_n_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ds_n_i[1]}]
set_property PACKAGE_PIN AK24 [get_ports {vme_data_oe_n_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_oe_n_o}]
set_property PACKAGE_PIN AG25 [get_ports {vme_data_dir_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_dir_o}]
set_property PACKAGE_PIN AH25 [get_ports {vme_berr_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_berr_o}]
set_property PACKAGE_PIN AF20 [get_ports {vme_as_n_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_as_n_i}]
set_property PACKAGE_PIN AF21 [get_ports {vme_addr_oe_n_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_oe_n_o}]
set_property PACKAGE_PIN AG22 [get_ports {vme_addr_dir_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_dir_o}]
set_property PACKAGE_PIN AH22 [get_ports {vme_irq_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[1]}]
set_property PACKAGE_PIN AJ22 [get_ports {vme_irq_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[2]}]
set_property PACKAGE_PIN AJ23 [get_ports {vme_irq_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[3]}]
set_property PACKAGE_PIN AG20 [get_ports {vme_irq_o[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[4]}]
set_property PACKAGE_PIN AH20 [get_ports {vme_irq_o[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[5]}]
set_property PACKAGE_PIN AH21 [get_ports {vme_irq_o[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[6]}]
set_property PACKAGE_PIN AJ21 [get_ports {vme_irq_o[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_irq_o[7]}]
set_property PACKAGE_PIN AK20 [get_ports {vme_ga_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[0]}]
set_property PACKAGE_PIN AK21 [get_ports {vme_ga_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[1]}]
set_property PACKAGE_PIN AE20 [get_ports {vme_ga_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[2]}]
set_property PACKAGE_PIN Y25 [get_ports {vme_ga_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[3]}]
set_property PACKAGE_PIN Y26 [get_ports {vme_ga_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_ga_i[4]}]
set_property PACKAGE_PIN AA26 [get_ports {vme_data_b[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[0]}]
set_property PACKAGE_PIN W27 [get_ports {vme_data_b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[1]}]
set_property PACKAGE_PIN W28 [get_ports {vme_data_b[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[2]}]
set_property PACKAGE_PIN Y28 [get_ports {vme_data_b[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[3]}]
set_property PACKAGE_PIN AA28 [get_ports {vme_data_b[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[4]}]
set_property PACKAGE_PIN W29 [get_ports {vme_data_b[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[5]}]
set_property PACKAGE_PIN Y29 [get_ports {vme_data_b[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[6]}]
set_property PACKAGE_PIN AA27 [get_ports {vme_data_b[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[7]}]
set_property PACKAGE_PIN AB28 [get_ports {vme_data_b[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[8]}]
set_property PACKAGE_PIN AA25 [get_ports {vme_data_b[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[9]}]
set_property PACKAGE_PIN AB25 [get_ports {vme_data_b[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[10]}]
set_property PACKAGE_PIN AC29 [get_ports {vme_data_b[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[11]}]
set_property PACKAGE_PIN AC30 [get_ports {vme_data_b[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[12]}]
set_property PACKAGE_PIN Y30 [get_ports {vme_data_b[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[13]}]
set_property PACKAGE_PIN AA30 [get_ports {vme_data_b[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[14]}]
set_property PACKAGE_PIN AD29 [get_ports {vme_data_b[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[15]}]
set_property PACKAGE_PIN AE29 [get_ports {vme_data_b[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[16]}]
set_property PACKAGE_PIN AB29 [get_ports {vme_data_b[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[17]}]
set_property PACKAGE_PIN AB30 [get_ports {vme_data_b[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[18]}]
set_property PACKAGE_PIN AD27 [get_ports {vme_data_b[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[19]}]
set_property PACKAGE_PIN AD28 [get_ports {vme_data_b[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[20]}]
set_property PACKAGE_PIN AB27 [get_ports {vme_data_b[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[21]}]
set_property PACKAGE_PIN AC27 [get_ports {vme_data_b[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[22]}]
set_property PACKAGE_PIN AG29 [get_ports {vme_data_b[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[23]}]
set_property PACKAGE_PIN AH29 [get_ports {vme_data_b[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[24]}]
set_property PACKAGE_PIN AE28 [get_ports {vme_data_b[25]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[25]}]
set_property PACKAGE_PIN AF28 [get_ports {vme_data_b[26]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[26]}]
set_property PACKAGE_PIN AK29 [get_ports {vme_data_b[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[27]}]
set_property PACKAGE_PIN AK30 [get_ports {vme_data_b[28]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[28]}]
set_property PACKAGE_PIN AE30 [get_ports {vme_data_b[29]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[29]}]
set_property PACKAGE_PIN AF30 [get_ports {vme_data_b[30]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[30]}]
set_property PACKAGE_PIN AJ28 [get_ports {vme_data_b[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_data_b[31]}]
set_property PACKAGE_PIN AJ29 [get_ports {vme_am_i[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[0]}]
set_property PACKAGE_PIN AG30 [get_ports {vme_am_i[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[1]}]
set_property PACKAGE_PIN AH30 [get_ports {vme_am_i[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[2]}]
set_property PACKAGE_PIN AC26 [get_ports {vme_am_i[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[3]}]
set_property PACKAGE_PIN AD26 [get_ports {vme_am_i[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[4]}]
set_property PACKAGE_PIN AJ27 [get_ports {vme_am_i[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_am_i[5]}]
set_property PACKAGE_PIN AK28 [get_ports {vme_addr_b[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[1]}]
set_property PACKAGE_PIN AG27 [get_ports {vme_addr_b[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[2]}]
set_property PACKAGE_PIN AG28 [get_ports {vme_addr_b[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[3]}]
set_property PACKAGE_PIN AH26 [get_ports {vme_addr_b[4]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[4]}]
set_property PACKAGE_PIN AH27 [get_ports {vme_addr_b[5]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[5]}]
set_property PACKAGE_PIN AF26 [get_ports {vme_addr_b[6]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[6]}]
set_property PACKAGE_PIN AF27 [get_ports {vme_addr_b[7]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[7]}]
set_property PACKAGE_PIN AJ26 [get_ports {vme_addr_b[8]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[8]}]
set_property PACKAGE_PIN AK26 [get_ports {vme_addr_b[9]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[9]}]
set_property PACKAGE_PIN AE26 [get_ports {vme_addr_b[10]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[10]}]
set_property PACKAGE_PIN G19 [get_ports {vme_addr_b[11]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[11]}]
set_property PACKAGE_PIN K18 [get_ports {vme_addr_b[12]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[12]}]
set_property PACKAGE_PIN J18 [get_ports {vme_addr_b[13]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[13]}]
set_property PACKAGE_PIN H20 [get_ports {vme_addr_b[14]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[14]}]
set_property PACKAGE_PIN G20 [get_ports {vme_addr_b[15]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[15]}]
set_property PACKAGE_PIN J17 [get_ports {vme_addr_b[16]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[16]}]
set_property PACKAGE_PIN H17 [get_ports {vme_addr_b[17]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[17]}]
set_property PACKAGE_PIN J19 [get_ports {vme_addr_b[18]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[18]}]
set_property PACKAGE_PIN H19 [get_ports {vme_addr_b[19]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[19]}]
set_property PACKAGE_PIN L17 [get_ports {vme_addr_b[20]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[20]}]
set_property PACKAGE_PIN L18 [get_ports {vme_addr_b[21]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[21]}]
set_property PACKAGE_PIN K19 [get_ports {vme_addr_b[22]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[22]}]
set_property PACKAGE_PIN K20 [get_ports {vme_addr_b[23]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[23]}]
set_property PACKAGE_PIN H21 [get_ports {vme_addr_b[24]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[24]}]
set_property PACKAGE_PIN H22 [get_ports {vme_addr_b[25]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[25]}]
set_property PACKAGE_PIN D21 [get_ports {vme_addr_b[26]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[26]}]
set_property PACKAGE_PIN C21 [get_ports {vme_addr_b[27]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[27]}]
set_property PACKAGE_PIN G22 [get_ports {vme_addr_b[28]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[28]}]
set_property PACKAGE_PIN F22 [get_ports {vme_addr_b[29]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[29]}]
set_property PACKAGE_PIN D22 [get_ports {vme_addr_b[30]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[30]}]
set_property PACKAGE_PIN C22 [get_ports {vme_addr_b[31]}]
set_property IOSTANDARD LVCMOS33 [get_ports {vme_addr_b[31]}]
set_property PACKAGE_PIN Y14 [get_ports {vme_noga_i[0]}]
set_property PACKAGE_PIN AK16 [get_ports {vme_noga_i[1]}]
set_property PACKAGE_PIN AK15 [get_ports {vme_noga_i[2]}]
set_property PACKAGE_PIN AG15 [get_ports {vme_noga_i[3]}]
set_property PACKAGE_PIN AH15 [get_ports {vme_noga_i[4]}]
set_property PACKAGE_PIN AH16 [get_ports {vme_use_ga_i}]
set_property PACKAGE_PIN R19 [get_ports {pll20dac_din_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_din_o}]
set_property PACKAGE_PIN W19 [get_ports {pll20dac_sclk_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sclk_o}]
set_property PACKAGE_PIN M19 [get_ports {pll20dac_sync_n_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll20dac_sync_n_o}]
set_property PACKAGE_PIN P19 [get_ports {pll25dac_din_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_din_o}]
set_property PACKAGE_PIN F23 [get_ports {pll25dac_sclk_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sclk_o}]
set_property PACKAGE_PIN G25 [get_ports {pll25dac_sync_n_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {pll25dac_sync_n_o}]
set_property PACKAGE_PIN Y2 [get_ports {sfp_txp_o}]
set_property PACKAGE_PIN Y1 [get_ports {sfp_txn_o}]
set_property PACKAGE_PIN AA4 [get_ports {sfp_rxp_i}]
set_property PACKAGE_PIN AA3 [get_ports {sfp_rxn_i}]
set_property PACKAGE_PIN AJ16 [get_ports {sfp_mod_def0_i}]
set_property PACKAGE_PIN F21 [get_ports {sfp_mod_def1_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {sfp_mod_def1_b}]
set_property PACKAGE_PIN E21 [get_ports {sfp_mod_def2_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {sfp_mod_def2_b}]
set_property PACKAGE_PIN F20 [get_ports {sfp_rate_select_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {sfp_rate_select_o}]
set_property PACKAGE_PIN AF15 [get_ports {sfp_tx_fault_i}]
set_property PACKAGE_PIN E20 [get_ports {sfp_tx_disable_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {sfp_tx_disable_o}]
set_property PACKAGE_PIN AG14 [get_ports {sfp_los_i}]
set_property PACKAGE_PIN D17 [get_ports {carrier_scl_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {carrier_scl_b}]
set_property PACKAGE_PIN D18 [get_ports {carrier_sda_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {carrier_sda_b}]
set_property PACKAGE_PIN AH17 [get_ports {pcbrev_i[0]}]
set_property PACKAGE_PIN AJ17 [get_ports {pcbrev_i[1]}]
set_property PACKAGE_PIN AE16 [get_ports {pcbrev_i[2]}]
set_property PACKAGE_PIN AF16 [get_ports {pcbrev_i[3]}]
set_property PACKAGE_PIN AJ19 [get_ports {pcbrev_i[4]}]
set_property PACKAGE_PIN E19 [get_ports {onewire_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {onewire_b}]
set_property PACKAGE_PIN D19 [get_ports {uart_rxd_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_rxd_i}]
set_property PACKAGE_PIN D16 [get_ports {uart_txd_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {uart_txd_o}]
set_property PACKAGE_PIN C16 [get_ports {spi_ncs_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_ncs_o}]
set_property PACKAGE_PIN G18 [get_ports {spi_mosi_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_mosi_o}]
set_property PACKAGE_PIN F18 [get_ports {spi_miso_i}]
set_property IOSTANDARD LVCMOS33 [get_ports {spi_miso_i}]
set_property PACKAGE_PIN C17 [get_ports {fp_led_line_oen_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_oen_o[0]}]
set_property PACKAGE_PIN B17 [get_ports {fp_led_line_oen_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_oen_o[1]}]
set_property PACKAGE_PIN G17 [get_ports {fp_led_line_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_o[0]}]
set_property PACKAGE_PIN F17 [get_ports {fp_led_line_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_line_o[1]}]
set_property PACKAGE_PIN C20 [get_ports {fp_led_column_o[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[0]}]
set_property PACKAGE_PIN B20 [get_ports {fp_led_column_o[1]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[1]}]
set_property PACKAGE_PIN A16 [get_ports {fp_led_column_o[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[2]}]
set_property PACKAGE_PIN A17 [get_ports {fp_led_column_o[3]}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_led_column_o[3]}]
set_property PACKAGE_PIN A20 [get_ports {fp_gpio1_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio1_b}]
set_property PACKAGE_PIN A21 [get_ports {fp_gpio2_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio2_b}]
set_property PACKAGE_PIN B18 [get_ports {fp_gpio3_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio3_b}]
set_property PACKAGE_PIN A18 [get_ports {fp_gpio4_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio4_b}]
set_property PACKAGE_PIN AK19 [get_ports {fp_term_en_o[1]}]
set_property PACKAGE_PIN AG19 [get_ports {fp_term_en_o[2]}]
set_property PACKAGE_PIN AH19 [get_ports {fp_term_en_o[3]}]
set_property PACKAGE_PIN AJ18 [get_ports {fp_term_en_o[4]}]
set_property PACKAGE_PIN B22 [get_ports {fp_gpio1_a2b_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio1_a2b_o}]
set_property PACKAGE_PIN A22 [get_ports {fp_gpio2_a2b_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio2_a2b_o}]
set_property PACKAGE_PIN C19 [get_ports {fp_gpio34_a2b_o}]
set_property IOSTANDARD LVCMOS33 [get_ports {fp_gpio34_a2b_o}]
set_property PACKAGE_PIN AK18 [get_ports {fp_pushbutton_n_i}]
set_property PACKAGE_PIN G12 [get_ports {fmc0_pg_i}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_pg_i}]
set_property PACKAGE_PIN A11 [get_ports {fmc0_prsnt_m2c_n_i}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_prsnt_m2c_n_i}]
set_property PACKAGE_PIN A12 [get_ports {fmc0_scl_b}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_scl_b}]
set_property PACKAGE_PIN D11 [get_ports {fmc0_sda_b}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_sda_b}]
set_property PACKAGE_PIN C11 [get_ports {fmc0_tck_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tck_o}]
set_property PACKAGE_PIN F15 [get_ports {fmc0_tms_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tms_o}]
set_property PACKAGE_PIN E16 [get_ports {fmc0_tdi_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdi_o}]
set_property PACKAGE_PIN E14 [get_ports {fmc0_tdo_i}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc0_tdo_i}]
set_property PACKAGE_PIN AD19 [get_ports {fmc1_pg_i}]
set_property PACKAGE_PIN AE19 [get_ports {fmc1_prsnt_m2c_n_i}]
set_property PACKAGE_PIN E15 [get_ports {fmc1_scl_b}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_scl_b}]
set_property PACKAGE_PIN D14 [get_ports {fmc1_sda_b}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_sda_b}]
set_property PACKAGE_PIN C14 [get_ports {fmc1_tck_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tck_o}]
set_property PACKAGE_PIN B13 [get_ports {fmc1_tms_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tms_o}]
set_property PACKAGE_PIN A13 [get_ports {fmc1_tdi_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdi_o}]
set_property PACKAGE_PIN C15 [get_ports {fmc1_tdo_i}]
set_property IOSTANDARD LVCMOS25 [get_ports {fmc1_tdo_i}]
set_property PACKAGE_PIN AF18 [get_ports {ddr_a_o[0]}]
set_property PACKAGE_PIN AG18 [get_ports {ddr_a_o[1]}]
set_property PACKAGE_PIN AF17 [get_ports {ddr_a_o[2]}]
set_property PACKAGE_PIN AG17 [get_ports {ddr_a_o[3]}]
set_property PACKAGE_PIN AD18 [get_ports {ddr_a_o[4]}]
set_property PACKAGE_PIN AE18 [get_ports {ddr_a_o[5]}]
set_property PACKAGE_PIN AD17 [get_ports {ddr_a_o[6]}]
set_property PACKAGE_PIN AD16 [get_ports {ddr_a_o[7]}]
set_property PACKAGE_PIN Y19 [get_ports {ddr_a_o[8]}]
set_property PACKAGE_PIN Y18 [get_ports {ddr_a_o[9]}]
set_property PACKAGE_PIN AA18 [get_ports {ddr_a_o[10]}]
set_property PACKAGE_PIN AB18 [get_ports {ddr_a_o[11]}]
set_property PACKAGE_PIN AB19 [get_ports {ddr_a_o[12]}]
set_property PACKAGE_PIN AC19 [get_ports {ddr_a_o[13]}]
set_property PACKAGE_PIN AB17 [get_ports {ddr_a_o[14]}]
set_property PACKAGE_PIN AC17 [get_ports {ddr_ba_o[0]}]
set_property PACKAGE_PIN AE15 [get_ports {ddr_ba_o[1]}]
set_property PACKAGE_PIN AE14 [get_ports {ddr_ba_o[2]}]
set_property PACKAGE_PIN AA15 [get_ports {ddr_cas_n_o}]
set_property PACKAGE_PIN AC15 [get_ports {ddr_ck_n_o}]
set_property PACKAGE_PIN AC16 [get_ports {ddr_ck_p_o}]
set_property PACKAGE_PIN AB15 [get_ports {ddr_cke_o}]
set_property PACKAGE_PIN AC14 [get_ports {ddr_dq_b[0]}]
set_property PACKAGE_PIN AD14 [get_ports {ddr_dq_b[1]}]
set_property PACKAGE_PIN AA17 [get_ports {ddr_dq_b[2]}]
set_property PACKAGE_PIN AA16 [get_ports {ddr_dq_b[3]}]
set_property PACKAGE_PIN Y16 [get_ports {ddr_dq_b[4]}]
set_property PACKAGE_PIN Y15 [get_ports {ddr_dq_b[5]}]
set_property PACKAGE_PIN AB14 [get_ports {ddr_dq_b[6]}]
set_property PACKAGE_PIN Y13 [get_ports {ddr_dq_b[7]}]
set_property PACKAGE_PIN AA12 [get_ports {ddr_dq_b[8]}]
set_property PACKAGE_PIN AB12 [get_ports {ddr_dq_b[9]}]
set_property PACKAGE_PIN AA8 [get_ports {ddr_dq_b[10]}]
set_property PACKAGE_PIN AB8 [get_ports {ddr_dq_b[11]}]
set_property PACKAGE_PIN AB9 [get_ports {ddr_dq_b[12]}]
set_property PACKAGE_PIN AC9 [get_ports {ddr_dq_b[13]}]
set_property PACKAGE_PIN Y11 [get_ports {ddr_dq_b[14]}]
set_property PACKAGE_PIN Y10 [get_ports {ddr_dq_b[15]}]
set_property PACKAGE_PIN AA11 [get_ports {ddr_dq_b[16]}]
set_property PACKAGE_PIN AA10 [get_ports {ddr_dq_b[17]}]
set_property PACKAGE_PIN AA13 [get_ports {ddr_dq_b[18]}]
set_property PACKAGE_PIN AB13 [get_ports {ddr_dq_b[19]}]
set_property PACKAGE_PIN AB10 [get_ports {ddr_dq_b[20]}]
set_property PACKAGE_PIN AC10 [get_ports {ddr_dq_b[21]}]
set_property PACKAGE_PIN AD8 [get_ports {ddr_dq_b[22]}]
set_property PACKAGE_PIN AE8 [get_ports {ddr_dq_b[23]}]
set_property PACKAGE_PIN AC12 [get_ports {ddr_dq_b[24]}]
set_property PACKAGE_PIN AC11 [get_ports {ddr_dq_b[25]}]
set_property PACKAGE_PIN AD9 [get_ports {ddr_dq_b[26]}]
set_property PACKAGE_PIN AE9 [get_ports {ddr_dq_b[27]}]
set_property PACKAGE_PIN AE11 [get_ports {ddr_dq_b[28]}]
set_property PACKAGE_PIN AF11 [get_ports {ddr_dq_b[29]}]
set_property PACKAGE_PIN AD12 [get_ports {ddr_dq_b[30]}]
set_property PACKAGE_PIN AD11 [get_ports {ddr_dq_b[31]}]
set_property PACKAGE_PIN AG10 [get_ports {ddr_dq_b[32]}]
set_property PACKAGE_PIN AH10 [get_ports {ddr_dq_b[33]}]
set_property PACKAGE_PIN AE10 [get_ports {ddr_dq_b[34]}]
set_property PACKAGE_PIN AF10 [get_ports {ddr_dq_b[35]}]
set_property PACKAGE_PIN AJ9 [get_ports {ddr_dq_b[36]}]
set_property PACKAGE_PIN AK9 [get_ports {ddr_dq_b[37]}]
set_property PACKAGE_PIN AG9 [get_ports {ddr_dq_b[38]}]
set_property PACKAGE_PIN AH9 [get_ports {ddr_dq_b[39]}]
set_property PACKAGE_PIN AK11 [get_ports {ddr_dq_b[40]}]
set_property PACKAGE_PIN AK10 [get_ports {ddr_dq_b[41]}]
set_property PACKAGE_PIN AH11 [get_ports {ddr_dq_b[42]}]
set_property PACKAGE_PIN AJ11 [get_ports {ddr_dq_b[43]}]
set_property PACKAGE_PIN AE13 [get_ports {ddr_dq_b[44]}]
set_property PACKAGE_PIN AF13 [get_ports {ddr_dq_b[45]}]
set_property PACKAGE_PIN AK14 [get_ports {ddr_dq_b[46]}]
set_property PACKAGE_PIN AK13 [get_ports {ddr_dq_b[47]}]
set_property PACKAGE_PIN AH14 [get_ports {ddr_dq_b[48]}]
set_property PACKAGE_PIN AJ14 [get_ports {ddr_dq_b[49]}]
set_property PACKAGE_PIN AJ13 [get_ports {ddr_dq_b[50]}]
set_property PACKAGE_PIN AJ12 [get_ports {ddr_dq_b[51]}]
set_property PACKAGE_PIN AF12 [get_ports {ddr_dq_b[52]}]
set_property PACKAGE_PIN AG12 [get_ports {ddr_dq_b[53]}]
set_property PACKAGE_PIN AG13 [get_ports {ddr_dq_b[54]}]
set_property PACKAGE_PIN AH12 [get_ports {ddr_dq_b[55]}]
set_property PACKAGE_PIN AD13 [get_ports {ddr_dq_b[56]}]
set_property PACKAGE_PIN AC6 [get_ports {ddr_dq_b[57]}]
set_property PACKAGE_PIN AD4 [get_ports {ddr_dq_b[58]}]
set_property PACKAGE_PIN AD3 [get_ports {ddr_dq_b[59]}]
set_property PACKAGE_PIN AC2 [get_ports {ddr_dq_b[60]}]
set_property PACKAGE_PIN AC1 [get_ports {ddr_dq_b[61]}]
set_property PACKAGE_PIN AD2 [get_ports {ddr_dq_b[62]}]
set_property PACKAGE_PIN AD1 [get_ports {ddr_dq_b[63]}]
set_property PACKAGE_PIN AC4 [get_ports {ddr_dqs_n_b[0]}]
set_property PACKAGE_PIN AE6 [get_ports {ddr_dqs_n_b[1]}]
set_property PACKAGE_PIN AD7 [get_ports {ddr_dqs_n_b[2]}]
set_property PACKAGE_PIN AF2 [get_ports {ddr_dqs_n_b[3]}]
set_property PACKAGE_PIN AF1 [get_ports {ddr_dqs_n_b[4]}]
set_property PACKAGE_PIN AG3 [get_ports {ddr_dqs_n_b[5]}]
set_property PACKAGE_PIN AE3 [get_ports {ddr_dqs_n_b[6]}]
set_property PACKAGE_PIN AF5 [get_ports {ddr_dqs_n_b[7]}]
set_property PACKAGE_PIN AC5 [get_ports {ddr_dqs_p_b[0]}]
set_property PACKAGE_PIN AD6 [get_ports {ddr_dqs_p_b[1]}]
set_property PACKAGE_PIN AC7 [get_ports {ddr_dqs_p_b[2]}]
set_property PACKAGE_PIN AF3 [get_ports {ddr_dqs_p_b[3]}]
set_property PACKAGE_PIN AE1 [get_ports {ddr_dqs_p_b[4]}]
set_property PACKAGE_PIN AG4 [get_ports {ddr_dqs_p_b[5]}]
set_property PACKAGE_PIN AE4 [get_ports {ddr_dqs_p_b[6]}]
set_property PACKAGE_PIN AE5 [get_ports {ddr_dqs_p_b[7]}]
set_property PACKAGE_PIN AF6 [get_ports {ddr_odt_o}]
set_property PACKAGE_PIN AG5 [get_ports {ddr_ras_n_o}]
set_property PACKAGE_PIN AH4 [get_ports {ddr_reset_n_o}]
set_property PACKAGE_PIN AJ4 [get_ports {ddr_rzq_b}]
set_property PACKAGE_PIN AH6 [get_ports {ddr_dm_o[0]}]
set_property PACKAGE_PIN AH5 [get_ports {ddr_dm_o[1]}]
set_property PACKAGE_PIN AG2 [get_ports {ddr_dm_o[2]}]
set_property PACKAGE_PIN AH1 [get_ports {ddr_dm_o[3]}]
set_property PACKAGE_PIN AH2 [get_ports {ddr_dm_o[4]}]
set_property PACKAGE_PIN AJ2 [get_ports {ddr_dm_o[5]}]
set_property PACKAGE_PIN AJ1 [get_ports {ddr_dm_o[6]}]
set_property PACKAGE_PIN AK1 [get_ports {ddr_dm_o[7]}]
set_property PACKAGE_PIN AJ3 [get_ports {ddr_we_n_o}]
set_property PACKAGE_PIN AK3 [get_ports {ddr_cs_n_o}]
set_property PACKAGE_PIN B19 [get_ports {si57x_scl_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {si57x_scl_b}]
set_property PACKAGE_PIN E18 [get_ports {si57x_sda_b}]
set_property IOSTANDARD LVCMOS33 [get_ports {si57x_sda_b}]
set_property PACKAGE_PIN B15 [get_ports {si57x_oe_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {si57x_oe_o}]
set_property PACKAGE_PIN B14 [get_ports {si57x_tune_o}]
set_property IOSTANDARD LVCMOS25 [get_ports {si57x_tune_o}]
hdl/syn/svec7_test/svec7_pins.py deleted 100755 → 0
View file @ 90348ce2
#!/usr/bin/python
import sys
import re
import csv
class FPGAPin:
def __init__(self, name, bank, pad):
self.name = name
self.bank = int(bank)
self.pad = pad
self.in_use = False
def differ_by_single_letter(s1, s2):
if len(s1) != len(s2):
return False;
ch = 0
last = None
for i in range(0, len(s1)):
if s1[i] != s2[i]:
ch += 1
last = i
if ch == 1:
return ( s1[last], s2[last] )
else:
return False
class FPGAPinFile:
def __init__(self, filename):
self.pins = []
for l in open(filename).readlines():
tok = l.split()
if len(tok) < 8:
continue
if tok[6] == "HR" or tok[6] == "HP" or tok[6] == "GTX":
self.pins += [ FPGAPin(tok[1], tok[3], tok[0])]
def find_pin(self, name, banks=None):
rv = None
for p in self.pins:
if banks and not p.bank in banks:
continue
if p.name == name:
return p
return None
def first_free_pin(self, banks=None):
rv = None
for p in self.pins:
if p.in_use:
continue
if banks and not p.bank in banks:
continue
return p
def first_free_diff_pair(self, banks=None):
rv = None
for p_ref in self.pins:
if p_ref.in_use:
continue
id1 = re.match("IO_L(\d+)([PN]).+", p_ref.name)
if id1 == None:
continue
p_ref_n = id1.group(1)
p_ref_pol = id1.group(2)
for p in self.pins:
if p.in_use:
continue
if banks and not p.bank in banks:
continue
if p.bank != p_ref.bank:
continue
id2 = re.match("IO_L(\d+)([PN]).+", p.name)
if id2 == None:
continue
p_n = id2.group(1)
p_pol = id2.group(2)
if p_ref_n == p_n and p_ref_pol != p_pol:
# print("MAtch!")
if p_ref_pol.lower() == 'p':
return ( p_ref, p )
else:
return ( p, p_ref )
return rv
def free_pins_in_banks(self, banks):
for b in banks:
cnt_free = 0
cnt_total = 0
for p in self.pins:
if p.bank == b:
cnt_total += 1
if not p.in_use:
cnt_free += 1
print("Bank %d: %d total, %d free pins" % (b, cnt_total, cnt_free))
class Signal:
def __init__(self, name, range_hi = 0, range_lo = 0, diff=False, force=None, banks=None, iostandard=None):
self.name = name
self.range_hi = range_hi
self.range_lo = range_lo
self.diff = diff
self.force = force
self.banks = banks
self.iostandard = iostandard
self.done=False
self.pair=None
self.fpga_pins={}
class TopLevelSignals:
def __init__(self):
self.signals=[]
def add( self, name, range_hi = 0, range_lo = 0, diff=False, force=None, banks=None, iostandard=None):
self.signals += [ Signal( name, range_hi, range_lo, diff, force, banks, iostandard)]
def print_stats(self):
total = 0
for s in self.signals:
total += (s.range_hi + 1 - s.range_lo)
print("Total signals : %d", total)
def find_diff_pair(self, p_ref):
rv = None
for p in self.signals:
ch = 0
#print("%s %s", p.name, p_ref.name)
if len(p.name) != len(p_ref.name):
continue
for i in range(0, len(p_ref.name)):
#print ( p.name[i].lower() )
if p.name[i].lower() != p_ref.name[i].lower():
ch+=1
if p.name[i].lower()=="p" and p_ref.name[i].lower()=="n":
#print("MATCH")
rv = (p, p_ref)
elif p.name[i].lower()=="n" and p_ref.name[i].lower()=="p":
#print("MATCH2")
rv = (p_ref, p)
if ch == 1 and rv:
return rv
return rv
fpga_pins = FPGAPinFile( 'xc7k325tffg900pkg.txt')
signals = TopLevelSignals()
banks_hp = [32, 33, 34]
banks_hr_33 = [12, 13, 17]
banks_hr_25 = [14, 15, 16, 18]
banks_hr_all = [12, 13, 14, 15, 16, 17, 18]
signals.add("clk_20m_vcxo_i", force="IO_L13P_T2_MRCC_13")
signals.add("clk_62m5_pllref_p_i", force="IO_L12P_T1_MRCC_12", iostandard="LVDS")
signals.add("clk_62m5_pllref_n_i", force="IO_L12N_T1_MRCC_12", iostandard="LVDS")
signals.add("clk_125m_gtx_n_i", force="MGTREFCLK0N_115")
signals.add("clk_125m_gtx_p_i", force="MGTREFCLK0P_115")
signals.add("clk_fpga2_p_i", force="IO_L13P_T2_MRCC_12", iostandard="LVDS")
signals.add("clk_fpga2_n_i", force="IO_L13N_T2_MRCC_12", iostandard="LVDS")
signals.add("clk_si57x_p_i", force="IO_L12P_T1_MRCC_13", iostandard="LVDS")
signals.add("clk_si57x_n_i", force="IO_L12N_T1_MRCC_13", iostandard="LVDS")
signals.add("fmc0_clk_m2c_p_i[0]", force="IO_L12P_T1_MRCC_AD5P_15", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc0_clk_m2c_n_i[0]", force="IO_L12N_T1_MRCC_AD5N_15", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc0_clk_m2c_p_i[1]", force="IO_L13P_T2_MRCC_15", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc0_clk_m2c_n_i[1]", force="IO_L13N_T2_MRCC_15", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc1_clk_m2c_p_i[0]", force="IO_L12P_T1_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc1_clk_m2c_n_i[0]", force="IO_L12N_T1_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc1_clk_m2c_p_i[1]", force="IO_L13P_T2_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc1_clk_m2c_n_i[1]", force="IO_L13P_T2_MRCC_16", banks=banks_hr_25, iostandard="LVDS_25")
signals.add("fmc0_la_p_b", 33, 0, diff=True, banks=banks_hr_25)
signals.add("fmc0_la_n_b", 33, 0, diff=True, banks=banks_hr_25)
signals.add("fmc1_la_p_b", 33, 0, diff=True, banks=banks_hr_25)
signals.add("fmc1_la_n_b", 33, 0, diff=True, banks=banks_hr_25)
signals.add("p2_p_b", 9, 0, diff=True, banks=banks_hr_33)
signals.add("p2_n_b", 9, 0, diff=True, banks=banks_hr_33)
signals.add("p2_p_b", 19, 10, diff=True, banks=banks_hr_25)
signals.add("p2_n_b", 19, 10, diff=True, banks=banks_hr_25)
signals.add("rst_n_i", banks = banks_hr_33)
signals.add("vme_write_n_i", banks = banks_hr_33)
signals.add("vme_sysreset_n_i", banks = banks_hr_33)
signals.add("vme_retry_oe_o", banks = banks_hr_33)
signals.add("vme_retry_n_o", banks = banks_hr_33)
signals.add("vme_lword_n_b", banks = banks_hr_33)
signals.add("vme_iackout_n_o", banks = banks_hr_33)
signals.add("vme_iackin_n_i", banks = banks_hr_33)
signals.add("vme_iack_n_i", banks = banks_hr_33)
signals.add("vme_gap_i", banks = banks_hr_33)
signals.add("vme_dtack_oe_o", banks = banks_hr_33)
signals.add("vme_dtack_n_o", banks = banks_hr_33)
signals.add("vme_ds_n_i", 1, 0, banks = banks_hr_33)
signals.add("vme_data_oe_n_o", banks = banks_hr_33)
signals.add("vme_data_dir_o", banks = banks_hr_33)
signals.add("vme_berr_o", banks = banks_hr_33)
signals.add("vme_as_n_i", banks = banks_hr_33)
signals.add("vme_addr_oe_n_o", banks = banks_hr_33)
signals.add("vme_addr_dir_o", banks = banks_hr_33)
signals.add("vme_irq_o", 7, 1, banks = banks_hr_33)
signals.add("vme_ga_i", 4, 0, banks = banks_hr_33)
signals.add("vme_data_b", 31, 0, banks = banks_hr_33)
signals.add("vme_am_i", 5, 0, banks = banks_hr_33)
signals.add("vme_addr_b", 31, 1, banks = banks_hr_33)
signals.add("vme_noga_i", 4, 0, banks = banks_hp)
signals.add("vme_use_ga_i", banks = banks_hp)
signals.add("pll20dac_din_o", banks=banks_hr_all),
signals.add("pll20dac_sclk_o", banks=banks_hr_all),
signals.add("pll20dac_sync_n_o", banks=banks_hr_all),
signals.add("pll25dac_din_o", banks=banks_hr_all),
signals.add("pll25dac_sclk_o", banks=banks_hr_all),
signals.add("pll25dac_sync_n_o", banks=banks_hr_all),
signals.add("sfp_txp_o", force="MGTXTXP0_115")
signals.add("sfp_txn_o", force="MGTXTXN0_115")
signals.add("sfp_rxp_i", force="MGTXRXP0_115")
signals.add("sfp_rxn_i", force="MGTXRXN0_115")
signals.add("sfp_mod_def0_i", banks=banks_hp),
signals.add("sfp_mod_def1_b", banks=banks_hr_all),
signals.add("sfp_mod_def2_b", banks=banks_hr_all),
signals.add("sfp_rate_select_o", banks=banks_hr_all),
signals.add("sfp_tx_fault_i", banks=banks_hp),
signals.add("sfp_tx_disable_o", banks=banks_hr_all),
signals.add("sfp_los_i", banks=banks_hp),
signals.add("carrier_scl_b", banks=banks_hr_all),
signals.add("carrier_sda_b", banks=banks_hr_all),
signals.add("pcbrev_i", 4, 0, banks=banks_hp),
signals.add("onewire_b", banks=banks_hr_all),
signals.add("uart_rxd_i", banks=banks_hr_all),
signals.add("uart_txd_o", banks=banks_hr_all),
signals.add("spi_ncs_o", banks=banks_hr_all),
signals.add("spi_mosi_o", banks=banks_hr_all),
signals.add("spi_miso_i", banks=banks_hr_all),
signals.add("fp_led_line_oen_o", 1,0, banks=banks_hr_all)
signals.add("fp_led_line_o", 1,0, banks=banks_hr_all)
signals.add("fp_led_column_o", 3,0, banks=banks_hr_all)
signals.add("fp_gpio1_b", banks=banks_hr_all),
signals.add("fp_gpio2_b", banks=banks_hr_all),
signals.add("fp_gpio3_b", banks=banks_hr_all),
signals.add("fp_gpio4_b", banks=banks_hr_all),
signals.add("fp_term_en_o",4, 1, banks=banks_hp)
signals.add("fp_gpio1_a2b_o", banks=banks_hr_all)
signals.add("fp_gpio2_a2b_o", banks=banks_hr_all)
signals.add("fp_gpio34_a2b_o", banks=banks_hr_all)
signals.add("fp_pushbutton_n_i", banks=banks_hp),
signals.add("fmc0_pg_i", banks=banks_hr_25)
signals.add("fmc0_prsnt_m2c_n_i", banks=banks_hr_25)
signals.add("fmc0_scl_b", banks=banks_hr_25)
signals.add("fmc0_sda_b", banks=banks_hr_25)
signals.add("fmc0_tck_o", banks=banks_hr_25)
signals.add("fmc0_tms_o", banks=banks_hr_25)
signals.add("fmc0_tdi_o", banks=banks_hr_25)
signals.add("fmc0_tdo_i", banks=banks_hr_25)
signals.add("fmc1_pg_i", banks=banks_hp)
signals.add("fmc1_prsnt_m2c_n_i", banks=banks_hp)
signals.add("fmc1_scl_b", banks=banks_hr_25)
signals.add("fmc1_sda_b", banks=banks_hr_25)
signals.add("fmc1_tck_o", banks=banks_hr_25)
signals.add("fmc1_tms_o", banks=banks_hr_25)
signals.add("fmc1_tdi_o", banks=banks_hr_25)
signals.add("fmc1_tdo_i", banks=banks_hr_25)
signals.add("ddr_a_o", 14, 0, banks=banks_hp)
signals.add("ddr_ba_o", 2, 0, banks=banks_hp)
signals.add("ddr_cas_n_o", banks=banks_hp)
signals.add("ddr_ck_n_o",diff=True, banks=banks_hp)
signals.add("ddr_ck_p_o",diff=True, banks=banks_hp)
signals.add("ddr_cke_o", banks=banks_hp)
signals.add("ddr_dq_b", 63, 0, banks=banks_hp)
signals.add("ddr_dqs_n_b", 7, 0, diff=True, banks=banks_hp)
signals.add("ddr_dqs_p_b", 7, 0, diff=True, banks=banks_hp)
signals.add("ddr_odt_o", banks=banks_hp)
signals.add("ddr_ras_n_o", banks=banks_hp)
signals.add("ddr_reset_n_o", banks=banks_hp)
signals.add("ddr_rzq_b", banks=banks_hp)
signals.add("ddr_dm_o", 7, 0, banks=banks_hp)
signals.add("ddr_we_n_o", banks=banks_hp)
signals.add("ddr_cs_n_o", banks=banks_hp)
signals.add("si57x_scl_b", banks=banks_hr_all)
signals.add("si57x_sda_b", banks=banks_hr_all)
signals.add("si57x_oe_o", banks=banks_hr_all)
signals.add("si57x_tune_o", banks=banks_hr_all)
for s in signals.signals:
if s.done:
continue
if s.force:
p = fpga_pins.find_pin(s.force)
if p == None:
print("!!!! unknown forced pin")
print("Force: %-30s -> %-20s" % (s.name, s.force))
s.done = True
s.fpga_pins[0] = p
for s in signals.signals:
if s.done:
continue
if s.diff:
for idx in range( s.range_lo, s.range_hi + 1 ):
#print("Do Signal %s[%d]" % (s.name, idx))
pair = signals.find_diff_pair( s )
f_pair = fpga_pins.first_free_diff_pair( banks = s.banks )
if f_pair == None:
print("!!!! Unable to fit diff pair: %s" % s.name)
break
pair[0].done = True
pair[1].done = True
f_pair[0].in_use = True
f_pair[1].in_use = True
pair[0].fpga_pins[idx] = f_pair[0]
pair[1].fpga_pins[idx] = f_pair[1]
#print("DP %s[%d] %s %s %d" %( pair[0].name, idx, f_pair[0].name, f_pair[0].pad, f_pair[0].bank ) )
#print("DN %s[%d] %s %s %d" %( pair[1].name, idx, f_pair[1].name, f_pair[1].pad, f_pair[1].bank ) )
else:
for idx in range( s.range_lo, s.range_hi + 1 ):
f_pin = fpga_pins.first_free_pin( banks = s.banks )
if f_pin == None:
print("!!!! Unable to fit pin: %s" % s.name)
break
s.done = True
f_pin.in_use = True
s.fpga_pins[idx] = f_pin
#print("D %s[%d] %s %s %d" %( s.name, idx, f_pin.name, f_pin.pad, f_pin.bank ) )
f_xdc = open("out.xdc","wb")
for s in signals.signals:
for idx in range( s.range_lo, s.range_hi + 1 ):
if s.range_lo == 0 and s.range_hi == 0:
rstring = ""
else:
rstring = "[%d]" % idx
f_xdc.write("set_property PACKAGE_PIN %s [get_ports {%s%s}]\n" % (s.fpga_pins[idx].pad, s.name, rstring))
if not s.diff:
iostd = None
if s.iostandard != None:
iostd = s.iostandard
elif s.fpga_pins[idx].bank in banks_hr_33:
iostd = "LVCMOS33"
elif s.fpga_pins[idx].bank in banks_hr_25:
iostd = "LVCMOS25"
if iostd:
f_xdc.write("set_property IOSTANDARD %s [get_ports {%s%s}]\n"% (iostd, s.name, rstring))
fpga_pins.free_pins_in_banks([12,13,14,15,16,17,18,32,33,34])
signals.print_stats()
f_xdc.close()
\ No newline at end of file
hdl/syn/svec7_test/xc7k160tfbg676pkg.txt deleted 100644 → 0
View file @ 90348ce2
Device/Package xc7k160tfbg676 8/10/2011 13:58:27
Pin Pin Name Memory Byte Group Bank VCCAUX Group Super Logic Region I/O Type No-Connect
R11 DXN_0 NA 0 NA NA CONFIG NA
M12 VCCADC_0 NA 0 NA NA CONFIG NA
M11 GNDADC_0 NA 0 NA NA CONFIG NA
R12 DXP_0 NA 0 NA NA CONFIG NA
N11 VREFN_0 NA 0 NA NA CONFIG NA
P12 VREFP_0 NA 0 NA NA CONFIG NA
N12 VP_0 NA 0 NA NA CONFIG NA
P11 VN_0 NA 0 NA NA CONFIG NA
E8 VCCBATT_0 NA 0 NA NA CONFIG NA
C8 CCLK_0 NA 0 NA NA CONFIG NA
L8 TCK_0 NA 0 NA NA CONFIG NA
N8 TMS_0 NA 0 NA NA CONFIG NA
R7 TDO_0 NA 0 NA NA CONFIG NA
R6 TDI_0 NA 0 NA NA CONFIG NA
G7 INIT_B_0 NA 0 NA NA CONFIG NA
P6 PROGRAM_B_0 NA 0 NA NA CONFIG NA
P7 CFGBVS_0 NA 0 NA NA CONFIG NA
J7 DONE_0 NA 0 NA NA CONFIG NA
P5 M2_0 NA 0 NA NA CONFIG NA
T5 M0_0 NA 0 NA NA CONFIG NA
T2 M1_0 NA 0 NA NA CONFIG NA
U21 IO_0_12 NA 12 NA NA HR 7K70T
U22 IO_L1P_T0_12 0 12 NA NA HR 7K70T
V22 IO_L1N_T0_12 0 12 NA NA HR 7K70T
U24 IO_L2P_T0_12 0 12 NA NA HR 7K70T
U25 IO_L2N_T0_12 0 12 NA NA HR 7K70T
V23 IO_L3P_T0_DQS_12 0 12 NA NA HR 7K70T
V24 IO_L3N_T0_DQS_12 0 12 NA NA HR 7K70T
U26 IO_L4P_T0_12 0 12 NA NA HR 7K70T
V26 IO_L4N_T0_12 0 12 NA NA HR 7K70T
W25 IO_L5P_T0_12 0 12 NA NA HR 7K70T
W26 IO_L5N_T0_12 0 12 NA NA HR 7K70T
V21 IO_L6P_T0_12 0 12 NA NA HR 7K70T
W21 IO_L6N_T0_VREF_12 0 12 NA NA HR 7K70T
AA25 IO_L7P_T1_12 1 12 NA NA HR 7K70T
AB25 IO_L7N_T1_12 1 12 NA NA HR 7K70T
W23 IO_L8P_T1_12 1 12 NA NA HR 7K70T
W24 IO_L8N_T1_12 1 12 NA NA HR 7K70T
AB26 IO_L9P_T1_DQS_12 1 12 NA NA HR 7K70T
AC26 IO_L9N_T1_DQS_12 1 12 NA NA HR 7K70T
Y25 IO_L10P_T1_12 1 12 NA NA HR 7K70T
Y26 IO_L10N_T1_12 1 12 NA NA HR 7K70T
AA23 IO_L11P_T1_SRCC_12 1 12 NA NA HR 7K70T
AB24 IO_L11N_T1_SRCC_12 1 12 NA NA HR 7K70T
Y23 IO_L12P_T1_MRCC_12 1 12 NA NA HR 7K70T
AA24 IO_L12N_T1_MRCC_12 1 12 NA NA HR 7K70T
Y22 IO_L13P_T2_MRCC_12 2 12 NA NA HR 7K70T
AA22 IO_L13N_T2_MRCC_12 2 12 NA NA HR 7K70T
AC23 IO_L14P_T2_SRCC_12 2 12 NA NA HR 7K70T
AC24 IO_L14N_T2_SRCC_12 2 12 NA NA HR 7K70T
W20 IO_L15P_T2_DQS_12 2 12 NA NA HR 7K70T
Y21 IO_L15N_T2_DQS_12 2 12 NA NA HR 7K70T
AD23 IO_L16P_T2_12 2 12 NA NA HR 7K70T
AD24 IO_L16N_T2_12 2 12 NA NA HR 7K70T
AB22 IO_L17P_T2_12 2 12 NA NA HR 7K70T
AC22 IO_L17N_T2_12 2 12 NA NA HR 7K70T
AB21 IO_L18P_T2_12 2 12 NA NA HR 7K70T
AC21 IO_L18N_T2_12 2 12 NA NA HR 7K70T
AD21 IO_L19P_T3_12 3 12 NA NA HR 7K70T
AE21 IO_L19N_T3_VREF_12 3 12 NA NA HR 7K70T
AF24 IO_L20P_T3_12 3 12 NA NA HR 7K70T
AF25 IO_L20N_T3_12 3 12 NA NA HR 7K70T
AD26 IO_L21P_T3_DQS_12 3 12 NA NA HR 7K70T
AE26 IO_L21N_T3_DQS_12 3 12 NA NA HR 7K70T
AE23 IO_L22P_T3_12 3 12 NA NA HR 7K70T
AF23 IO_L22N_T3_12 3 12 NA NA HR 7K70T
AD25 IO_L23P_T3_12 3 12 NA NA HR 7K70T
AE25 IO_L23N_T3_12 3 12 NA NA HR 7K70T
AE22 IO_L24P_T3_12 3 12 NA NA HR 7K70T
AF22 IO_L24N_T3_12 3 12 NA NA HR 7K70T
Y20 IO_25_12 NA 12 NA NA HR 7K70T
N16 IO_0_13 NA 13 NA NA HR NA
K25 IO_L1P_T0_13 0 13 NA NA HR NA
K26 IO_L1N_T0_13 0 13 NA NA HR NA
R26 IO_L2P_T0_13 0 13 NA NA HR NA
P26 IO_L2N_T0_13 0 13 NA NA HR NA
M25 IO_L3P_T0_DQS_13 0 13 NA NA HR NA
L25 IO_L3N_T0_DQS_13 0 13 NA NA HR NA
P24 IO_L4P_T0_13 0 13 NA NA HR NA
N24 IO_L4N_T0_13 0 13 NA NA HR NA
N26 IO_L5P_T0_13 0 13 NA NA HR NA
M26 IO_L5N_T0_13 0 13 NA NA HR NA
R25 IO_L6P_T0_13 0 13 NA NA HR NA
P25 IO_L6N_T0_VREF_13 0 13 NA NA HR NA
N19 IO_L7P_T1_13 1 13 NA NA HR NA
M20 IO_L7N_T1_13 1 13 NA NA HR NA
M24 IO_L8P_T1_13 1 13 NA NA HR NA
L24 IO_L8N_T1_13 1 13 NA NA HR NA
P19 IO_L9P_T1_DQS_13 1 13 NA NA HR NA
P20 IO_L9N_T1_DQS_13 1 13 NA NA HR NA
M21 IO_L10P_T1_13 1 13 NA NA HR NA
M22 IO_L10N_T1_13 1 13 NA NA HR NA
P23 IO_L11P_T1_SRCC_13 1 13 NA NA HR NA
N23 IO_L11N_T1_SRCC_13 1 13 NA NA HR NA
N21 IO_L12P_T1_MRCC_13 1 13 NA NA HR NA
N22 IO_L12N_T1_MRCC_13 1 13 NA NA HR NA
R21 IO_L13P_T2_MRCC_13 2 13 NA NA HR NA
P21 IO_L13N_T2_MRCC_13 2 13 NA NA HR NA
R22 IO_L14P_T2_SRCC_13 2 13 NA NA HR NA
R23 IO_L14N_T2_SRCC_13 2 13 NA NA HR NA
T24 IO_L15P_T2_DQS_13 2 13 NA NA HR NA
T25 IO_L15N_T2_DQS_13 2 13 NA NA HR NA
T20 IO_L16P_T2_13 2 13 NA NA HR NA
R20 IO_L16N_T2_13 2 13 NA NA HR NA
T22 IO_L17P_T2_13 2 13 NA NA HR NA
T23 IO_L17N_T2_13 2 13 NA NA HR NA
U19 IO_L18P_T2_13 2 13 NA NA HR NA
U20 IO_L18N_T2_13 2 13 NA NA HR NA
T18 IO_L19P_T3_13 3 13 NA NA HR NA
T19 IO_L19N_T3_VREF_13 3 13 NA NA HR NA
P16 IO_L20P_T3_13 3 13 NA NA HR NA
N17 IO_L20N_T3_13 3 13 NA NA HR NA
R16 IO_L21P_T3_DQS_13 3 13 NA NA HR NA
R17 IO_L21N_T3_DQS_13 3 13 NA NA HR NA
N18 IO_L22P_T3_13 3 13 NA NA HR NA
M19 IO_L22N_T3_13 3 13 NA NA HR NA
U17 IO_L23P_T3_13 3 13 NA NA HR NA
T17 IO_L23N_T3_13 3 13 NA NA HR NA
R18 IO_L24P_T3_13 3 13 NA NA HR NA
P18 IO_L24N_T3_13 3 13 NA NA HR NA
U16 IO_25_13 NA 13 NA NA HR NA
K21 IO_0_14 NA 14 NA NA HR NA
B24 IO_L1P_T0_D00_MOSI_14 0 14 NA NA HR NA
A25 IO_L1N_T0_D01_DIN_14 0 14 NA NA HR NA
B22 IO_L2P_T0_D02_14 0 14 NA NA HR NA
A22 IO_L2N_T0_D03_14 0 14 NA NA HR NA
B25 IO_L3P_T0_DQS_PUDC_B_14 0 14 NA NA HR NA
B26 IO_L3N_T0_DQS_EMCCLK_14 0 14 NA NA HR NA
A23 IO_L4P_T0_D04_14 0 14 NA NA HR NA
A24 IO_L4N_T0_D05_14 0 14 NA NA HR NA
D26 IO_L5P_T0_D06_14 0 14 NA NA HR NA
C26 IO_L5N_T0_D07_14 0 14 NA NA HR NA
C23 IO_L6P_T0_FCS_B_14 0 14 NA NA HR NA
C24 IO_L6N_T0_D08_VREF_14 0 14 NA NA HR NA
D21 IO_L7P_T1_D09_14 1 14 NA NA HR NA
C22 IO_L7N_T1_D10_14 1 14 NA NA HR NA
B20 IO_L8P_T1_D11_14 1 14 NA NA HR NA
A20 IO_L8N_T1_D12_14 1 14 NA NA HR NA
E21 IO_L9P_T1_DQS_14 1 14 NA NA HR NA
E22 IO_L9N_T1_DQS_D13_14 1 14 NA NA HR NA
C21 IO_L10P_T1_D14_14 1 14 NA NA HR NA
B21 IO_L10N_T1_D15_14 1 14 NA NA HR NA
D23 IO_L11P_T1_SRCC_14 1 14 NA NA HR NA
D24 IO_L11N_T1_SRCC_14 1 14 NA NA HR NA
F22 IO_L12P_T1_MRCC_14 1 14 NA NA HR NA
E23 IO_L12N_T1_MRCC_14 1 14 NA NA HR NA
G22 IO_L13P_T2_MRCC_14 2 14 NA NA HR NA
F23 IO_L13N_T2_MRCC_14 2 14 NA NA HR NA
G24 IO_L14P_T2_SRCC_14 2 14 NA NA HR NA
F24 IO_L14N_T2_SRCC_14 2 14 NA NA HR NA
E25 IO_L15P_T2_DQS_RDWR_B_14 2 14 NA NA HR NA
D25 IO_L15N_T2_DQS_DOUT_CSO_B_14 2 14 NA NA HR NA
G25 IO_L16P_T2_CSI_B_14 2 14 NA NA HR NA
G26 IO_L16N_T2_A15_D31_14 2 14 NA NA HR NA
F25 IO_L17P_T2_A14_D30_14 2 14 NA NA HR NA
E26 IO_L17N_T2_A13_D29_14 2 14 NA NA HR NA
J26 IO_L18P_T2_A12_D28_14 2 14 NA NA HR NA
H26 IO_L18N_T2_A11_D27_14 2 14 NA NA HR NA
H21 IO_L19P_T3_A10_D26_14 3 14 NA NA HR NA
G21 IO_L19N_T3_A09_D25_VREF_14 3 14 NA NA HR NA
H23 IO_L20P_T3_A08_D24_14 3 14 NA NA HR NA
H24 IO_L20N_T3_A07_D23_14 3 14 NA NA HR NA
J21 IO_L21P_T3_DQS_14 3 14 NA NA HR NA
H22 IO_L21N_T3_DQS_A06_D22_14 3 14 NA NA HR NA
J24 IO_L22P_T3_A05_D21_14 3 14 NA NA HR NA
J25 IO_L22N_T3_A04_D20_14 3 14 NA NA HR NA
L22 IO_L23P_T3_A03_D19_14 3 14 NA NA HR NA
K22 IO_L23N_T3_A02_D18_14 3 14 NA NA HR NA
K23 IO_L24P_T3_A01_D17_14 3 14 NA NA HR NA
J23 IO_L24N_T3_A00_D16_14 3 14 NA NA HR NA
L23 IO_25_14 NA 14 NA NA HR NA
K15 IO_0_15 NA 15 NA NA HR NA
C16 IO_L1P_T0_AD0P_15 0 15 NA NA HR NA
B16 IO_L1N_T0_AD0N_15 0 15 NA NA HR NA
A18 IO_L2P_T0_AD8P_15 0 15 NA NA HR NA
A19 IO_L2N_T0_AD8N_15 0 15 NA NA HR NA
B17 IO_L3P_T0_DQS_AD1P_15 0 15 NA NA HR NA
A17 IO_L3N_T0_DQS_AD1N_15 0 15 NA NA HR NA
C19 IO_L4P_T0_AD9P_15 0 15 NA NA HR NA
B19 IO_L4N_T0_AD9N_15 0 15 NA NA HR NA
C17 IO_L5P_T0_AD2P_15 0 15 NA NA HR NA
C18 IO_L5N_T0_AD2N_15 0 15 NA NA HR NA
D15 IO_L6P_T0_15 0 15 NA NA HR NA
D16 IO_L6N_T0_VREF_15 0 15 NA NA HR NA
H16 IO_L7P_T1_AD10P_15 1 15 NA NA HR NA
G16 IO_L7N_T1_AD10N_15 1 15 NA NA HR NA
G15 IO_L8P_T1_AD3P_15 1 15 NA NA HR NA
F15 IO_L8N_T1_AD3N_15 1 15 NA NA HR NA
J15 IO_L9P_T1_DQS_AD11P_15 1 15 NA NA HR NA
J16 IO_L9N_T1_DQS_AD11N_15 1 15 NA NA HR NA
E15 IO_L10P_T1_AD4P_15 1 15 NA NA HR NA
E16 IO_L10N_T1_AD4N_15 1 15 NA NA HR NA
G17 IO_L11P_T1_SRCC_AD12P_15 1 15 NA NA HR NA
F18 IO_L11N_T1_SRCC_AD12N_15 1 15 NA NA HR NA
F17 IO_L12P_T1_MRCC_AD5P_15 1 15 NA NA HR NA
E17 IO_L12N_T1_MRCC_AD5N_15 1 15 NA NA HR NA
E18 IO_L13P_T2_MRCC_15 2 15 NA NA HR NA
D18 IO_L13N_T2_MRCC_15 2 15 NA NA HR NA
H17 IO_L14P_T2_SRCC_15 2 15 NA NA HR NA
H18 IO_L14N_T2_SRCC_15 2 15 NA NA HR NA
D19 IO_L15P_T2_DQS_15 2 15 NA NA HR NA
D20 IO_L15N_T2_DQS_ADV_B_15 2 15 NA NA HR NA
G19 IO_L16P_T2_A28_15 2 15 NA NA HR NA
F20 IO_L16N_T2_A27_15 2 15 NA NA HR NA
F19 IO_L17P_T2_A26_15 2 15 NA NA HR NA
E20 IO_L17N_T2_A25_15 2 15 NA NA HR NA
H19 IO_L18P_T2_A24_15 2 15 NA NA HR NA
G20 IO_L18N_T2_A23_15 2 15 NA NA HR NA
K20 IO_L19P_T3_A22_15 3 15 NA NA HR NA
J20 IO_L19N_T3_A21_VREF_15 3 15 NA NA HR NA
J18 IO_L20P_T3_A20_15 3 15 NA NA HR NA
J19 IO_L20N_T3_A19_15 3 15 NA NA HR NA
L19 IO_L21P_T3_DQS_15 3 15 NA NA HR NA
L20 IO_L21N_T3_DQS_A18_15 3 15 NA NA HR NA
K16 IO_L22P_T3_A17_15 3 15 NA NA HR NA
K17 IO_L22N_T3_A16_15 3 15 NA NA HR NA
M17 IO_L23P_T3_FOE_B_15 3 15 NA NA HR NA
L18 IO_L23N_T3_FWE_B_15 3 15 NA NA HR NA
L17 IO_L24P_T3_RS1_15 3 15 NA NA HR NA
K18 IO_L24N_T3_RS0_15 3 15 NA NA HR NA
M16 IO_25_15 NA 15 NA NA HR NA
J8 IO_0_16 NA 16 NA NA HR NA
H9 IO_L1P_T0_16 0 16 NA NA HR NA
H8 IO_L1N_T0_16 0 16 NA NA HR NA
G10 IO_L2P_T0_16 0 16 NA NA HR NA
G9 IO_L2N_T0_16 0 16 NA NA HR NA
J13 IO_L3P_T0_DQS_16 0 16 NA NA HR NA
H13 IO_L3N_T0_DQS_16 0 16 NA NA HR NA
J11 IO_L4P_T0_16 0 16 NA NA HR NA
J10 IO_L4N_T0_16 0 16 NA NA HR NA
H14 IO_L5P_T0_16 0 16 NA NA HR NA
G14 IO_L5N_T0_16 0 16 NA NA HR NA
H12 IO_L6P_T0_16 0 16 NA NA HR NA
H11 IO_L6N_T0_VREF_16 0 16 NA NA HR NA
F9 IO_L7P_T1_16 1 16 NA NA HR NA
F8 IO_L7N_T1_16 1 16 NA NA HR NA
D9 IO_L8P_T1_16 1 16 NA NA HR NA
D8 IO_L8N_T1_16 1 16 NA NA HR NA
A9 IO_L9P_T1_DQS_16 1 16 NA NA HR NA
A8 IO_L9N_T1_DQS_16 1 16 NA NA HR NA
C9 IO_L10P_T1_16 1 16 NA NA HR NA
B9 IO_L10N_T1_16 1 16 NA NA HR NA
G11 IO_L11P_T1_SRCC_16 1 16 NA NA HR NA
F10 IO_L11N_T1_SRCC_16 1 16 NA NA HR NA
E10 IO_L12P_T1_MRCC_16 1 16 NA NA HR NA
D10 IO_L12N_T1_MRCC_16 1 16 NA NA HR NA
C12 IO_L13P_T2_MRCC_16 2 16 NA NA HR NA
C11 IO_L13N_T2_MRCC_16 2 16 NA NA HR NA
E11 IO_L14P_T2_SRCC_16 2 16 NA NA HR NA
D11 IO_L14N_T2_SRCC_16 2 16 NA NA HR NA
F14 IO_L15P_T2_DQS_16 2 16 NA NA HR NA
F13 IO_L15N_T2_DQS_16 2 16 NA NA HR NA
G12 IO_L16P_T2_16 2 16 NA NA HR NA
F12 IO_L16N_T2_16 2 16 NA NA HR NA
D14 IO_L17P_T2_16 2 16 NA NA HR NA
D13 IO_L17N_T2_16 2 16 NA NA HR NA
E13 IO_L18P_T2_16 2 16 NA NA HR NA
E12 IO_L18N_T2_16 2 16 NA NA HR NA
C14 IO_L19P_T3_16 3 16 NA NA HR NA
C13 IO_L19N_T3_VREF_16 3 16 NA NA HR NA
B12 IO_L20P_T3_16 3 16 NA NA HR NA
B11 IO_L20N_T3_16 3 16 NA NA HR NA
B14 IO_L21P_T3_DQS_16 3 16 NA NA HR NA
A14 IO_L21N_T3_DQS_16 3 16 NA NA HR NA
B10 IO_L22P_T3_16 3 16 NA NA HR NA
A10 IO_L22N_T3_16 3 16 NA NA HR NA
B15 IO_L23P_T3_16 3 16 NA NA HR NA
A15 IO_L23N_T3_16 3 16 NA NA HR NA
A13 IO_L24P_T3_16 3 16 NA NA HR NA
A12 IO_L24N_T3_16 3 16 NA NA HR NA
J14 IO_25_16 NA 16 NA NA HR NA
V13 IO_0_VRN_32 NA 32 VCCAUX NA HP 7K70T
AE17 IO_L1P_T0_32 0 32 VCCAUX NA HP 7K70T
AF17 IO_L1N_T0_32 0 32 VCCAUX NA HP 7K70T
AF14 IO_L2P_T0_32 0 32 VCCAUX NA HP 7K70T
AF15 IO_L2N_T0_32 0 32 VCCAUX NA HP 7K70T
AE18 IO_L3P_T0_DQS_32 0 32 VCCAUX NA HP 7K70T
AF18 IO_L3N_T0_DQS_32 0 32 VCCAUX NA HP 7K70T
AD15 IO_L4P_T0_32 0 32 VCCAUX NA HP 7K70T
AE15 IO_L4N_T0_32 0 32 VCCAUX NA HP 7K70T
AF19 IO_L5P_T0_32 0 32 VCCAUX NA HP 7K70T
AF20 IO_L5N_T0_32 0 32 VCCAUX NA HP 7K70T
AD16 IO_L6P_T0_32 0 32 VCCAUX NA HP 7K70T
AE16 IO_L6N_T0_VREF_32 0 32 VCCAUX NA HP 7K70T
AA14 IO_L7P_T1_32 1 32 VCCAUX NA HP 7K70T
AA15 IO_L7N_T1_32 1 32 VCCAUX NA HP 7K70T
AC14 IO_L8P_T1_32 1 32 VCCAUX NA HP 7K70T
AD14 IO_L8N_T1_32 1 32 VCCAUX NA HP 7K70T
Y15 IO_L9P_T1_DQS_32 1 32 VCCAUX NA HP 7K70T
Y16 IO_L9N_T1_DQS_32 1 32 VCCAUX NA HP 7K70T
AB14 IO_L10P_T1_32 1 32 VCCAUX NA HP 7K70T
AB15 IO_L10N_T1_32 1 32 VCCAUX NA HP 7K70T
AA17 IO_L11P_T1_SRCC_32 1 32 VCCAUX NA HP 7K70T
AA18 IO_L11N_T1_SRCC_32 1 32 VCCAUX NA HP 7K70T
AB16 IO_L12P_T1_MRCC_32 1 32 VCCAUX NA HP 7K70T
AC16 IO_L12N_T1_MRCC_32 1 32 VCCAUX NA HP 7K70T
AC18 IO_L13P_T2_MRCC_32 2 32 VCCAUX NA HP 7K70T
AD18 IO_L13N_T2_MRCC_32 2 32 VCCAUX NA HP 7K70T
AB17 IO_L14P_T2_SRCC_32 2 32 VCCAUX NA HP 7K70T
AC17 IO_L14N_T2_SRCC_32 2 32 VCCAUX NA HP 7K70T
AD20 IO_L15P_T2_DQS_32 2 32 VCCAUX NA HP 7K70T
AE20 IO_L15N_T2_DQS_32 2 32 VCCAUX NA HP 7K70T
AA19 IO_L16P_T2_32 2 32 VCCAUX NA HP 7K70T
AA20 IO_L16N_T2_32 2 32 VCCAUX NA HP 7K70T
AC19 IO_L17P_T2_32 2 32 VCCAUX NA HP 7K70T
AD19 IO_L17N_T2_32 2 32 VCCAUX NA HP 7K70T
AB19 IO_L18P_T2_32 2 32 VCCAUX NA HP 7K70T
AB20 IO_L18N_T2_32 2 32 VCCAUX NA HP 7K70T
Y17 IO_L19P_T3_32 3 32 VCCAUX NA HP 7K70T
Y18 IO_L19N_T3_VREF_32 3 32 VCCAUX NA HP 7K70T
V16 IO_L20P_T3_32 3 32 VCCAUX NA HP 7K70T
V17 IO_L20N_T3_32 3 32 VCCAUX NA HP 7K70T
W18 IO_L21P_T3_DQS_32 3 32 VCCAUX NA HP 7K70T
W19 IO_L21N_T3_DQS_32 3 32 VCCAUX NA HP 7K70T
W15 IO_L22P_T3_32 3 32 VCCAUX NA HP 7K70T
W16 IO_L22N_T3_32 3 32 VCCAUX NA HP 7K70T
V18 IO_L23P_T3_32 3 32 VCCAUX NA HP 7K70T
V19 IO_L23N_T3_32 3 32 VCCAUX NA HP 7K70T
V14 IO_L24P_T3_32 3 32 VCCAUX NA HP 7K70T
W14 IO_L24N_T3_32 3 32 VCCAUX NA HP 7K70T
W13 IO_25_VRP_32 NA 32 VCCAUX NA HP 7K70T
U9 IO_0_VRN_33 NA 33 VCCAUX NA HP NA
V11 IO_L1P_T0_33 0 33 VCCAUX NA HP NA
W11 IO_L1N_T0_33 0 33 VCCAUX NA HP NA
V8 IO_L2P_T0_33 0 33 VCCAUX NA HP NA
V7 IO_L2N_T0_33 0 33 VCCAUX NA HP NA
W10 IO_L3P_T0_DQS_33 0 33 VCCAUX NA HP NA
W9 IO_L3N_T0_DQS_33 0 33 VCCAUX NA HP NA
Y8 IO_L4P_T0_33 0 33 VCCAUX NA HP NA
Y7 IO_L4N_T0_33 0 33 VCCAUX NA HP NA
Y11 IO_L5P_T0_33 0 33 VCCAUX NA HP NA
Y10 IO_L5N_T0_33 0 33 VCCAUX NA HP NA
V9 IO_L6P_T0_33 0 33 VCCAUX NA HP NA
W8 IO_L6N_T0_VREF_33 0 33 VCCAUX NA HP NA
AE7 IO_L7P_T1_33 1 33 VCCAUX NA HP NA
AF7 IO_L7N_T1_33 1 33 VCCAUX NA HP NA
AA8 IO_L8P_T1_33 1 33 VCCAUX NA HP NA
AA7 IO_L8N_T1_33 1 33 VCCAUX NA HP NA
AC8 IO_L9P_T1_DQS_33 1 33 VCCAUX NA HP NA
AD8 IO_L9N_T1_DQS_33 1 33 VCCAUX NA HP NA
AB7 IO_L10P_T1_33 1 33 VCCAUX NA HP NA
AC7 IO_L10N_T1_33 1 33 VCCAUX NA HP NA
AA9 IO_L11P_T1_SRCC_33 1 33 VCCAUX NA HP NA
AB9 IO_L11N_T1_SRCC_33 1 33 VCCAUX NA HP NA
AC9 IO_L12P_T1_MRCC_33 1 33 VCCAUX NA HP NA
AD9 IO_L12N_T1_MRCC_33 1 33 VCCAUX NA HP NA
AB11 IO_L13P_T2_MRCC_33 2 33 VCCAUX NA HP NA
AC11 IO_L13N_T2_MRCC_33 2 33 VCCAUX NA HP NA
AA10 IO_L14P_T2_SRCC_33 2 33 VCCAUX NA HP NA
AB10 IO_L14N_T2_SRCC_33 2 33 VCCAUX NA HP NA
AB12 IO_L15P_T2_DQS_33 2 33 VCCAUX NA HP NA
AC12 IO_L15N_T2_DQS_33 2 33 VCCAUX NA HP NA
AA13 IO_L16P_T2_33 2 33 VCCAUX NA HP NA
AA12 IO_L16N_T2_33 2 33 VCCAUX NA HP NA
AC13 IO_L17P_T2_33 2 33 VCCAUX NA HP NA
AD13 IO_L17N_T2_33 2 33 VCCAUX NA HP NA
Y13 IO_L18P_T2_33 2 33 VCCAUX NA HP NA
Y12 IO_L18N_T2_33 2 33 VCCAUX NA HP NA
AD11 IO_L19P_T3_33 3 33 VCCAUX NA HP NA
AE11 IO_L19N_T3_VREF_33 3 33 VCCAUX NA HP NA
AD10 IO_L20P_T3_33 3 33 VCCAUX NA HP NA
AE10 IO_L20N_T3_33 3 33 VCCAUX NA HP NA
AE12 IO_L21P_T3_DQS_33 3 33 VCCAUX NA HP NA
AF12 IO_L21N_T3_DQS_33 3 33 VCCAUX NA HP NA
AE8 IO_L22P_T3_33 3 33 VCCAUX NA HP NA
AF8 IO_L22N_T3_33 3 33 VCCAUX NA HP NA
AE13 IO_L23P_T3_33 3 33 VCCAUX NA HP NA
AF13 IO_L23N_T3_33 3 33 VCCAUX NA HP NA
AF10 IO_L24P_T3_33 3 33 VCCAUX NA HP NA
AF9 IO_L24N_T3_33 3 33 VCCAUX NA HP NA
V12 IO_25_VRP_33 NA 33 VCCAUX NA HP NA
U4 IO_0_VRN_34 NA 34 VCCAUX NA HP NA
U6 IO_L1P_T0_34 0 34 VCCAUX NA HP NA
U5 IO_L1N_T0_34 0 34 VCCAUX NA HP NA
U2 IO_L2P_T0_34 0 34 VCCAUX NA HP NA
U1 IO_L2N_T0_34 0 34 VCCAUX NA HP NA
W6 IO_L3P_T0_DQS_34 0 34 VCCAUX NA HP NA
W5 IO_L3N_T0_DQS_34 0 34 VCCAUX NA HP NA
V3 IO_L4P_T0_34 0 34 VCCAUX NA HP NA
W3 IO_L4N_T0_34 0 34 VCCAUX NA HP NA
U7 IO_L5P_T0_34 0 34 VCCAUX NA HP NA
V6 IO_L5N_T0_34 0 34 VCCAUX NA HP NA
V4 IO_L6P_T0_34 0 34 VCCAUX NA HP NA
W4 IO_L6N_T0_VREF_34 0 34 VCCAUX NA HP NA
Y3 IO_L7P_T1_34 1 34 VCCAUX NA HP NA
Y2 IO_L7N_T1_34 1 34 VCCAUX NA HP NA
V2 IO_L8P_T1_34 1 34 VCCAUX NA HP NA
V1 IO_L8N_T1_34 1 34 VCCAUX NA HP NA
AB1 IO_L9P_T1_DQS_34 1 34 VCCAUX NA HP NA
AC1 IO_L9N_T1_DQS_34 1 34 VCCAUX NA HP NA
W1 IO_L10P_T1_34 1 34 VCCAUX NA HP NA
Y1 IO_L10N_T1_34 1 34 VCCAUX NA HP NA
AB2 IO_L11P_T1_SRCC_34 1 34 VCCAUX NA HP NA
AC2 IO_L11N_T1_SRCC_34 1 34 VCCAUX NA HP NA
AA3 IO_L12P_T1_MRCC_34 1 34 VCCAUX NA HP NA
AA2 IO_L12N_T1_MRCC_34 1 34 VCCAUX NA HP NA
AA4 IO_L13P_T2_MRCC_34 2 34 VCCAUX NA HP NA
AB4 IO_L13N_T2_MRCC_34 2 34 VCCAUX NA HP NA
AC4 IO_L14P_T2_SRCC_34 2 34 VCCAUX NA HP NA
AC3 IO_L14N_T2_SRCC_34 2 34 VCCAUX NA HP NA
AA5 IO_L15P_T2_DQS_34 2 34 VCCAUX NA HP NA
AB5 IO_L15N_T2_DQS_34 2 34 VCCAUX NA HP NA
AB6 IO_L16P_T2_34 2 34 VCCAUX NA HP NA
AC6 IO_L16N_T2_34 2 34 VCCAUX NA HP NA
Y6 IO_L17P_T2_34 2 34 VCCAUX NA HP NA
Y5 IO_L17N_T2_34 2 34 VCCAUX NA HP NA
AD6 IO_L18P_T2_34 2 34 VCCAUX NA HP NA
AD5 IO_L18N_T2_34 2 34 VCCAUX NA HP NA
AD4 IO_L19P_T3_34 3 34 VCCAUX NA HP NA
AD3 IO_L19N_T3_VREF_34 3 34 VCCAUX NA HP NA
AD1 IO_L20P_T3_34 3 34 VCCAUX NA HP NA
AE1 IO_L20N_T3_34 3 34 VCCAUX NA HP NA
AF5 IO_L21P_T3_DQS_34 3 34 VCCAUX NA HP NA
AF4 IO_L21N_T3_DQS_34 3 34 VCCAUX NA HP NA
AE3 IO_L22P_T3_34 3 34 VCCAUX NA HP NA
AE2 IO_L22N_T3_34 3 34 VCCAUX NA HP NA
AE6 IO_L23P_T3_34 3 34 VCCAUX NA HP NA
AE5 IO_L23N_T3_34 3 34 VCCAUX NA HP NA
AF3 IO_L24P_T3_34 3 34 VCCAUX NA HP NA
AF2 IO_L24N_T3_34 3 34 VCCAUX NA HP NA
T7 IO_25_VRP_34 NA 34 VCCAUX NA HP NA
H2 MGTXTXP3_115 NA 115 NA NA GTX NA
J4 MGTXRXP3_115 NA 115 NA NA GTX NA
H1 MGTXTXN3_115 NA 115 NA NA GTX NA
J3 MGTXRXN3_115 NA 115 NA NA GTX NA
K2 MGTXTXP2_115 NA 115 NA NA GTX NA
L4 MGTXRXP2_115 NA 115 NA NA GTX NA
K1 MGTXTXN2_115 NA 115 NA NA GTX NA
H6 MGTREFCLK0P_115 NA 115 NA NA GTX NA
L3 MGTXRXN2_115 NA 115 NA NA GTX NA
M5 MGTAVTTRCAL_115 NA 115 NA NA GTX NA
H5 MGTREFCLK0N_115 NA 115 NA NA GTX NA
M6 MGTRREF_115 NA 115 NA NA GTX NA
K5 MGTREFCLK1N_115 NA 115 NA NA GTX NA
K6 MGTREFCLK1P_115 NA 115 NA NA GTX NA
M2 MGTXTXP1_115 NA 115 NA NA GTX NA
N4 MGTXRXP1_115 NA 115 NA NA GTX NA
M1 MGTXTXN1_115 NA 115 NA NA GTX NA
N3 MGTXRXN1_115 NA 115 NA NA GTX NA
P2 MGTXTXP0_115 NA 115 NA NA GTX NA
R4 MGTXRXP0_115 NA 115 NA NA GTX NA
P1 MGTXTXN0_115 NA 115 NA NA GTX NA
R3 MGTXRXN0_115 NA 115 NA NA GTX NA
A4 MGTXTXP3_116 NA 116 NA NA GTX NA
B6 MGTXRXP3_116 NA 116 NA NA GTX NA
A3 MGTXTXN3_116 NA 116 NA NA GTX NA
B5 MGTXRXN3_116 NA 116 NA NA GTX NA
B2 MGTXTXP2_116 NA 116 NA NA GTX NA
C4 MGTXRXP2_116 NA 116 NA NA GTX NA
B1 MGTXTXN2_116 NA 116 NA NA GTX NA
D6 MGTREFCLK0P_116 NA 116 NA NA GTX NA
C3 MGTXRXN2_116 NA 116 NA NA GTX NA
D5 MGTREFCLK0N_116 NA 116 NA NA GTX NA
F5 MGTREFCLK1N_116 NA 116 NA NA GTX NA
F6 MGTREFCLK1P_116 NA 116 NA NA GTX NA
D2 MGTXTXP1_116 NA 116 NA NA GTX NA
E4 MGTXRXP1_116 NA 116 NA NA GTX NA
D1 MGTXTXN1_116 NA 116 NA NA GTX NA
E3 MGTXRXN1_116 NA 116 NA NA GTX NA
F2 MGTXTXP0_116 NA 116 NA NA GTX NA
G4 MGTXRXP0_116 NA 116 NA NA GTX NA
F1 MGTXTXN0_116 NA 116 NA NA GTX NA
G3 MGTXRXN0_116 NA 116 NA NA GTX NA
N13 VCCBRAM NA NA NA NA NA NA
R13 VCCBRAM NA NA NA NA NA NA
T12 VCCBRAM NA NA NA NA NA NA
U13 VCCBRAM NA NA NA NA NA NA
C6 MGTAVCC NA NA NA NA NA NA
E6 MGTAVCC NA NA NA NA NA NA
G6 MGTAVCC NA NA NA NA NA NA
J6 MGTAVCC NA NA NA NA NA NA
L6 MGTAVCC NA NA NA NA NA NA
B3 MGTAVTT NA NA NA NA NA NA
C2 MGTAVTT NA NA NA NA NA NA
D3 MGTAVTT NA NA NA NA NA NA
G2 MGTAVTT NA NA NA NA NA NA
H3 MGTAVTT NA NA NA NA NA NA
L2 MGTAVTT NA NA NA NA NA NA
M3 MGTAVTT NA NA NA NA NA NA
N6 MGTVCCAUX NA NA NA NA NA NA
A1 GND NA NA NA NA NA NA
A2 GND NA NA NA NA NA NA
A5 GND NA NA NA NA NA NA
A6 GND NA NA NA NA NA NA
A7 GND NA NA NA NA NA NA
A16 GND NA NA NA NA NA NA
A26 GND NA NA NA NA NA NA
AA6 GND NA NA NA NA NA NA
AA16 GND NA NA NA NA NA NA
AA26 GND NA NA NA NA NA NA
AB3 GND NA NA NA NA NA NA
AB13 GND NA NA NA NA NA NA
AB23 GND NA NA NA NA NA NA
AC10 GND NA NA NA NA NA NA
AC20 GND NA NA NA NA NA NA
AD7 GND NA NA NA NA NA NA
AD17 GND NA NA NA NA NA NA
AE4 GND NA NA NA NA NA NA
AE14 GND NA NA NA NA NA NA
AE24 GND NA NA NA NA NA NA
AF1 GND NA NA NA NA NA NA
AF11 GND NA NA NA NA NA NA
AF21 GND NA NA NA NA NA NA
B4 GND NA NA NA NA NA NA
B7 GND NA NA NA NA NA NA
B13 GND NA NA NA NA NA NA
B23 GND NA NA NA NA NA NA
C1 GND NA NA NA NA NA NA
C5 GND NA NA NA NA NA NA
C7 GND NA NA NA NA NA NA
C10 GND NA NA NA NA NA NA
C20 GND NA NA NA NA NA NA
D4 GND NA NA NA NA NA NA
D7 GND NA NA NA NA NA NA
D17 GND NA NA NA NA NA NA
E1 GND NA NA NA NA NA NA
E2 GND NA NA NA NA NA NA
E5 GND NA NA NA NA NA NA
E7 GND NA NA NA NA NA NA
E14 GND NA NA NA NA NA NA
E24 GND NA NA NA NA NA NA
F3 GND NA NA NA NA NA NA
F4 GND NA NA NA NA NA NA
F7 GND NA NA NA NA NA NA
F11 GND NA NA NA NA NA NA
F21 GND NA NA NA NA NA NA
G1 GND NA NA NA NA NA NA
G5 GND NA NA NA NA NA NA
G8 GND NA NA NA NA NA NA
G18 GND NA NA NA NA NA NA
H4 GND NA NA NA NA NA NA
H7 GND NA NA NA NA NA NA
H15 GND NA NA NA NA NA NA
H25 GND NA NA NA NA NA NA
J1 GND NA NA NA NA NA NA
J2 GND NA NA NA NA NA NA
J5 GND NA NA NA NA NA NA
J12 GND NA NA NA NA NA NA
J22 GND NA NA NA NA NA NA
K3 GND NA NA NA NA NA NA
K4 GND NA NA NA NA NA NA
K7 GND NA NA NA NA NA NA
K9 GND NA NA NA NA NA NA
K11 GND NA NA NA NA NA NA
K13 GND NA NA NA NA NA NA
K19 GND NA NA NA NA NA NA
L1 GND NA NA NA NA NA NA
L5 GND NA NA NA NA NA NA
L10 GND NA NA NA NA NA NA
L12 GND NA NA NA NA NA NA
L14 GND NA NA NA NA NA NA
L16 GND NA NA NA NA NA NA
L26 GND NA NA NA NA NA NA
M4 GND NA NA NA NA NA NA
M7 GND NA NA NA NA NA NA
M9 GND NA NA NA NA NA NA
M13 GND NA NA NA NA NA NA
M15 GND NA NA NA NA NA NA
M23 GND NA NA NA NA NA NA
N1 GND NA NA NA NA NA NA
N2 GND NA NA NA NA NA NA
N5 GND NA NA NA NA NA NA
N7 GND NA NA NA NA NA NA
N10 GND NA NA NA NA NA NA
N14 GND NA NA NA NA NA NA
N20 GND NA NA NA NA NA NA
P3 GND NA NA NA NA NA NA
P4 GND NA NA NA NA NA NA
P9 GND NA NA NA NA NA NA
P13 GND NA NA NA NA NA NA
P15 GND NA NA NA NA NA NA
P17 GND NA NA NA NA NA NA
R1 GND NA NA NA NA NA NA
R2 GND NA NA NA NA NA NA
R5 GND NA NA NA NA NA NA
R8 GND NA NA NA NA NA NA
R10 GND NA NA NA NA NA NA
R14 GND NA NA NA NA NA NA
R24 GND NA NA NA NA NA NA
T1 GND NA NA NA NA NA NA
T3 GND NA NA NA NA NA NA
T4 GND NA NA NA NA NA NA
T9 GND NA NA NA NA NA NA
T11 GND NA NA NA NA NA NA
T13 GND NA NA NA NA NA NA
T15 GND NA NA NA NA NA NA
T21 GND NA NA NA NA NA NA
U8 GND NA NA NA NA NA NA
U10 GND NA NA NA NA NA NA
U12 GND NA NA NA NA NA NA
U14 GND NA NA NA NA NA NA
U18 GND NA NA NA NA NA NA
V5 GND NA NA NA NA NA NA
V15 GND NA NA NA NA NA NA
V25 GND NA NA NA NA NA NA
W2 GND NA NA NA NA NA NA
W12 GND NA NA NA NA NA NA
W22 GND NA NA NA NA NA NA
Y9 GND NA NA NA NA NA NA
Y19 GND NA NA NA NA NA NA
J9 VCCINT NA NA NA NA NA NA
K8 VCCINT NA NA NA NA NA NA
K10 VCCINT NA NA NA NA NA NA
K12 VCCINT NA NA NA NA NA NA
K14 VCCINT NA NA NA NA NA NA
L9 VCCINT NA NA NA NA NA NA
L13 VCCINT NA NA NA NA NA NA
L15 VCCINT NA NA NA NA NA NA
M8 VCCINT NA NA NA NA NA NA
M14 VCCINT NA NA NA NA NA NA
N9 VCCINT NA NA NA NA NA NA
N15 VCCINT NA NA NA NA NA NA
P14 VCCINT NA NA NA NA NA NA
R15 VCCINT NA NA NA NA NA NA
T14 VCCINT NA NA NA NA NA NA
U15 VCCINT NA NA NA NA NA NA
T10 VCCAUX NA NA NA NA NA NA
U11 VCCAUX NA NA NA NA NA NA
L11 VCCAUX NA NA NA NA NA NA
M10 VCCAUX NA NA NA NA NA NA
P10 VCCAUX NA NA NA NA NA NA
T8 VCCAUX_IO_G0 NA NA NA NA NA NA
R9 VCCAUX_IO_G0 NA NA NA NA NA NA
P8 VCCAUX_IO_G0 NA NA NA NA NA NA
L7 VCCO_0 NA 0 NA NA NA NA
T6 VCCO_0 NA 0 NA NA NA NA
AA21 VCCO_12 NA 12 NA NA NA NA
AC25 VCCO_12 NA 12 NA NA NA NA
AD22 VCCO_12 NA 12 NA NA NA NA
AF26 VCCO_12 NA 12 NA NA NA NA
U23 VCCO_12 NA 12 NA NA NA NA
V20 VCCO_12 NA 12 NA NA NA NA
Y24 VCCO_12 NA 12 NA NA NA NA
K24 VCCO_13 NA 13 NA NA NA NA
N25 VCCO_13 NA 13 NA NA NA NA
P22 VCCO_13 NA 13 NA NA NA NA
R19 VCCO_13 NA 13 NA NA NA NA
T16 VCCO_13 NA 13 NA NA NA NA
T26 VCCO_13 NA 13 NA NA NA NA
A21 VCCO_14 NA 14 NA NA NA NA
C25 VCCO_14 NA 14 NA NA NA NA
D22 VCCO_14 NA 14 NA NA NA NA
F26 VCCO_14 NA 14 NA NA NA NA
G23 VCCO_14 NA 14 NA NA NA NA
L21 VCCO_14 NA 14 NA NA NA NA
B18 VCCO_15 NA 15 NA NA NA NA
E19 VCCO_15 NA 15 NA NA NA NA
F16 VCCO_15 NA 15 NA NA NA NA
H20 VCCO_15 NA 15 NA NA NA NA
J17 VCCO_15 NA 15 NA NA NA NA
M18 VCCO_15 NA 15 NA NA NA NA
A11 VCCO_16 NA 16 NA NA NA NA
B8 VCCO_16 NA 16 NA NA NA NA
C15 VCCO_16 NA 16 NA NA NA NA
D12 VCCO_16 NA 16 NA NA NA NA
E9 VCCO_16 NA 16 NA NA NA NA
G13 VCCO_16 NA 16 NA NA NA NA
H10 VCCO_16 NA 16 NA NA NA NA
AB18 VCCO_32 NA 32 NA NA NA NA
AC15 VCCO_32 NA 32 NA NA NA NA
AE19 VCCO_32 NA 32 NA NA NA NA
AF16 VCCO_32 NA 32 NA NA NA NA
W17 VCCO_32 NA 32 NA NA NA NA
Y14 VCCO_32 NA 32 NA NA NA NA
AA11 VCCO_33 NA 33 NA NA NA NA
AB8 VCCO_33 NA 33 NA NA NA NA
AD12 VCCO_33 NA 33 NA NA NA NA
AE9 VCCO_33 NA 33 NA NA NA NA
V10 VCCO_33 NA 33 NA NA NA NA
W7 VCCO_33 NA 33 NA NA NA NA
AA1 VCCO_34 NA 34 NA NA NA NA
AC5 VCCO_34 NA 34 NA NA NA NA
AD2 VCCO_34 NA 34 NA NA NA NA
AF6 VCCO_34 NA 34 NA NA NA NA
U3 VCCO_34 NA 34 NA NA NA NA
Y4 VCCO_34 NA 34 NA NA NA NA
Total Number of Pins Generated, 676
hdl/syn/svec7_test/xc7k325tffg900pkg.txt deleted 100644 → 0
View file @ 90348ce2
Device/Package xc7k325tffg900 8/10/2011 13:59:07
Pin Pin Name Memory Byte Group Bank VCCAUX Group Super Logic Region I/O Type No-Connect
U14 DXN_0 NA 0 NA NA CONFIG NA
P15 VCCADC_0 NA 0 NA NA CONFIG NA
P14 GNDADC_0 NA 0 NA NA CONFIG NA
U15 DXP_0 NA 0 NA NA CONFIG NA
R14 VREFN_0 NA 0 NA NA CONFIG NA
T15 VREFP_0 NA 0 NA NA CONFIG NA
R15 VP_0 NA 0 NA NA CONFIG NA
T14 VN_0 NA 0 NA NA CONFIG NA
C10 VCCBATT_0 NA 0 NA NA CONFIG NA
B10 CCLK_0 NA 0 NA NA CONFIG NA
E10 TCK_0 NA 0 NA NA CONFIG NA
F10 TMS_0 NA 0 NA NA CONFIG NA
G10 TDO_0 NA 0 NA NA CONFIG NA
H10 TDI_0 NA 0 NA NA CONFIG NA
A10 INIT_B_0 NA 0 NA NA CONFIG NA
K10 PROGRAM_B_0 NA 0 NA NA CONFIG NA
L10 CFGBVS_0 NA 0 NA NA CONFIG NA
M10 DONE_0 NA 0 NA NA CONFIG NA
AB1 M2_0 NA 0 NA NA CONFIG NA
AB5 M0_0 NA 0 NA NA CONFIG NA
AB2 M1_0 NA 0 NA NA CONFIG NA
Y20 IO_0_12 NA 12 NA NA HR NA
Y23 IO_L1P_T0_12 0 12 NA NA HR NA
Y24 IO_L1N_T0_12 0 12 NA NA HR NA
Y21 IO_L2P_T0_12 0 12 NA NA HR NA
AA21 IO_L2N_T0_12 0 12 NA NA HR NA
AB22 IO_L3P_T0_DQS_12 0 12 NA NA HR NA
AB23 IO_L3N_T0_DQS_12 0 12 NA NA HR NA
AA22 IO_L4P_T0_12 0 12 NA NA HR NA
AA23 IO_L4N_T0_12 0 12 NA NA HR NA
AC20 IO_L5P_T0_12 0 12 NA NA HR NA
AC21 IO_L5N_T0_12 0 12 NA NA HR NA
AA20 IO_L6P_T0_12 0 12 NA NA HR NA
AB20 IO_L6N_T0_VREF_12 0 12 NA NA HR NA
AB24 IO_L7P_T1_12 1 12 NA NA HR NA
AC25 IO_L7N_T1_12 1 12 NA NA HR NA
AC22 IO_L8P_T1_12 1 12 NA NA HR NA
AD22 IO_L8N_T1_12 1 12 NA NA HR NA
AC24 IO_L9P_T1_DQS_12 1 12 NA NA HR NA
AD24 IO_L9N_T1_DQS_12 1 12 NA NA HR NA
AD21 IO_L10P_T1_12 1 12 NA NA HR NA
AE21 IO_L10N_T1_12 1 12 NA NA HR NA
AE23 IO_L11P_T1_SRCC_12 1 12 NA NA HR NA
AF23 IO_L11N_T1_SRCC_12 1 12 NA NA HR NA
AD23 IO_L12P_T1_MRCC_12 1 12 NA NA HR NA
AE24 IO_L12N_T1_MRCC_12 1 12 NA NA HR NA
AF22 IO_L13P_T2_MRCC_12 2 12 NA NA HR NA
AG23 IO_L13N_T2_MRCC_12 2 12 NA NA HR NA
AG24 IO_L14P_T2_SRCC_12 2 12 NA NA HR NA
AH24 IO_L14N_T2_SRCC_12 2 12 NA NA HR NA
AJ24 IO_L15P_T2_DQS_12 2 12 NA NA HR NA
AK25 IO_L15N_T2_DQS_12 2 12 NA NA HR NA
AE25 IO_L16P_T2_12 2 12 NA NA HR NA
AF25 IO_L16N_T2_12 2 12 NA NA HR NA
AK23 IO_L17P_T2_12 2 12 NA NA HR NA
AK24 IO_L17N_T2_12 2 12 NA NA HR NA
AG25 IO_L18P_T2_12 2 12 NA NA HR NA
AH25 IO_L18N_T2_12 2 12 NA NA HR NA
AF20 IO_L19P_T3_12 3 12 NA NA HR NA
AF21 IO_L19N_T3_VREF_12 3 12 NA NA HR NA
AG22 IO_L20P_T3_12 3 12 NA NA HR NA
AH22 IO_L20N_T3_12 3 12 NA NA HR NA
AJ22 IO_L21P_T3_DQS_12 3 12 NA NA HR NA
AJ23 IO_L21N_T3_DQS_12 3 12 NA NA HR NA
AG20 IO_L22P_T3_12 3 12 NA NA HR NA
AH20 IO_L22N_T3_12 3 12 NA NA HR NA
AH21 IO_L23P_T3_12 3 12 NA NA HR NA
AJ21 IO_L23N_T3_12 3 12 NA NA HR NA
AK20 IO_L24P_T3_12 3 12 NA NA HR NA
AK21 IO_L24N_T3_12 3 12 NA NA HR NA
AE20 IO_25_12 NA 12 NA NA HR NA
Y25 IO_0_13 NA 13 NA NA HR NA
Y26 IO_L1P_T0_13 0 13 NA NA HR NA
AA26 IO_L1N_T0_13 0 13 NA NA HR NA
W27 IO_L2P_T0_13 0 13 NA NA HR NA
W28 IO_L2N_T0_13 0 13 NA NA HR NA
Y28 IO_L3P_T0_DQS_13 0 13 NA NA HR NA
AA28 IO_L3N_T0_DQS_13 0 13 NA NA HR NA
W29 IO_L4P_T0_13 0 13 NA NA HR NA
Y29 IO_L4N_T0_13 0 13 NA NA HR NA
AA27 IO_L5P_T0_13 0 13 NA NA HR NA
AB28 IO_L5N_T0_13 0 13 NA NA HR NA
AA25 IO_L6P_T0_13 0 13 NA NA HR NA
AB25 IO_L6N_T0_VREF_13 0 13 NA NA HR NA
AC29 IO_L7P_T1_13 1 13 NA NA HR NA
AC30 IO_L7N_T1_13 1 13 NA NA HR NA
Y30 IO_L8P_T1_13 1 13 NA NA HR NA
AA30 IO_L8N_T1_13 1 13 NA NA HR NA
AD29 IO_L9P_T1_DQS_13 1 13 NA NA HR NA
AE29 IO_L9N_T1_DQS_13 1 13 NA NA HR NA
AB29 IO_L10P_T1_13 1 13 NA NA HR NA
AB30 IO_L10N_T1_13 1 13 NA NA HR NA
AD27 IO_L11P_T1_SRCC_13 1 13 NA NA HR NA
AD28 IO_L11N_T1_SRCC_13 1 13 NA NA HR NA
AB27 IO_L12P_T1_MRCC_13 1 13 NA NA HR NA
AC27 IO_L12N_T1_MRCC_13 1 13 NA NA HR NA
AG29 IO_L13P_T2_MRCC_13 2 13 NA NA HR NA
AH29 IO_L13N_T2_MRCC_13 2 13 NA NA HR NA
AE28 IO_L14P_T2_SRCC_13 2 13 NA NA HR NA
AF28 IO_L14N_T2_SRCC_13 2 13 NA NA HR NA
AK29 IO_L15P_T2_DQS_13 2 13 NA NA HR NA
AK30 IO_L15N_T2_DQS_13 2 13 NA NA HR NA
AE30 IO_L16P_T2_13 2 13 NA NA HR NA
AF30 IO_L16N_T2_13 2 13 NA NA HR NA
AJ28 IO_L17P_T2_13 2 13 NA NA HR NA
AJ29 IO_L17N_T2_13 2 13 NA NA HR NA
AG30 IO_L18P_T2_13 2 13 NA NA HR NA
AH30 IO_L18N_T2_13 2 13 NA NA HR NA
AC26 IO_L19P_T3_13 3 13 NA NA HR NA
AD26 IO_L19N_T3_VREF_13 3 13 NA NA HR NA
AJ27 IO_L20P_T3_13 3 13 NA NA HR NA
AK28 IO_L20N_T3_13 3 13 NA NA HR NA
AG27 IO_L21P_T3_DQS_13 3 13 NA NA HR NA
AG28 IO_L21N_T3_DQS_13 3 13 NA NA HR NA
AH26 IO_L22P_T3_13 3 13 NA NA HR NA
AH27 IO_L22N_T3_13 3 13 NA NA HR NA
AF26 IO_L23P_T3_13 3 13 NA NA HR NA
AF27 IO_L23N_T3_13 3 13 NA NA HR NA
AJ26 IO_L24P_T3_13 3 13 NA NA HR NA
AK26 IO_L24N_T3_13 3 13 NA NA HR NA
AE26 IO_25_13 NA 13 NA NA HR NA
R19 IO_0_14 NA 14 NA NA HR NA
P24 IO_L1P_T0_D00_MOSI_14 0 14 NA NA HR NA
R25 IO_L1N_T0_D01_DIN_14 0 14 NA NA HR NA
R20 IO_L2P_T0_D02_14 0 14 NA NA HR NA
R21 IO_L2N_T0_D03_14 0 14 NA NA HR NA
R23 IO_L3P_T0_DQS_PUDC_B_14 0 14 NA NA HR NA
R24 IO_L3N_T0_DQS_EMCCLK_14 0 14 NA NA HR NA
T20 IO_L4P_T0_D04_14 0 14 NA NA HR NA
T21 IO_L4N_T0_D05_14 0 14 NA NA HR NA
T22 IO_L5P_T0_D06_14 0 14 NA NA HR NA
T23 IO_L5N_T0_D07_14 0 14 NA NA HR NA
U19 IO_L6P_T0_FCS_B_14 0 14 NA NA HR NA
U20 IO_L6N_T0_D08_VREF_14 0 14 NA NA HR NA
P29 IO_L7P_T1_D09_14 1 14 NA NA HR NA
R29 IO_L7N_T1_D10_14 1 14 NA NA HR NA
P27 IO_L8P_T1_D11_14 1 14 NA NA HR NA
P28 IO_L8N_T1_D12_14 1 14 NA NA HR NA
R30 IO_L9P_T1_DQS_14 1 14 NA NA HR NA
T30 IO_L9N_T1_DQS_D13_14 1 14 NA NA HR NA
P26 IO_L10P_T1_D14_14 1 14 NA NA HR NA
R26 IO_L10N_T1_D15_14 1 14 NA NA HR NA
R28 IO_L11P_T1_SRCC_14 1 14 NA NA HR NA
T28 IO_L11N_T1_SRCC_14 1 14 NA NA HR NA
T26 IO_L12P_T1_MRCC_14 1 14 NA NA HR NA
T27 IO_L12N_T1_MRCC_14 1 14 NA NA HR NA
U27 IO_L13P_T2_MRCC_14 2 14 NA NA HR NA
U28 IO_L13N_T2_MRCC_14 2 14 NA NA HR NA
T25 IO_L14P_T2_SRCC_14 2 14 NA NA HR NA
U25 IO_L14N_T2_SRCC_14 2 14 NA NA HR NA
U29 IO_L15P_T2_DQS_RDWR_B_14 2 14 NA NA HR NA
U30 IO_L15N_T2_DQS_DOUT_CSO_B_14 2 14 NA NA HR NA
V26 IO_L16P_T2_CSI_B_14 2 14 NA NA HR NA
V27 IO_L16N_T2_A15_D31_14 2 14 NA NA HR NA
V29 IO_L17P_T2_A14_D30_14 2 14 NA NA HR NA
V30 IO_L17N_T2_A13_D29_14 2 14 NA NA HR NA
V25 IO_L18P_T2_A12_D28_14 2 14 NA NA HR NA
W26 IO_L18N_T2_A11_D27_14 2 14 NA NA HR NA
V19 IO_L19P_T3_A10_D26_14 3 14 NA NA HR NA
V20 IO_L19N_T3_A09_D25_VREF_14 3 14 NA NA HR NA
W23 IO_L20P_T3_A08_D24_14 3 14 NA NA HR NA
W24 IO_L20N_T3_A07_D23_14 3 14 NA NA HR NA
U22 IO_L21P_T3_DQS_14 3 14 NA NA HR NA
U23 IO_L21N_T3_DQS_A06_D22_14 3 14 NA NA HR NA
V21 IO_L22P_T3_A05_D21_14 3 14 NA NA HR NA
V22 IO_L22N_T3_A04_D20_14 3 14 NA NA HR NA
U24 IO_L23P_T3_A03_D19_14 3 14 NA NA HR NA
V24 IO_L23N_T3_A02_D18_14 3 14 NA NA HR NA
W21 IO_L24P_T3_A01_D17_14 3 14 NA NA HR NA
W22 IO_L24N_T3_A00_D16_14 3 14 NA NA HR NA
W19 IO_25_14 NA 14 NA NA HR NA
M19 IO_0_15 NA 15 NA NA HR NA
J23 IO_L1P_T0_AD0P_15 0 15 NA NA HR NA
J24 IO_L1N_T0_AD0N_15 0 15 NA NA HR NA
L22 IO_L2P_T0_AD8P_15 0 15 NA NA HR NA
L23 IO_L2N_T0_AD8N_15 0 15 NA NA HR NA
K23 IO_L3P_T0_DQS_AD1P_15 0 15 NA NA HR NA
K24 IO_L3N_T0_DQS_AD1N_15 0 15 NA NA HR NA
L21 IO_L4P_T0_AD9P_15 0 15 NA NA HR NA
K21 IO_L4N_T0_AD9N_15 0 15 NA NA HR NA
J21 IO_L5P_T0_AD2P_15 0 15 NA NA HR NA
J22 IO_L5N_T0_AD2N_15 0 15 NA NA HR NA
M20 IO_L6P_T0_15 0 15 NA NA HR NA
L20 IO_L6N_T0_VREF_15 0 15 NA NA HR NA
J29 IO_L7P_T1_AD10P_15 1 15 NA NA HR NA
H29 IO_L7N_T1_AD10N_15 1 15 NA NA HR NA
J27 IO_L8P_T1_AD3P_15 1 15 NA NA HR NA
J28 IO_L8N_T1_AD3N_15 1 15 NA NA HR NA
L30 IO_L9P_T1_DQS_AD11P_15 1 15 NA NA HR NA
K30 IO_L9N_T1_DQS_AD11N_15 1 15 NA NA HR NA
K26 IO_L10P_T1_AD4P_15 1 15 NA NA HR NA
J26 IO_L10N_T1_AD4N_15 1 15 NA NA HR NA
L26 IO_L11P_T1_SRCC_AD12P_15 1 15 NA NA HR NA
L27 IO_L11N_T1_SRCC_AD12N_15 1 15 NA NA HR NA
L25 IO_L12P_T1_MRCC_AD5P_15 1 15 NA NA HR NA
K25 IO_L12N_T1_MRCC_AD5N_15 1 15 NA NA HR NA
K28 IO_L13P_T2_MRCC_15 2 15 NA NA HR NA
K29 IO_L13N_T2_MRCC_15 2 15 NA NA HR NA
M28 IO_L14P_T2_SRCC_15 2 15 NA NA HR NA
L28 IO_L14N_T2_SRCC_15 2 15 NA NA HR NA
M29 IO_L15P_T2_DQS_15 2 15 NA NA HR NA
M30 IO_L15N_T2_DQS_ADV_B_15 2 15 NA NA HR NA
N27 IO_L16P_T2_A28_15 2 15 NA NA HR NA
M27 IO_L16N_T2_A27_15 2 15 NA NA HR NA
N29 IO_L17P_T2_A26_15 2 15 NA NA HR NA
N30 IO_L17N_T2_A25_15 2 15 NA NA HR NA
N25 IO_L18P_T2_A24_15 2 15 NA NA HR NA
N26 IO_L18N_T2_A23_15 2 15 NA NA HR NA
N19 IO_L19P_T3_A22_15 3 15 NA NA HR NA
N20 IO_L19N_T3_A21_VREF_15 3 15 NA NA HR NA
N21 IO_L20P_T3_A20_15 3 15 NA NA HR NA
N22 IO_L20N_T3_A19_15 3 15 NA NA HR NA
P23 IO_L21P_T3_DQS_15 3 15 NA NA HR NA
N24 IO_L21N_T3_DQS_A18_15 3 15 NA NA HR NA
P21 IO_L22P_T3_A17_15 3 15 NA NA HR NA
P22 IO_L22N_T3_A16_15 3 15 NA NA HR NA
M24 IO_L23P_T3_FOE_B_15 3 15 NA NA HR NA
M25 IO_L23N_T3_FWE_B_15 3 15 NA NA HR NA
M22 IO_L24P_T3_RS1_15 3 15 NA NA HR NA
M23 IO_L24N_T3_RS0_15 3 15 NA NA HR NA
P19 IO_25_15 NA 15 NA NA HR NA
F23 IO_0_16 NA 16 NA NA HR NA
B23 IO_L1P_T0_16 0 16 NA NA HR NA
A23 IO_L1N_T0_16 0 16 NA NA HR NA
E23 IO_L2P_T0_16 0 16 NA NA HR NA
D23 IO_L2N_T0_16 0 16 NA NA HR NA
F25 IO_L3P_T0_DQS_16 0 16 NA NA HR NA
E25 IO_L3N_T0_DQS_16 0 16 NA NA HR NA
E24 IO_L4P_T0_16 0 16 NA NA HR NA
D24 IO_L4N_T0_16 0 16 NA NA HR NA
F26 IO_L5P_T0_16 0 16 NA NA HR NA
E26 IO_L5N_T0_16 0 16 NA NA HR NA
G23 IO_L6P_T0_16 0 16 NA NA HR NA
G24 IO_L6N_T0_VREF_16 0 16 NA NA HR NA
B27 IO_L7P_T1_16 1 16 NA NA HR NA
A27 IO_L7N_T1_16 1 16 NA NA HR NA
C24 IO_L8P_T1_16 1 16 NA NA HR NA
B24 IO_L8N_T1_16 1 16 NA NA HR NA
B28 IO_L9P_T1_DQS_16 1 16 NA NA HR NA
A28 IO_L9N_T1_DQS_16 1 16 NA NA HR NA
A25 IO_L10P_T1_16 1 16 NA NA HR NA
A26 IO_L10N_T1_16 1 16 NA NA HR NA
D26 IO_L11P_T1_SRCC_16 1 16 NA NA HR NA
C26 IO_L11N_T1_SRCC_16 1 16 NA NA HR NA
C25 IO_L12P_T1_MRCC_16 1 16 NA NA HR NA
B25 IO_L12N_T1_MRCC_16 1 16 NA NA HR NA
D27 IO_L13P_T2_MRCC_16 2 16 NA NA HR NA
C27 IO_L13N_T2_MRCC_16 2 16 NA NA HR NA
E28 IO_L14P_T2_SRCC_16 2 16 NA NA HR NA
D28 IO_L14N_T2_SRCC_16 2 16 NA NA HR NA
C29 IO_L15P_T2_DQS_16 2 16 NA NA HR NA
B29 IO_L15N_T2_DQS_16 2 16 NA NA HR NA
D29 IO_L16P_T2_16 2 16 NA NA HR NA
C30 IO_L16N_T2_16 2 16 NA NA HR NA
B30 IO_L17P_T2_16 2 16 NA NA HR NA
A30 IO_L17N_T2_16 2 16 NA NA HR NA
E29 IO_L18P_T2_16 2 16 NA NA HR NA
E30 IO_L18N_T2_16 2 16 NA NA HR NA
H24 IO_L19P_T3_16 3 16 NA NA HR NA
H25 IO_L19N_T3_VREF_16 3 16 NA NA HR NA
G28 IO_L20P_T3_16 3 16 NA NA HR NA
F28 IO_L20N_T3_16 3 16 NA NA HR NA
G27 IO_L21P_T3_DQS_16 3 16 NA NA HR NA
F27 IO_L21N_T3_DQS_16 3 16 NA NA HR NA
G29 IO_L22P_T3_16 3 16 NA NA HR NA
F30 IO_L22N_T3_16 3 16 NA NA HR NA
H26 IO_L23P_T3_16 3 16 NA NA HR NA
H27 IO_L23N_T3_16 3 16 NA NA HR NA
H30 IO_L24P_T3_16 3 16 NA NA HR NA
G30 IO_L24N_T3_16 3 16 NA NA HR NA
G25 IO_25_16 NA 16 NA NA HR NA
G19 IO_0_17 NA 17 NA NA HR NA
K18 IO_L1P_T0_17 0 17 NA NA HR NA
J18 IO_L1N_T0_17 0 17 NA NA HR NA
H20 IO_L2P_T0_17 0 17 NA NA HR NA
G20 IO_L2N_T0_17 0 17 NA NA HR NA
J17 IO_L3P_T0_DQS_17 0 17 NA NA HR NA
H17 IO_L3N_T0_DQS_17 0 17 NA NA HR NA
J19 IO_L4P_T0_17 0 17 NA NA HR NA
H19 IO_L4N_T0_17 0 17 NA NA HR NA
L17 IO_L5P_T0_17 0 17 NA NA HR NA
L18 IO_L5N_T0_17 0 17 NA NA HR NA
K19 IO_L6P_T0_17 0 17 NA NA HR NA
K20 IO_L6N_T0_VREF_17 0 17 NA NA HR NA
H21 IO_L7P_T1_17 1 17 NA NA HR NA
H22 IO_L7N_T1_17 1 17 NA NA HR NA
D21 IO_L8P_T1_17 1 17 NA NA HR NA
C21 IO_L8N_T1_17 1 17 NA NA HR NA
G22 IO_L9P_T1_DQS_17 1 17 NA NA HR NA
F22 IO_L9N_T1_DQS_17 1 17 NA NA HR NA
D22 IO_L10P_T1_17 1 17 NA NA HR NA
C22 IO_L10N_T1_17 1 17 NA NA HR NA
F21 IO_L11P_T1_SRCC_17 1 17 NA NA HR NA
E21 IO_L11N_T1_SRCC_17 1 17 NA NA HR NA
F20 IO_L12P_T1_MRCC_17 1 17 NA NA HR NA
E20 IO_L12N_T1_MRCC_17 1 17 NA NA HR NA
D17 IO_L13P_T2_MRCC_17 2 17 NA NA HR NA
D18 IO_L13N_T2_MRCC_17 2 17 NA NA HR NA
E19 IO_L14P_T2_SRCC_17 2 17 NA NA HR NA
D19 IO_L14N_T2_SRCC_17 2 17 NA NA HR NA
D16 IO_L15P_T2_DQS_17 2 17 NA NA HR NA
C16 IO_L15N_T2_DQS_17 2 17 NA NA HR NA
G18 IO_L16P_T2_17 2 17 NA NA HR NA
F18 IO_L16N_T2_17 2 17 NA NA HR NA
C17 IO_L17P_T2_17 2 17 NA NA HR NA
B17 IO_L17N_T2_17 2 17 NA NA HR NA
G17 IO_L18P_T2_17 2 17 NA NA HR NA
F17 IO_L18N_T2_17 2 17 NA NA HR NA
C20 IO_L19P_T3_17 3 17 NA NA HR NA
B20 IO_L19N_T3_VREF_17 3 17 NA NA HR NA
A16 IO_L20P_T3_17 3 17 NA NA HR NA
A17 IO_L20N_T3_17 3 17 NA NA HR NA
A20 IO_L21P_T3_DQS_17 3 17 NA NA HR NA
A21 IO_L21N_T3_DQS_17 3 17 NA NA HR NA
B18 IO_L22P_T3_17 3 17 NA NA HR NA
A18 IO_L22N_T3_17 3 17 NA NA HR NA
B22 IO_L23P_T3_17 3 17 NA NA HR NA
A22 IO_L23N_T3_17 3 17 NA NA HR NA
C19 IO_L24P_T3_17 3 17 NA NA HR NA
B19 IO_L24N_T3_17 3 17 NA NA HR NA
E18 IO_25_17 NA 17 NA NA HR NA
G12 IO_0_18 NA 18 NA NA HR NA
L16 IO_L1P_T0_18 0 18 NA NA HR NA
K16 IO_L1N_T0_18 0 18 NA NA HR NA
L15 IO_L2P_T0_18 0 18 NA NA HR NA
K15 IO_L2N_T0_18 0 18 NA NA HR NA
L12 IO_L3P_T0_DQS_18 0 18 NA NA HR NA
L13 IO_L3N_T0_DQS_18 0 18 NA NA HR NA
K13 IO_L4P_T0_18 0 18 NA NA HR NA
J13 IO_L4N_T0_18 0 18 NA NA HR NA
K14 IO_L5P_T0_18 0 18 NA NA HR NA
J14 IO_L5N_T0_18 0 18 NA NA HR NA
L11 IO_L6P_T0_18 0 18 NA NA HR NA
K11 IO_L6N_T0_VREF_18 0 18 NA NA HR NA
H15 IO_L7P_T1_18 1 18 NA NA HR NA
G15 IO_L7N_T1_18 1 18 NA NA HR NA
J11 IO_L8P_T1_18 1 18 NA NA HR NA
J12 IO_L8N_T1_18 1 18 NA NA HR NA
J16 IO_L9P_T1_DQS_18 1 18 NA NA HR NA
H16 IO_L9N_T1_DQS_18 1 18 NA NA HR NA
H11 IO_L10P_T1_18 1 18 NA NA HR NA
H12 IO_L10N_T1_18 1 18 NA NA HR NA
H14 IO_L11P_T1_SRCC_18 1 18 NA NA HR NA
G14 IO_L11N_T1_SRCC_18 1 18 NA NA HR NA
G13 IO_L12P_T1_MRCC_18 1 18 NA NA HR NA
F13 IO_L12N_T1_MRCC_18 1 18 NA NA HR NA
D12 IO_L13P_T2_MRCC_18 2 18 NA NA HR NA
D13 IO_L13N_T2_MRCC_18 2 18 NA NA HR NA
F12 IO_L14P_T2_SRCC_18 2 18 NA NA HR NA
E13 IO_L14N_T2_SRCC_18 2 18 NA NA HR NA
C12 IO_L15P_T2_DQS_18 2 18 NA NA HR NA
B12 IO_L15N_T2_DQS_18 2 18 NA NA HR NA
F11 IO_L16P_T2_18 2 18 NA NA HR NA
E11 IO_L16N_T2_18 2 18 NA NA HR NA
A11 IO_L17P_T2_18 2 18 NA NA HR NA
A12 IO_L17N_T2_18 2 18 NA NA HR NA
D11 IO_L18P_T2_18 2 18 NA NA HR NA
C11 IO_L18N_T2_18 2 18 NA NA HR NA
F15 IO_L19P_T3_18 3 18 NA NA HR NA
E16 IO_L19N_T3_VREF_18 3 18 NA NA HR NA
E14 IO_L20P_T3_18 3 18 NA NA HR NA
E15 IO_L20N_T3_18 3 18 NA NA HR NA
D14 IO_L21P_T3_DQS_18 3 18 NA NA HR NA
C14 IO_L21N_T3_DQS_18 3 18 NA NA HR NA
B13 IO_L22P_T3_18 3 18 NA NA HR NA
A13 IO_L22N_T3_18 3 18 NA NA HR NA
C15 IO_L23P_T3_18 3 18 NA NA HR NA
B15 IO_L23N_T3_18 3 18 NA NA HR NA
B14 IO_L24P_T3_18 3 18 NA NA HR NA
A15 IO_L24N_T3_18 3 18 NA NA HR NA
F16 IO_25_18 NA 18 NA NA HR NA
Y14 IO_0_VRN_32 NA 32 0 NA HP NA
AK16 IO_L1P_T0_32 0 32 0 NA HP NA
AK15 IO_L1N_T0_32 0 32 0 NA HP NA
AG15 IO_L2P_T0_32 0 32 0 NA HP NA
AH15 IO_L2N_T0_32 0 32 0 NA HP NA
AH16 IO_L3P_T0_DQS_32 0 32 0 NA HP NA
AJ16 IO_L3N_T0_DQS_32 0 32 0 NA HP NA
AF15 IO_L4P_T0_32 0 32 0 NA HP NA
AG14 IO_L4N_T0_32 0 32 0 NA HP NA
AH17 IO_L5P_T0_32 0 32 0 NA HP NA
AJ17 IO_L5N_T0_32 0 32 0 NA HP NA
AE16 IO_L6P_T0_32 0 32 0 NA HP NA
AF16 IO_L6N_T0_VREF_32 0 32 0 NA HP NA
AJ19 IO_L7P_T1_32 1 32 0 NA HP NA
AK19 IO_L7N_T1_32 1 32 0 NA HP NA
AG19 IO_L8P_T1_32 1 32 0 NA HP NA
AH19 IO_L8N_T1_32 1 32 0 NA HP NA
AJ18 IO_L9P_T1_DQS_32 1 32 0 NA HP NA
AK18 IO_L9N_T1_DQS_32 1 32 0 NA HP NA
AD19 IO_L10P_T1_32 1 32 0 NA HP NA
AE19 IO_L10N_T1_32 1 32 0 NA HP NA
AF18 IO_L11P_T1_SRCC_32 1 32 0 NA HP NA
AG18 IO_L11N_T1_SRCC_32 1 32 0 NA HP NA
AF17 IO_L12P_T1_MRCC_32 1 32 0 NA HP NA
AG17 IO_L12N_T1_MRCC_32 1 32 0 NA HP NA
AD18 IO_L13P_T2_MRCC_32 2 32 0 NA HP NA
AE18 IO_L13N_T2_MRCC_32 2 32 0 NA HP NA
AD17 IO_L14P_T2_SRCC_32 2 32 0 NA HP NA
AD16 IO_L14N_T2_SRCC_32 2 32 0 NA HP NA
Y19 IO_L15P_T2_DQS_32 2 32 0 NA HP NA
Y18 IO_L15N_T2_DQS_32 2 32 0 NA HP NA
AA18 IO_L16P_T2_32 2 32 0 NA HP NA
AB18 IO_L16N_T2_32 2 32 0 NA HP NA
AB19 IO_L17P_T2_32 2 32 0 NA HP NA
AC19 IO_L17N_T2_32 2 32 0 NA HP NA
AB17 IO_L18P_T2_32 2 32 0 NA HP NA
AC17 IO_L18N_T2_32 2 32 0 NA HP NA
AE15 IO_L19P_T3_32 3 32 0 NA HP NA
AE14 IO_L19N_T3_VREF_32 3 32 0 NA HP NA
AA15 IO_L20P_T3_32 3 32 0 NA HP NA
AB15 IO_L20N_T3_32 3 32 0 NA HP NA
AC16 IO_L21P_T3_DQS_32 3 32 0 NA HP NA
AC15 IO_L21N_T3_DQS_32 3 32 0 NA HP NA
AC14 IO_L22P_T3_32 3 32 0 NA HP NA
AD14 IO_L22N_T3_32 3 32 0 NA HP NA
AA17 IO_L23P_T3_32 3 32 0 NA HP NA
AA16 IO_L23N_T3_32 3 32 0 NA HP NA
Y16 IO_L24P_T3_32 3 32 0 NA HP NA
Y15 IO_L24N_T3_32 3 32 0 NA HP NA
AB14 IO_25_VRP_32 NA 32 0 NA HP NA
Y13 IO_0_VRN_33 NA 33 0 NA HP NA
AA12 IO_L1P_T0_33 0 33 0 NA HP NA
AB12 IO_L1N_T0_33 0 33 0 NA HP NA
AA8 IO_L2P_T0_33 0 33 0 NA HP NA
AB8 IO_L2N_T0_33 0 33 0 NA HP NA
AB9 IO_L3P_T0_DQS_33 0 33 0 NA HP NA
AC9 IO_L3N_T0_DQS_33 0 33 0 NA HP NA
Y11 IO_L4P_T0_33 0 33 0 NA HP NA
Y10 IO_L4N_T0_33 0 33 0 NA HP NA
AA11 IO_L5P_T0_33 0 33 0 NA HP NA
AA10 IO_L5N_T0_33 0 33 0 NA HP NA
AA13 IO_L6P_T0_33 0 33 0 NA HP NA
AB13 IO_L6N_T0_VREF_33 0 33 0 NA HP NA
AB10 IO_L7P_T1_33 1 33 0 NA HP NA
AC10 IO_L7N_T1_33 1 33 0 NA HP NA
AD8 IO_L8P_T1_33 1 33 0 NA HP NA
AE8 IO_L8N_T1_33 1 33 0 NA HP NA
AC12 IO_L9P_T1_DQS_33 1 33 0 NA HP NA
AC11 IO_L9N_T1_DQS_33 1 33 0 NA HP NA
AD9 IO_L10P_T1_33 1 33 0 NA HP NA
AE9 IO_L10N_T1_33 1 33 0 NA HP NA
AE11 IO_L11P_T1_SRCC_33 1 33 0 NA HP NA
AF11 IO_L11N_T1_SRCC_33 1 33 0 NA HP NA
AD12 IO_L12P_T1_MRCC_33 1 33 0 NA HP NA
AD11 IO_L12N_T1_MRCC_33 1 33 0 NA HP NA
AG10 IO_L13P_T2_MRCC_33 2 33 0 NA HP NA
AH10 IO_L13N_T2_MRCC_33 2 33 0 NA HP NA
AE10 IO_L14P_T2_SRCC_33 2 33 0 NA HP NA
AF10 IO_L14N_T2_SRCC_33 2 33 0 NA HP NA
AJ9 IO_L15P_T2_DQS_33 2 33 0 NA HP NA
AK9 IO_L15N_T2_DQS_33 2 33 0 NA HP NA
AG9 IO_L16P_T2_33 2 33 0 NA HP NA
AH9 IO_L16N_T2_33 2 33 0 NA HP NA
AK11 IO_L17P_T2_33 2 33 0 NA HP NA
AK10 IO_L17N_T2_33 2 33 0 NA HP NA
AH11 IO_L18P_T2_33 2 33 0 NA HP NA
AJ11 IO_L18N_T2_33 2 33 0 NA HP NA
AE13 IO_L19P_T3_33 3 33 0 NA HP NA
AF13 IO_L19N_T3_VREF_33 3 33 0 NA HP NA
AK14 IO_L20P_T3_33 3 33 0 NA HP NA
AK13 IO_L20N_T3_33 3 33 0 NA HP NA
AH14 IO_L21P_T3_DQS_33 3 33 0 NA HP NA
AJ14 IO_L21N_T3_DQS_33 3 33 0 NA HP NA
AJ13 IO_L22P_T3_33 3 33 0 NA HP NA
AJ12 IO_L22N_T3_33 3 33 0 NA HP NA
AF12 IO_L23P_T3_33 3 33 0 NA HP NA
AG12 IO_L23N_T3_33 3 33 0 NA HP NA
AG13 IO_L24P_T3_33 3 33 0 NA HP NA
AH12 IO_L24N_T3_33 3 33 0 NA HP NA
AD13 IO_25_VRP_33 NA 33 0 NA HP NA
AC6 IO_0_VRN_34 NA 34 0 NA HP NA
AD4 IO_L1P_T0_34 0 34 0 NA HP NA
AD3 IO_L1N_T0_34 0 34 0 NA HP NA
AC2 IO_L2P_T0_34 0 34 0 NA HP NA
AC1 IO_L2N_T0_34 0 34 0 NA HP NA
AD2 IO_L3P_T0_DQS_34 0 34 0 NA HP NA
AD1 IO_L3N_T0_DQS_34 0 34 0 NA HP NA
AC5 IO_L4P_T0_34 0 34 0 NA HP NA
AC4 IO_L4N_T0_34 0 34 0 NA HP NA
AD6 IO_L5P_T0_34 0 34 0 NA HP NA
AE6 IO_L5N_T0_34 0 34 0 NA HP NA
AC7 IO_L6P_T0_34 0 34 0 NA HP NA
AD7 IO_L6N_T0_VREF_34 0 34 0 NA HP NA
AF3 IO_L7P_T1_34 1 34 0 NA HP NA
AF2 IO_L7N_T1_34 1 34 0 NA HP NA
AE1 IO_L8P_T1_34 1 34 0 NA HP NA
AF1 IO_L8N_T1_34 1 34 0 NA HP NA
AG4 IO_L9P_T1_DQS_34 1 34 0 NA HP NA
AG3 IO_L9N_T1_DQS_34 1 34 0 NA HP NA
AE4 IO_L10P_T1_34 1 34 0 NA HP NA
AE3 IO_L10N_T1_34 1 34 0 NA HP NA
AE5 IO_L11P_T1_SRCC_34 1 34 0 NA HP NA
AF5 IO_L11N_T1_SRCC_34 1 34 0 NA HP NA
AF6 IO_L12P_T1_MRCC_34 1 34 0 NA HP NA
AG5 IO_L12N_T1_MRCC_34 1 34 0 NA HP NA
AH4 IO_L13P_T2_MRCC_34 2 34 0 NA HP NA
AJ4 IO_L13N_T2_MRCC_34 2 34 0 NA HP NA
AH6 IO_L14P_T2_SRCC_34 2 34 0 NA HP NA
AH5 IO_L14N_T2_SRCC_34 2 34 0 NA HP NA
AG2 IO_L15P_T2_DQS_34 2 34 0 NA HP NA
AH1 IO_L15N_T2_DQS_34 2 34 0 NA HP NA
AH2 IO_L16P_T2_34 2 34 0 NA HP NA
AJ2 IO_L16N_T2_34 2 34 0 NA HP NA
AJ1 IO_L17P_T2_34 2 34 0 NA HP NA
AK1 IO_L17N_T2_34 2 34 0 NA HP NA
AJ3 IO_L18P_T2_34 2 34 0 NA HP NA
AK3 IO_L18N_T2_34 2 34 0 NA HP NA
AF8 IO_L19P_T3_34 3 34 0 NA HP NA
AG8 IO_L19N_T3_VREF_34 3 34 0 NA HP NA
AF7 IO_L20P_T3_34 3 34 0 NA HP NA
AG7 IO_L20N_T3_34 3 34 0 NA HP NA
AH7 IO_L21P_T3_DQS_34 3 34 0 NA HP NA
AJ7 IO_L21N_T3_DQS_34 3 34 0 NA HP NA
AJ6 IO_L22P_T3_34 3 34 0 NA HP NA
AK6 IO_L22N_T3_34 3 34 0 NA HP NA
AJ8 IO_L23P_T3_34 3 34 0 NA HP NA
AK8 IO_L23N_T3_34 3 34 0 NA HP NA
AK5 IO_L24P_T3_34 3 34 0 NA HP NA
AK4 IO_L24N_T3_34 3 34 0 NA HP NA
AB7 IO_25_VRP_34 NA 34 0 NA HP NA
T2 MGTXTXP3_115 NA 115 NA NA GTX NA
V6 MGTXRXP3_115 NA 115 NA NA GTX NA
T1 MGTXTXN3_115 NA 115 NA NA GTX NA
V5 MGTXRXN3_115 NA 115 NA NA GTX NA
U4 MGTXTXP2_115 NA 115 NA NA GTX NA
W4 MGTXRXP2_115 NA 115 NA NA GTX NA
U3 MGTXTXN2_115 NA 115 NA NA GTX NA
R8 MGTREFCLK0P_115 NA 115 NA NA GTX NA
W3 MGTXRXN2_115 NA 115 NA NA GTX NA
W7 MGTAVTTRCAL_115 NA 115 NA NA GTX NA
R7 MGTREFCLK0N_115 NA 115 NA NA GTX NA
W8 MGTRREF_115 NA 115 NA NA GTX NA
U7 MGTREFCLK1N_115 NA 115 NA NA GTX NA
U8 MGTREFCLK1P_115 NA 115 NA NA GTX NA
V2 MGTXTXP1_115 NA 115 NA NA GTX NA
Y6 MGTXRXP1_115 NA 115 NA NA GTX NA
V1 MGTXTXN1_115 NA 115 NA NA GTX NA
Y5 MGTXRXN1_115 NA 115 NA NA GTX NA
Y2 MGTXTXP0_115 NA 115 NA NA GTX NA
AA4 MGTXRXP0_115 NA 115 NA NA GTX NA
Y1 MGTXTXN0_115 NA 115 NA NA GTX NA
AA3 MGTXRXN0_115 NA 115 NA NA GTX NA
L4 MGTXTXP3_116 NA 116 NA NA GTX NA
M6 MGTXRXP3_116 NA 116 NA NA GTX NA
L3 MGTXTXN3_116 NA 116 NA NA GTX NA
M5 MGTXRXN3_116 NA 116 NA NA GTX NA
M2 MGTXTXP2_116 NA 116 NA NA GTX NA
P6 MGTXRXP2_116 NA 116 NA NA GTX NA
M1 MGTXTXN2_116 NA 116 NA NA GTX NA
L8 MGTREFCLK0P_116 NA 116 NA NA GTX NA
P5 MGTXRXN2_116 NA 116 NA NA GTX NA
L7 MGTREFCLK0N_116 NA 116 NA NA GTX NA
N7 MGTREFCLK1N_116 NA 116 NA NA GTX NA
N8 MGTREFCLK1P_116 NA 116 NA NA GTX NA
N4 MGTXTXP1_116 NA 116 NA NA GTX NA
R4 MGTXRXP1_116 NA 116 NA NA GTX NA
N3 MGTXTXN1_116 NA 116 NA NA GTX NA
R3 MGTXRXN1_116 NA 116 NA NA GTX NA
P2 MGTXTXP0_116 NA 116 NA NA GTX NA
T6 MGTXRXP0_116 NA 116 NA NA GTX NA
P1 MGTXTXN0_116 NA 116 NA NA GTX NA
T5 MGTXRXN0_116 NA 116 NA NA GTX NA
F2 MGTXTXP3_117 NA 117 NA NA GTX NA
F6 MGTXRXP3_117 NA 117 NA NA GTX NA
F1 MGTXTXN3_117 NA 117 NA NA GTX NA
F5 MGTXRXN3_117 NA 117 NA NA GTX NA
H2 MGTXTXP2_117 NA 117 NA NA GTX NA
G4 MGTXRXP2_117 NA 117 NA NA GTX NA
H1 MGTXTXN2_117 NA 117 NA NA GTX NA
G8 MGTREFCLK0P_117 NA 117 NA NA GTX NA
G3 MGTXRXN2_117 NA 117 NA NA GTX NA
G7 MGTREFCLK0N_117 NA 117 NA NA GTX NA
J7 MGTREFCLK1N_117 NA 117 NA NA GTX NA
J8 MGTREFCLK1P_117 NA 117 NA NA GTX NA
J4 MGTXTXP1_117 NA 117 NA NA GTX NA
H6 MGTXRXP1_117 NA 117 NA NA GTX NA
J3 MGTXTXN1_117 NA 117 NA NA GTX NA
H5 MGTXRXN1_117 NA 117 NA NA GTX NA
K2 MGTXTXP0_117 NA 117 NA NA GTX NA
K6 MGTXRXP0_117 NA 117 NA NA GTX NA
K1 MGTXTXN0_117 NA 117 NA NA GTX NA
K5 MGTXRXN0_117 NA 117 NA NA GTX NA
A4 MGTXTXP3_118 NA 118 NA NA GTX NA
A8 MGTXRXP3_118 NA 118 NA NA GTX NA
A3 MGTXTXN3_118 NA 118 NA NA GTX NA
A7 MGTXRXN3_118 NA 118 NA NA GTX NA
B2 MGTXTXP2_118 NA 118 NA NA GTX NA
B6 MGTXRXP2_118 NA 118 NA NA GTX NA
B1 MGTXTXN2_118 NA 118 NA NA GTX NA
C8 MGTREFCLK0P_118 NA 118 NA NA GTX NA
B5 MGTXRXN2_118 NA 118 NA NA GTX NA
C7 MGTREFCLK0N_118 NA 118 NA NA GTX NA
E7 MGTREFCLK1N_118 NA 118 NA NA GTX NA
E8 MGTREFCLK1P_118 NA 118 NA NA GTX NA
C4 MGTXTXP1_118 NA 118 NA NA GTX NA
D6 MGTXRXP1_118 NA 118 NA NA GTX NA
C3 MGTXTXN1_118 NA 118 NA NA GTX NA
D5 MGTXRXN1_118 NA 118 NA NA GTX NA
D2 MGTXTXP0_118 NA 118 NA NA GTX NA
E4 MGTXRXP0_118 NA 118 NA NA GTX NA
D1 MGTXTXN0_118 NA 118 NA NA GTX NA
E3 MGTXRXN0_118 NA 118 NA NA GTX NA
B7 MGTAVCC NA NA NA NA NA NA
D7 MGTAVCC NA NA NA NA NA NA
F7 MGTAVCC NA NA NA NA NA NA
H7 MGTAVCC NA NA NA NA NA NA
K7 MGTAVCC NA NA NA NA NA NA
M7 MGTAVCC NA NA NA NA NA NA
P7 MGTAVCC NA NA NA NA NA NA
T7 MGTVCCAUX NA NA NA NA NA NA
V7 MGTVCCAUX NA NA NA NA NA NA
B3 MGTAVTT NA NA NA NA NA NA
C5 MGTAVTT NA NA NA NA NA NA
D3 MGTAVTT NA NA NA NA NA NA
E5 MGTAVTT NA NA NA NA NA NA
F3 MGTAVTT NA NA NA NA NA NA
G5 MGTAVTT NA NA NA NA NA NA
H3 MGTAVTT NA NA NA NA NA NA
J5 MGTAVTT NA NA NA NA NA NA
K3 MGTAVTT NA NA NA NA NA NA
L5 MGTAVTT NA NA NA NA NA NA
M3 MGTAVTT NA NA NA NA NA NA
N5 MGTAVTT NA NA NA NA NA NA
P3 MGTAVTT NA NA NA NA NA NA
R5 MGTAVTT NA NA NA NA NA NA
T3 MGTAVTT NA NA NA NA NA NA
U5 MGTAVTT NA NA NA NA NA NA
V3 MGTAVTT NA NA NA NA NA NA
W5 MGTAVTT NA NA NA NA NA NA
N16 VCCBRAM NA NA NA NA NA NA
R16 VCCBRAM NA NA NA NA NA NA
U16 VCCBRAM NA NA NA NA NA NA
W16 VCCBRAM NA NA NA NA NA NA
A1 GND NA NA NA NA NA NA
A14 GND NA NA NA NA NA NA
A2 GND NA NA NA NA NA NA
A24 GND NA NA NA NA NA NA
A5 GND NA NA NA NA NA NA
A6 GND NA NA NA NA NA NA
A9 GND NA NA NA NA NA NA
AA1 GND NA NA NA NA NA NA
AA14 GND NA NA NA NA NA NA
AA2 GND NA NA NA NA NA NA
AA24 GND NA NA NA NA NA NA
AA5 GND NA NA NA NA NA NA
AA6 GND NA NA NA NA NA NA
AA7 GND NA NA NA NA NA NA
AB11 GND NA NA NA NA NA NA
AB21 GND NA NA NA NA NA NA
AB3 GND NA NA NA NA NA NA
AB4 GND NA NA NA NA NA NA
AC18 GND NA NA NA NA NA NA
AC28 GND NA NA NA NA NA NA
AC8 GND NA NA NA NA NA NA
AD15 GND NA NA NA NA NA NA
AD25 GND NA NA NA NA NA NA
AD5 GND NA NA NA NA NA NA
AE12 GND NA NA NA NA NA NA
AE2 GND NA NA NA NA NA NA
AE22 GND NA NA NA NA NA NA
AF19 GND NA NA NA NA NA NA
AF29 GND NA NA NA NA NA NA
AF9 GND NA NA NA NA NA NA
AG16 GND NA NA NA NA NA NA
AG26 GND NA NA NA NA NA NA
AG6 GND NA NA NA NA NA NA
AH13 GND NA NA NA NA NA NA
AH23 GND NA NA NA NA NA NA
AH3 GND NA NA NA NA NA NA
AJ10 GND NA NA NA NA NA NA
AJ20 GND NA NA NA NA NA NA
AJ30 GND NA NA NA NA NA NA
AK17 GND NA NA NA NA NA NA
AK27 GND NA NA NA NA NA NA
AK7 GND NA NA NA NA NA NA
B11 GND NA NA NA NA NA NA
B21 GND NA NA NA NA NA NA
B4 GND NA NA NA NA NA NA
B8 GND NA NA NA NA NA NA
B9 GND NA NA NA NA NA NA
C1 GND NA NA NA NA NA NA
C18 GND NA NA NA NA NA NA
C2 GND NA NA NA NA NA NA
C28 GND NA NA NA NA NA NA
C6 GND NA NA NA NA NA NA
C9 GND NA NA NA NA NA NA
D15 GND NA NA NA NA NA NA
D25 GND NA NA NA NA NA NA
D4 GND NA NA NA NA NA NA
D8 GND NA NA NA NA NA NA
D9 GND NA NA NA NA NA NA
E1 GND NA NA NA NA NA NA
E12 GND NA NA NA NA NA NA
E2 GND NA NA NA NA NA NA
E22 GND NA NA NA NA NA NA
E6 GND NA NA NA NA NA NA
E9 GND NA NA NA NA NA NA
F19 GND NA NA NA NA NA NA
F29 GND NA NA NA NA NA NA
F4 GND NA NA NA NA NA NA
F8 GND NA NA NA NA NA NA
F9 GND NA NA NA NA NA NA
G1 GND NA NA NA NA NA NA
G16 GND NA NA NA NA NA NA
G2 GND NA NA NA NA NA NA
G26 GND NA NA NA NA NA NA
G6 GND NA NA NA NA NA NA
G9 GND NA NA NA NA NA NA
H13 GND NA NA NA NA NA NA
H23 GND NA NA NA NA NA NA
H4 GND NA NA NA NA NA NA
H8 GND NA NA NA NA NA NA
H9 GND NA NA NA NA NA NA
J1 GND NA NA NA NA NA NA
J10 GND NA NA NA NA NA NA
J2 GND NA NA NA NA NA NA
J20 GND NA NA NA NA NA NA
J30 GND NA NA NA NA NA NA
J6 GND NA NA NA NA NA NA
J9 GND NA NA NA NA NA NA
K17 GND NA NA NA NA NA NA
K27 GND NA NA NA NA NA NA
K4 GND NA NA NA NA NA NA
K8 GND NA NA NA NA NA NA
K9 GND NA NA NA NA NA NA
L1 GND NA NA NA NA NA NA
L14 GND NA NA NA NA NA NA
L2 GND NA NA NA NA NA NA
L24 GND NA NA NA NA NA NA
L6 GND NA NA NA NA NA NA
L9 GND NA NA NA NA NA NA
M12 GND NA NA NA NA NA NA
M14 GND NA NA NA NA NA NA
M16 GND NA NA NA NA NA NA
M18 GND NA NA NA NA NA NA
M21 GND NA NA NA NA NA NA
M4 GND NA NA NA NA NA NA
M8 GND NA NA NA NA NA NA
M9 GND NA NA NA NA NA NA
N1 GND NA NA NA NA NA NA
N11 GND NA NA NA NA NA NA
N13 GND NA NA NA NA NA NA
N15 GND NA NA NA NA NA NA
N17 GND NA NA NA NA NA NA
N2 GND NA NA NA NA NA NA
N28 GND NA NA NA NA NA NA
N6 GND NA NA NA NA NA NA
N9 GND NA NA NA NA NA NA
P10 GND NA NA NA NA NA NA
P12 GND NA NA NA NA NA NA
P16 GND NA NA NA NA NA NA
P18 GND NA NA NA NA NA NA
P25 GND NA NA NA NA NA NA
P4 GND NA NA NA NA NA NA
P8 GND NA NA NA NA NA NA
P9 GND NA NA NA NA NA NA
R1 GND NA NA NA NA NA NA
R11 GND NA NA NA NA NA NA
R13 GND NA NA NA NA NA NA
R17 GND NA NA NA NA NA NA
R2 GND NA NA NA NA NA NA
R22 GND NA NA NA NA NA NA
R6 GND NA NA NA NA NA NA
R9 GND NA NA NA NA NA NA
T10 GND NA NA NA NA NA NA
T12 GND NA NA NA NA NA NA
T16 GND NA NA NA NA NA NA
T18 GND NA NA NA NA NA NA
T19 GND NA NA NA NA NA NA
T29 GND NA NA NA NA NA NA
T4 GND NA NA NA NA NA NA
T8 GND NA NA NA NA NA NA
U1 GND NA NA NA NA NA NA
U11 GND NA NA NA NA NA NA
U13 GND NA NA NA NA NA NA
U17 GND NA NA NA NA NA NA
U2 GND NA NA NA NA NA NA
U26 GND NA NA NA NA NA NA
U6 GND NA NA NA NA NA NA
U9 GND NA NA NA NA NA NA
V10 GND NA NA NA NA NA NA
V12 GND NA NA NA NA NA NA
V14 GND NA NA NA NA NA NA
V16 GND NA NA NA NA NA NA
V18 GND NA NA NA NA NA NA
V23 GND NA NA NA NA NA NA
V4 GND NA NA NA NA NA NA
V8 GND NA NA NA NA NA NA
V9 GND NA NA NA NA NA NA
W1 GND NA NA NA NA NA NA
W11 GND NA NA NA NA NA NA
W13 GND NA NA NA NA NA NA
W15 GND NA NA NA NA NA NA
W17 GND NA NA NA NA NA NA
W2 GND NA NA NA NA NA NA
W20 GND NA NA NA NA NA NA
W30 GND NA NA NA NA NA NA
W6 GND NA NA NA NA NA NA
W9 GND NA NA NA NA NA NA
Y17 GND NA NA NA NA NA NA
Y27 GND NA NA NA NA NA NA
Y3 GND NA NA NA NA NA NA
Y4 GND NA NA NA NA NA NA
Y7 GND NA NA NA NA NA NA
Y8 GND NA NA NA NA NA NA
Y9 GND NA NA NA NA NA NA
M11 VCCINT NA NA NA NA NA NA
M13 VCCINT NA NA NA NA NA NA
M15 VCCINT NA NA NA NA NA NA
M17 VCCINT NA NA NA NA NA NA
N10 VCCINT NA NA NA NA NA NA
N12 VCCINT NA NA NA NA NA NA
N14 VCCINT NA NA NA NA NA NA
N18 VCCINT NA NA NA NA NA NA
P11 VCCINT NA NA NA NA NA NA
P17 VCCINT NA NA NA NA NA NA
R10 VCCINT NA NA NA NA NA NA
R12 VCCINT NA NA NA NA NA NA
R18 VCCINT NA NA NA NA NA NA
T11 VCCINT NA NA NA NA NA NA
T17 VCCINT NA NA NA NA NA NA
U10 VCCINT NA NA NA NA NA NA
U12 VCCINT NA NA NA NA NA NA
U18 VCCINT NA NA NA NA NA NA
V17 VCCINT NA NA NA NA NA NA
W18 VCCINT NA NA NA NA NA NA
P13 VCCAUX NA NA NA NA NA NA
T13 VCCAUX NA NA NA NA NA NA
V13 VCCAUX NA NA NA NA NA NA
V15 VCCAUX NA NA NA NA NA NA
W14 VCCAUX NA NA NA NA NA NA
W12 VCCAUX_IO_G0 NA NA NA NA NA NA
V11 VCCAUX_IO_G0 NA NA NA NA NA NA
W10 VCCAUX_IO_G0 NA NA NA NA NA NA
AA19 VCCO_32 NA 32 NA NA NA NA
AB16 VCCO_32 NA 32 NA NA NA NA
AE17 VCCO_32 NA 32 NA NA NA NA
AF14 VCCO_32 NA 32 NA NA NA NA
AH18 VCCO_32 NA 32 NA NA NA NA
AJ15 VCCO_32 NA 32 NA NA NA NA
AA9 VCCO_33 NA 33 NA NA NA NA
AC13 VCCO_33 NA 33 NA NA NA NA
AD10 VCCO_33 NA 33 NA NA NA NA
AG11 VCCO_33 NA 33 NA NA NA NA
AK12 VCCO_33 NA 33 NA NA NA NA
Y12 VCCO_33 NA 33 NA NA NA NA
AC3 VCCO_34 NA 34 NA NA NA NA
AE7 VCCO_34 NA 34 NA NA NA NA
AF4 VCCO_34 NA 34 NA NA NA NA
AG1 VCCO_34 NA 34 NA NA NA NA
AH8 VCCO_34 NA 34 NA NA NA NA
AJ5 VCCO_34 NA 34 NA NA NA NA
AK2 VCCO_34 NA 34 NA NA NA NA
AC23 VCCO_12 NA 12 NA NA NA NA
AD20 VCCO_12 NA 12 NA NA NA NA
AF24 VCCO_12 NA 12 NA NA NA NA
AG21 VCCO_12 NA 12 NA NA NA NA
AK22 VCCO_12 NA 12 NA NA NA NA
Y22 VCCO_12 NA 12 NA NA NA NA
AA29 VCCO_13 NA 13 NA NA NA NA
AB26 VCCO_13 NA 13 NA NA NA NA
AD30 VCCO_13 NA 13 NA NA NA NA
AE27 VCCO_13 NA 13 NA NA NA NA
AH28 VCCO_13 NA 13 NA NA NA NA
AJ25 VCCO_13 NA 13 NA NA NA NA
P30 VCCO_14 NA 14 NA NA NA NA
R27 VCCO_14 NA 14 NA NA NA NA
T24 VCCO_14 NA 14 NA NA NA NA
U21 VCCO_14 NA 14 NA NA NA NA
V28 VCCO_14 NA 14 NA NA NA NA
W25 VCCO_14 NA 14 NA NA NA NA
J25 VCCO_15 NA 15 NA NA NA NA
K22 VCCO_15 NA 15 NA NA NA NA
L29 VCCO_15 NA 15 NA NA NA NA
M26 VCCO_15 NA 15 NA NA NA NA
N23 VCCO_15 NA 15 NA NA NA NA
P20 VCCO_15 NA 15 NA NA NA NA
A29 VCCO_16 NA 16 NA NA NA NA
B26 VCCO_16 NA 16 NA NA NA NA
C23 VCCO_16 NA 16 NA NA NA NA
D30 VCCO_16 NA 16 NA NA NA NA
E27 VCCO_16 NA 16 NA NA NA NA
F24 VCCO_16 NA 16 NA NA NA NA
H28 VCCO_16 NA 16 NA NA NA NA
A19 VCCO_17 NA 17 NA NA NA NA
B16 VCCO_17 NA 17 NA NA NA NA
D20 VCCO_17 NA 17 NA NA NA NA
E17 VCCO_17 NA 17 NA NA NA NA
G21 VCCO_17 NA 17 NA NA NA NA
H18 VCCO_17 NA 17 NA NA NA NA
L19 VCCO_17 NA 17 NA NA NA NA
C13 VCCO_18 NA 18 NA NA NA NA
D10 VCCO_18 NA 18 NA NA NA NA
F14 VCCO_18 NA 18 NA NA NA NA
G11 VCCO_18 NA 18 NA NA NA NA
J15 VCCO_18 NA 18 NA NA NA NA
K12 VCCO_18 NA 18 NA NA NA NA
AB6 VCCO_0 NA 0 NA NA NA NA
T9 VCCO_0 NA 0 NA NA NA NA
Total Number of Pins Generated, 900
hdl/testbench/svec7_bridge/Manifest.py 0 → 100644
View file @ 29b98259
action = "simulation"
target = "xilinx"
sim_tool = "modelsim"
sim_top = "main"
vcom_opt = "-93 -mixedsvvh"
syn_device = "xc7k325t"
svec_template_ucf = []
board = "svec7a"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[ "../../ip_cores/vme64x-core/hdl/sim/vme64x_bfm",
"../../ip_cores/general-cores/sim",
"../../ip_cores/general-cores/modules/wishbone/wb_spi",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6",
"." ]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7a",
"../../top/svec7_sfpga",
"../../top/svec7_test",
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core"
],
}
# Do not fail during hdlmake fetch
try:
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/svec7_bridge/buildinfo_pkg.vhd 0 → 100644
View file @ 29b98259
-- Buildinfo for project main
--
-- This file was automatically generated; do not edit
package buildinfo_pkg is
constant buildinfo : string :=
"buildinfo:1" & LF
& "module:main" & LF
& "commit:90348ce26bfdc3ee9b9477c26c91f74450f730db" & LF
& "syntool:modelsim" & LF
& "syndate:2019-11-27, 17:39 CET" & LF
& "synauth:Tomasz Wlostowski" & LF;
end buildinfo_pkg;
hdl/testbench/svec7_bridge/main.sv 0 → 100644
View file @ 29b98259
`include "vme64x_bfm.svh"
`include "svec_vme_buffers.svh"
import wishbone_pkg::*;
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
wire clk_62m5;
wire rst_62m5_n;
reg clk_local = 0;
always #25ns clk_local <= ~clk_local;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
IVME64X VME(rst_n);
`DECLARE_VME_BUFFERS(VME.slave);
logic ddr_reset_n;
logic ddr_ck_p;
logic ddr_ck_n;
logic ddr_cke;
logic ddr_ras_n;
logic ddr_cas_n;
logic ddr_we_n;
wire [7:0] ddr_dm;
logic [2:0] ddr_ba;
logic [14:0] ddr_a;
wire [63:0] ddr_dq;
wire [7:0] ddr_dqs_p;
wire [7:0] ddr_dqs_n;
wire ddr_rzq;
logic ddr_odt;
logic [4:0] slot_id = 5'h8;
wire [7:0] afpga_dout, afpga_din;
wire afpga_fout, afpga_fin ;
reg [7:0] afpga_dout_delayed, afpga_din_delayed;
reg afpga_fout_delayed, afpga_fin_delayed ;
wire afpga_clk, afpga_rst_n;
always@(afpga_dout)
#1ns afpga_dout_delayed <= afpga_dout;
always@(afpga_din)
#1ns afpga_din_delayed <= afpga_din;
always@(afpga_fout)
#1ns afpga_fout_delayed <= afpga_fout;
always@(afpga_fin)
#1ns afpga_fin_delayed <= afpga_fin;
svec7_sfpga_top
#(
.g_SIMULATION(1'b1)
)
DUT (
.rst_n_i(rst_n),
.lclk_i (clk_local),
.afpga_clk_i(afpga_clk),
.afpga_rst_n_i(afpga_rst_n),
.afpga_d_i(afpga_dout_delayed),
.afpga_d_o(afpga_din ),
.afpga_frame_o(afpga_fin),
.afpga_frame_i(afpga_fout_delayed),
.vme_as_n_i (VME_AS_n),
.vme_sysreset_n_i (VME_RST_n),
.vme_write_n_i (VME_WRITE_n),
.vme_am_i (VME_AM),
.vme_ds_n_i (VME_DS_n),
.vme_gap_i (^slot_id),
.vme_ga_i (~slot_id),
.vme_berr_o (VME_BERR),
.vme_dtack_n_o (VME_DTACK_n),
.vme_retry_n_o (VME_RETRY_n),
.vme_retry_oe_o (VME_RETRY_OE),
.vme_lword_n_b (VME_LWORD_n),
.vme_addr_b (VME_ADDR),
.vme_data_b (VME_DATA),
.vme_irq_o (VME_IRQ_n),
.vme_iack_n_i (VME_IACK_n),
.vme_iackin_n_i (VME_IACKIN_n),
.vme_iackout_n_o (VME_IACKOUT_n),
.vme_dtack_oe_o (VME_DTACK_OE),
.vme_data_dir_o (VME_DATA_DIR),
.vme_data_oe_n_o (VME_DATA_OE_N),
.vme_addr_dir_o (VME_ADDR_DIR),
.vme_addr_oe_n_o (VME_ADDR_OE_N)
);
svec7_test_top
#(
.g_SIMULATION(1'b1)
)
DUT2(
.rst_n_i(rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (clk_local),
.clk_125m_gtp_n_i (clk_125m_pllref),
.clk_125m_gtp_p_i (~clk_125m_pllref),
.sfpga_clk_o(afpga_clk),
.sfpga_rst_n_o(afpga_rst_n),
.sfpga_d_i(afpga_din_delayed ),
.sfpga_d_o(afpga_dout),
.sfpga_frame_o(afpga_fout),
.sfpga_frame_i(afpga_fin_delayed ),
.vme_sysreset_n_i(VME_RST_n),
.fmc0_scl_b (),
.fmc0_sda_b (),
.fmc1_scl_b (),
.fmc1_sda_b (),
.fmc0_prsnt_m2c_n_i (),
.fmc1_prsnt_m2c_n_i (),
.onewire_b (),
.carrier_scl_b (),
.carrier_sda_b (),
// .spi_sclk_o (),
.spi_ncs_o (),
.spi_mosi_o (),
.spi_miso_i (),
.uart_rxd_i (),
.uart_txd_o (),
.pll20dac_din_o (),
.pll20dac_sclk_o (),
.pll20dac_sync_n_o (),
.pll25dac_din_o (),
.pll25dac_sclk_o (),
.pll25dac_sync_n_o (),
.sfp_txp_o (),
.sfp_txn_o (),
.sfp_rxp_i (),
.sfp_rxn_i (),
.sfp_mod_def0_i (),
.sfp_mod_def1_b (),
.sfp_mod_def2_b (),
.sfp_rate_select_o (),
.sfp_tx_fault_i (),
.sfp_tx_disable_o (),
.sfp_los_i (),
.pcbrev_i (5'h2)
);
task automatic init_vme64x_core(ref CBusAccessor_VME64x acc);
uint64_t rv;
/* map func0 to 0x80000000, A32 */
acc.write('h7ff63, 'h80, A32|CR_CSR|D08Byte3);
acc.write('h7ff67, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6b, 0, CR_CSR|A32|D08Byte3);
acc.write('h7ff6f, 36, CR_CSR|A32|D08Byte3);
acc.write('h7ff33, 1, CR_CSR|A32|D08Byte3);
acc.write('h7fffb, 'h10, CR_CSR|A32|D08Byte3); /* enable module (BIT_SET = 0x10) */
acc.read( 'h7ff63, rv, CR_CSR|A32|D08Byte3);
$display("Rv %x", rv );
acc.set_default_modifiers(A32 | D32 | SINGLE);
endtask // init_vme64x_core
initial begin
uint64_t d;
int i, result;
automatic CBusAccessor_VME64x acc = new(VME.tb);
// automatic CWishboneAccessor ddr4_acc = xwb_ddr4.get_accessor();
#5us;
init_vme64x_core(acc);
// Display meta data
d = 'hdeadbeef;
acc.write('h80000000, d, A32|SINGLE|D32);
d = 'hcafebabe;
acc.write('h80000004, d, A32|SINGLE|D32);
acc.read('h80000000, d, A32|SINGLE|D32);
$display("Rdbk[0] = %x", d);
acc.read('h80000004, d, A32|SINGLE|D32);
$display("Rdbk[4] = %x", d);
//$display("ddr status: %x", d);
end
endmodule // main
hdl/testbench/svec7_bridge/run.do 0 → 100644
View file @ 29b98259
vsim -quiet -L unisim work.main -novopt
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
do wave.do
run 10us
wave zoomfull
hdl/testbench/svec7_bridge/wave.do 0 → 100644
View file @ 29b98259
onerror {resume}
quietly WaveActivateNextPane {} 0
add wave -noupdate -group SFPGATop /main/DUT/lclk_i
add wave -noupdate -group SFPGATop /main/DUT/rst_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_write_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_sysreset_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_retry_oe_o
add wave -noupdate -group SFPGATop /main/DUT/vme_retry_n_o
add wave -noupdate -group SFPGATop /main/DUT/vme_lword_n_b
add wave -noupdate -group SFPGATop /main/DUT/vme_iackout_n_o
add wave -noupdate -group SFPGATop /main/DUT/vme_iackin_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_iack_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_gap_i
add wave -noupdate -group SFPGATop /main/DUT/vme_dtack_oe_o
add wave -noupdate -group SFPGATop /main/DUT/vme_dtack_n_o
add wave -noupdate -group SFPGATop /main/DUT/vme_ds_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_data_oe_n_o
add wave -noupdate -group SFPGATop /main/DUT/vme_data_dir_o
add wave -noupdate -group SFPGATop /main/DUT/vme_berr_o
add wave -noupdate -group SFPGATop /main/DUT/vme_as_n_i
add wave -noupdate -group SFPGATop /main/DUT/vme_addr_oe_n_o
add wave -noupdate -group SFPGATop /main/DUT/vme_addr_dir_o
add wave -noupdate -group SFPGATop /main/DUT/vme_irq_o
add wave -noupdate -group SFPGATop /main/DUT/vme_ga_i
add wave -noupdate -group SFPGATop /main/DUT/vme_data_b
add wave -noupdate -group SFPGATop /main/DUT/vme_am_i
add wave -noupdate -group SFPGATop /main/DUT/vme_addr_b
add wave -noupdate -group SFPGATop /main/DUT/vme_noga_i
add wave -noupdate -group SFPGATop /main/DUT/vme_use_ga_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_clk_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_rst_n_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_d_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_d_o
add wave -noupdate -group SFPGATop /main/DUT/afpga_frame_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_frame_o
add wave -noupdate -group SFPGATop /main/DUT/boot_clk_o
add wave -noupdate -group SFPGATop /main/DUT/boot_config_o
add wave -noupdate -group SFPGATop /main/DUT/boot_done_i
add wave -noupdate -group SFPGATop /main/DUT/boot_dout_o
add wave -noupdate -group SFPGATop /main/DUT/boot_status_i
add wave -noupdate -group SFPGATop /main/DUT/spi_cs_n_o
add wave -noupdate -group SFPGATop /main/DUT/spi_mosi_o
add wave -noupdate -group SFPGATop /main/DUT/spi_miso_i
add wave -noupdate -group SFPGATop /main/DUT/spi_sclk_o
add wave -noupdate -group SFPGATop /main/DUT/debugled_n_o
add wave -noupdate -group SFPGATop /main/DUT/afpga_flash_sck_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_flash_mosi_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_flash_cs_n_i
add wave -noupdate -group SFPGATop /main/DUT/afpga_flash_miso_o
add wave -noupdate -group SFPGATop /main/DUT/pll_ce_o
add wave -noupdate -group SFPGATop /main/DUT/wb_vme_in
add wave -noupdate -group SFPGATop /main/DUT/wb_vme_out
add wave -noupdate -group SFPGATop /main/DUT/passive
add wave -noupdate -group SFPGATop /main/DUT/boot_en
add wave -noupdate -group SFPGATop /main/DUT/boot_trig_p1
add wave -noupdate -group SFPGATop /main/DUT/boot_exit_p1
add wave -noupdate -group SFPGATop /main/DUT/CONTROL
add wave -noupdate -group SFPGATop /main/DUT/CLK
add wave -noupdate -group SFPGATop /main/DUT/TRIG0
add wave -noupdate -group SFPGATop /main/DUT/TRIG1
add wave -noupdate -group SFPGATop /main/DUT/TRIG2
add wave -noupdate -group SFPGATop /main/DUT/TRIG3
add wave -noupdate -group SFPGATop /main/DUT/boot_config_int
add wave -noupdate -group SFPGATop /main/DUT/erase_afpga_n
add wave -noupdate -group SFPGATop /main/DUT/erase_afpga_n_d0
add wave -noupdate -group SFPGATop /main/DUT/pllout_clk_fb_sys
add wave -noupdate -group SFPGATop /main/DUT/pllout_clk_sys
add wave -noupdate -group SFPGATop /main/DUT/clk_sys
add wave -noupdate -group SFPGATop /main/DUT/rst_n_sys
add wave -noupdate -group SFPGATop /main/DUT/go_passive
add wave -noupdate -group SFPGATop /main/DUT/vme_idle
add wave -noupdate -group SFPGATop /main/DUT/pll_reset_count
add wave -noupdate -group SFPGATop /main/DUT/spi_cs_n_int
add wave -noupdate -group SFPGATop /main/DUT/spi_mosi_int
add wave -noupdate -group SFPGATop /main/DUT/spi_sclk_int
add wave -noupdate -group SFPGATop /main/DUT/pass_flash
add wave -noupdate -group SFPGATop -expand /main/DUT/vme_in
add wave -noupdate -group SFPGATop /main/DUT/vme_out_boot
add wave -noupdate -group SFPGATop /main/DUT/vme_out_bridge
add wave -noupdate -group SFPGATop /main/DUT/vme_data_b_out
add wave -noupdate -group SFPGATop /main/DUT/vme_addr_b_out
add wave -noupdate -group SFPGATop /main/DUT/vme_lword_n_b_out
add wave -noupdate -group SFPGATop /main/DUT/vme_data_dir_int
add wave -noupdate -group SFPGATop /main/DUT/vme_addr_dir_int
add wave -noupdate -group SFPGATop /main/DUT/vme_ga
add wave -noupdate -group SFPGATop /main/DUT/vme_berr_n
add wave -noupdate -group SFPGATop /main/DUT/vme_irq_n
add wave -noupdate -group SFPGATop /main/DUT/addr_decoder_in
add wave -noupdate -group SFPGATop /main/DUT/addr_decoder_out
add wave -noupdate -group SFPGATop /main/DUT/decode_start
add wave -noupdate -group SFPGATop /main/DUT/decode_done
add wave -noupdate -group SFPGATop /main/DUT/r_am
add wave -noupdate -group SFPGATop /main/DUT/decode_sel
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_addr
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_data_in
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_data_out
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_we
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_req
add wave -noupdate -group SFPGATop /main/DUT/cr_csr_done
add wave -noupdate -group SFPGATop /main/DUT/r_module_enable
add wave -noupdate -group SFPGATop /main/DUT/r_bar
add wave -noupdate -group SFPGATop /main/DUT/r_int_level
add wave -noupdate -group SFPGATop /main/DUT/r_int_vector
add wave -noupdate -group SFPGATop /main/DUT/r_irq_pending
add wave -noupdate -group SFPGATop /main/DUT/r_irq_ack
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/clk_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/rst_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_as_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_lword_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_lword_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_retry_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_retry_oe_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_write_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_ds_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_dtack_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_dtack_oe_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_berr_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_addr_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_addr_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_addr_dir_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_addr_oe_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_data_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_data_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_data_dir_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_data_oe_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_am_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_iackin_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_iack_n_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/vme_iackout_n_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_req_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_is_blt_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_ack_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_err_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_we_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_addr_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_data_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_data_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/mem_sel_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/addr_decoder_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/addr_decoder_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/decode_start_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/decode_done_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/am_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/decode_sel_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_addr_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_data_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_data_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_we_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_req_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/cr_csr_done_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/module_enable_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/bar_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/int_level_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/int_vector_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/irq_pending_i
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/irq_ack_o
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_locDataIn
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_locDataOut
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_ADDRlatched
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_LWORDlatched_n
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_DSlatched_n
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_AMlatched
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_WRITElatched_n
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_vme_addr_reg
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_vme_data_reg
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_vme_lword_n_reg
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_vme_addr_dir
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_addressingType
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_transferType
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_mainFSMstate
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_conf_req
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_dataPhase
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_MBLT_Data
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_conf_sel
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_card_sel
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_irq_sel
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_err
add wave -noupdate -group SFPGABus /main/DUT/xvme64x_core_master_1/inst_vme_bus/s_DS_latch_count
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/vme_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/vme_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_clk_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_rst_n_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_d_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_frame_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_d_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/afpga_frame_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_reset_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_irq_n_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_irq_ack
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_irq_pending
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_ga
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_ga_parity
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_cr_csr_addr
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_cr_csr_data_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_cr_csr_data_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_cr_csr_we
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_module_reset
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_module_enable
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_bar
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_berr_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_irq_vector
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_irq_level
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_user_csr_addr
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_user_csr_data_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_user_csr_data_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_user_csr_we
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_addr_decoder_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_addr_decoder_o
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_decode_start
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_decode_done
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_decode_sel
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_am
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_rst_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_as_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_write_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_ds_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_iack_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/s_vme_iackin_n
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_req
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_is_blt
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_we
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_ack
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_err
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_addr
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_data_out
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_data_in
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/mem_sel
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/cr_csr_req
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/cr_csr_done
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/rst_n_i
add wave -noupdate -group SfpgaMaster /main/DUT/xvme64x_core_master_1/clk_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_rst_n_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_clk_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_d_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_frame_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_d_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_frame_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_req_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_is_blt_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_ack_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_err_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_we_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_addr_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_data_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_data_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/mem_sel_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/addr_decoder_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/addr_decoder_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/decode_start_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/decode_done_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/am_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/decode_sel_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_addr_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_data_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_data_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_we_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_req_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/cr_csr_done_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/module_enable_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/bar_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/int_level_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/int_vector_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/irq_pending_o
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/irq_ack_i
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_dout
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_din
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_frame_out
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_frame_in
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/afpga_clk_n
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/tx_state
add wave -noupdate -group SfpgaBridge /main/DUT/xvme64x_core_master_1/bridge_master_1/rx_state
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_rst_n_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_clk_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_d_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_frame_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_d_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_din
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_frame_in
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_clk_n
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_frame_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/vme_berr_n_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/vme_ga_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_req_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_is_blt_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_ack_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_err_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_we_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_addr_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_data_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_data_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/mem_sel_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/addr_decoder_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/addr_decoder_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/decode_start_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/decode_done_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/am_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/decode_sel_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_addr_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_data_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_data_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_we_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_req_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/cr_csr_done_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/module_enable_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/bar_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/int_level_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/int_vector_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/irq_pending_i
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/irq_ack_o
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_dout
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/sfpga_frame_out
add wave -noupdate -group AfpgaBridge /main/DUT2/inst_svec_base/cmp_vme_core/bridge_slave_1/rx_state
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/clk_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/rst_n_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/vme_aux_valid_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/vme_ga_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/vme_berr_n_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/bar_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/module_enable_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/module_reset_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/addr_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/data_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/data_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/we_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_csr_addr_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_csr_data_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_csr_data_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_csr_we_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_cr_addr_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/user_cr_data_i
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/ader_o
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_addr
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_reg_bar
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_reg_bit_reg
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_reg_cram_owner
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_reg_usr_bit_reg
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_reg_ader
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cr_access
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_csr_access
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram_access
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_user_cr_access
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_user_csr_access
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cr_data
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_csr_data
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram_data
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram_waddr
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram_raddr
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_cram_we
add wave -noupdate -group AfpgaCrCSR /main/DUT2/inst_svec_base/cmp_vme_core/gen_enable_cr_csr/inst_vme_cr_csr_space/s_vme_aux_valid_d
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/clk_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/rst_n_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/addr_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/addr_o
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/decode_start_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/am_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/ader_i
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/decode_sel_o
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/decode_done_o
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/s_function_sel
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/s_function_sel_valid
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/s_decode_start_1
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/s_function
add wave -noupdate -group FunctMatch /main/DUT2/inst_svec_base/cmp_vme_core/inst_vme_funct_match/s_ader_am_valid
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/clk_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/rst_n_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/rst_n_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/wb_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/wb_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_clk_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_rst_n_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_frame_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_d_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_frame_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/bridge_d_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/int_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/irq_ack_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/irq_level_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/irq_vector_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_csr_addr_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_csr_data_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_csr_data_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_csr_we_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_cr_addr_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/user_cr_data_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_reset_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_irq_n_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_irq_ack
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_irq_pending
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_ga
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_addr
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_data_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_data_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_we
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_module_reset
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_module_enable
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_bar
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_berr_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_irq_vector
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_irq_level
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_user_csr_addr
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_user_csr_data_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_user_csr_data_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_user_csr_we
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_addr_decoder_i
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_addr_decoder_o
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_decode_start
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_decode_done
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_decode_sel
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_am
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_rst_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_as_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_write_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_ds_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_iack_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_iackin_n
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_vme_aux_valid
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_req
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_is_blt
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_we
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_ack
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_err
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_addr
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_data_out
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_data_in
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/mem_sel
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_req
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_cr_csr_done
add wave -noupdate -expand -group AFPGASlave /main/DUT2/inst_svec_base/cmp_vme_core/s_ader
TreeUpdate [SetDefaultTree]
WaveRestoreCursors {{Cursor 1} {1166667 ps} 0}
configure wave -namecolwidth 241
configure wave -valuecolwidth 100
configure wave -justifyvalue left
configure wave -signalnamewidth 1
configure wave -snapdistance 10
configure wave -datasetprefix 0
configure wave -rowmargin 4
configure wave -childrowmargin 2
configure wave -gridoffset 0
configure wave -gridperiod 1
configure wave -griddelta 40
configure wave -timeline 0
configure wave -timelineunits ns
update
WaveRestoreZoom {0 ps} {10500 ns}
hdl/testbench/svec7_test_top/Manifest.py
View file @ 29b98259
......@@ -6,33 +6,34 @@ vcom_opt = "-93 -mixedsvvh"
syn_device = "xc7k325t"
svec_template_ucf = []
board = "svec7"
board = "svec7a"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
include_dirs=[ "../../../../vme64x-core/hdl/sim/vme64x_bfm",
"../../../../general-cores/sim",
"../../../../general-cores/modules/wishbone/wb_spi",
"../../../../general-cores/modules/wishbone/wb_lm32/src",
include_dirs=[ "../../ip_cores/vme64x-core/hdl/sim/vme64x_bfm",
"../../ip_cores/general-cores/sim",
"../../ip_cores/general-cores/modules/wishbone/wb_spi",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/src",
"../../ip_cores/general-cores/modules/wishbone/wb_lm32/platform/spartan6",
"." ]
files = [ "main.sv", "buildinfo_pkg.vhd" ]
modules = {
"local" : [ "../../rtl/svec7",
"local" : [ "../../rtl/svec7a",
"../../top/svec7_test",
"../../../../wr-cores",
"../../../../general-cores",
"../../../../vme64x-core"
"../../ip_cores/wr-cores",
"../../ip_cores/general-cores",
"../../ip_cores/vme64x-core"
],
}
# Do not fail during hdlmake fetch
try:
exec(open("../../../../general-cores/tools/gen_buildinfo.py").read())
exec(open("../../ip_cores/general-cores/tools/gen_buildinfo.py").read())
except:
pass
hdl/testbench/svec7_test_top/main.sv
View file @ 29b98259
......@@ -46,12 +46,12 @@ module main;
DUT (
.rst_n_i(rst_n),
.clk_62m5_pllref_p_i (clk_125m_pllref),
.clk_62m5_pllref_n_i (~clk_125m_pllref),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.clk_20m_vcxo_i (1'b0),
.clk_125m_gtx_n_i (1'b0),
.clk_125m_gtx_p_i (1'b1),
.clk_125m_gtp_n_i (1'b0),
.clk_125m_gtp_p_i (1'b1),
.vme_as_n_i (VME_AS_n),
......
hdl/top/sfpga_bootloader/svec_sfpga_bridge.vhd 0 → 100644
View file @ 29b98259
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.vme64x_pkg.all;
entity svec_sfpga_bridge is
generic(
g_clock_period : integer
);
port (
afpga_rst_n_i : in STD_LOGIC;
afpga_clk_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
afpga_d_o : in std_logic_vector(7 downto 0);
afpga_frame_o : in std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out
);
end svec_sfpga_bridge;
architecture rtl of svec_sfpga_bridge is
constant c_tag_addr : std_logic_vector(7 downto 0) := x"a0";
constant c_tag_ds_req : std_logic_vector(7 downto 0) := x"a1";
signal as_fedge_p : std_logic;
signal ds_synced: std_logic_vector(1 downto 0);
signal ADDR_latched : std_logic_vector(31 downto 1);
signal LWORD_latched_n : std_logic;
signal AM_latched : std_logic_vector(5 downto 0);
signal WRITE_latched : std_logic;
signal addr_req : std_logic;
signal ds_req : std_logic;
signal wdata_req : std_logic;
signal ds_count : unsigned(2 downto 0);
-- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
-- (max skew for the slave is 20 ns)
constant c_num_latchDS : natural range 1 to 8 :=
(20 + g_CLOCK_PERIOD - 1) / g_CLOCK_PERIOD;
begin
U_Sync1 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.as_n,
npulse_o => as_fedge_p);
U_Sync2 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(0),
synced_o => ds_synced(0));
U_Sync3 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(1),
synced_o => ds_synced(1));
p_latch_addr: process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if as_fedge_p = '1' then
ADDR_latched <= vme_i.Addr;
LWORD_latched_n <= vme_i.LWORD_n;
AM_latched <= vme_i.am;
addr_req <= '1';
end if;
end if;
end process;
p_latch_data: process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if ds_synced /= "00" then
WRITE_latched <= vme_i.WRITE_n;
end if;
end if;
end process;
end rtl;
hdl/top/sfpga_bootloader/svec_sfpga_top.vhd
View file @ 29b98259
......@@ -113,6 +113,12 @@ entity svec_sfpga_top is
afpga_flash_cs_n_i : in std_logic;
afpga_flash_miso_o : out std_logic;
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
-- Onboard PLL enable signal. Must be one for the clock system to work.
pll_ce_o : out std_logic
......
hdl/top/svec7_sfpga/Manifest.py 0 → 100644
View file @ 29b98259
files = [ "svec7_sfpga_top.vhd", "svec7_sfpga_top.ucf", "reset_gen.vhd", "svec7_sfpga_bridge.vhd" ]
fetchto = "../../ip_cores"
modules = {
"local" : ["../../rtl/bootloader" ],
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git" ]
}
hdl/top/svec7_sfpga/reset_gen.vhd 0 → 100644
View file @ 29b98259
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
entity reset_gen is
port (
clk_sys_i : in std_logic;
rst_vme_n_a_i : in std_logic;
rst_local_n_a_i : in std_logic;
rst_n_o : out std_logic
);
end reset_gen;
architecture behavioral of reset_gen is
signal powerup_cnt : unsigned(7 downto 0) := x"00";
signal local_synced_n : std_logic;
signal vme_synced_n : std_logic;
signal powerup_n : std_logic := '0';
begin -- behavioral
U_EdgeDet_PCIe : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_vme_n_a_i,
synced_o => vme_synced_n);
U_Sync_Button : gc_sync_ffs port map (
clk_i => clk_sys_i,
rst_n_i => '1',
data_i => rst_local_n_a_i,
synced_o => local_synced_n);
p_powerup_reset : process(clk_sys_i)
begin
if rising_edge(clk_sys_i) then
if(powerup_cnt /= x"ff") then
powerup_cnt <= powerup_cnt + 1;
powerup_n <= '0';
else
powerup_n <= '1';
end if;
end if;
end process;
rst_n_o <= powerup_n and local_synced_n and vme_synced_n;
end behavioral;
hdl/top/svec7_sfpga/svec7_sfpga_bridge.vhd 0 → 100644
View file @ 29b98259
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec7_sfpga_bridge is
generic(
g_clock_period : integer
);
port (
afpga_rst_n_i : in std_logic;
afpga_clk_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out
);
end svec7_sfpga_bridge;
architecture rtl of svec7_sfpga_bridge is
constant c_tag_addr : std_logic_vector(7 downto 0) := x"a0";
constant c_tag_read : std_logic_vector(7 downto 0) := x"a1";
constant c_tag_write : std_logic_vector(7 downto 0) := x"a2";
constant c_tag_read_cpl : std_logic_vector(7 downto 0) := x"a3";
constant c_tag_irq : std_logic_vector(7 downto 0) := x"a4";
constant c_tag_iackin : std_logic_vector(7 downto 0) := x"a5";
constant c_tag_iackout : std_logic_vector(7 downto 0) := x"a6";
constant c_tag_aux : std_logic_vector(7 downto 0) := x"a7";
constant c_tag_release : std_logic_vector(7 downto 0) := x"a8";
signal as_fedge_p : std_logic;
signal as_redge_p : std_logic;
signal ds_fedge_p : std_logic_vector(1 downto 0);
signal ds_synced : std_logic_vector(1 downto 0);
signal ADDR_latched : std_logic_vector(31 downto 1);
signal LWORD_latched_n : std_logic;
signal AM_latched : std_logic_vector(5 downto 0);
signal WRITE_latched : std_logic;
signal data_latched : std_logic_vector(63 downto 0);
signal ds_latched : std_logic_vector(1 downto 0);
signal release_req : std_logic;
signal release_ack : std_logic;
signal addr_req, addr_ack : std_logic;
signal write_req, write_ack : std_logic;
signal read_req, read_ack : std_logic;
signal rdata_req, rdata_ack : std_logic;
signal rx_dtack, rx_berr : std_logic;
signal as_n_synced : std_logic;
signal ds_count : unsigned(2 downto 0);
-- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
-- (max skew for the slave is 20 ns)
constant c_num_latchDS : natural range 1 to 8 :=
(20 + g_CLOCK_PERIOD - 1) / g_CLOCK_PERIOD;
signal afpga_dout : std_logic_vector(15 downto 0);
signal afpga_din : std_logic_vector(15 downto 0);
signal afpga_frame_out : std_logic;
signal afpga_frame_in : std_logic_vector(1 downto 0);
signal afpga_clk_n : std_logic;
type t_ds_fsm_state is
(
IDLE,
REQ_READ,
REQ_WRITE,
REQ_WRITE_ACK);
type t_bridge_tx_state is
(IDLE,
TX_ADDR0,
TX_ADDR1,
TX_WRITE0,
TX_WRITE1,
TX_WRITE2,
TX_WRITE3);
type t_bridge_rx_state is
(
IDLE,
RX_DATA0,
RX_DATA1,
RX_DATA2,
RX_DATA3,
GEN_DTACK);
signal ds_state : t_ds_fsm_state;
signal tx_state : t_bridge_tx_state;
signal rx_state : t_bridge_rx_state;
begin
afpga_clk_n <= not afpga_clk_i;
gen_ddr_ios : for i in 0 to 7 generate
U_ODDR_Data : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_d_o(i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_dout(2*i),
D1 => afpga_dout(2*i+1),
R => '0',
S => '0');
U_IDDR_Data : IDDR2
generic map (
DDR_ALIGNMENT => "C0" )
port map (
Q0 => afpga_din(2*i),
Q1 => afpga_din(2*i+1),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_d_i(i),
R => '0',
S => '0');
end generate gen_ddr_ios;
U_IDDR_Frame : IDDR2
generic map (
DDR_ALIGNMENT => "C0" )
port map (
Q0 => afpga_frame_in(0),
Q1 => afpga_frame_in(1),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_frame_i,
R => '0',
S => '0');
U_ODDR_Frame : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_frame_o,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_frame_out,
D1 => afpga_frame_out,
R => '0',
S => '0');
U_Sync1 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.as_n,
synced_o => as_n_synced,
npulse_o => as_fedge_p);
U_Sync2 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(0),
synced_o => ds_synced(0),
npulse_o => ds_fedge_p(0));
U_Sync3 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(1),
synced_o => ds_synced(1),
npulse_o => ds_fedge_p(1));
p_latch_addr : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
addr_req <= '0';
release_req <= '0';
elsif as_redge_p = '1' then
release_req <= '1';
elsif as_fedge_p = '1' then
ADDR_latched <= vme_i.Addr;
LWORD_latched_n <= vme_i.LWORD_n;
AM_latched <= vme_i.am;
addr_req <= '1';
elsif addr_ack = '1' then
addr_req <= '0';
end if;
end if;
end process;
p_latch_data : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
read_req <= '0';
write_req <= '0';
ds_state <= IDLE;
else
case ds_state is
when IDLE =>
read_req <= '0';
write_req <= '0';
if ds_fedge_p /= "00" and as_n_synced = '0' then
if vme_i.write_n = '0' then
ds_state <= REQ_WRITE;
ds_count <= (others => '0');
else
ds_state <= REQ_READ;
read_req <= '1';
end if;
end if;
when REQ_READ =>
if read_ack = '1' or ds_synced = "11" then
ds_state <= IDLE;
read_req <= '0';
end if;
when REQ_WRITE =>
ds_count <= ds_count + 1;
if ds_synced = "11" then
ds_state <= IDLE;
elsif ds_count = c_num_latchDS then
write_req <= '1';
ds_latched <= vme_i.ds_n;
data_latched(63 downto 33) <= vme_i.addr;
data_latched(32) <= vme_i.LWORD_n;
data_latched(31 downto 0) <= vme_i.data;
ds_state <= REQ_WRITE_ACK;
end if;
when REQ_WRITE_ACK =>
if write_ack = '1' then
write_req <= '0';
ds_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
p_in_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
rx_state <= IDLE;
case rx_state is
when IDLE =>
if afpga_frame_i = '1' then
case afpga_din(15 downto 8) is
when c_tag_read_cpl =>
rx_dtack <= afpga_din(0);
rx_berr <= afpga_din(1);
rx_state <= RX_DATA0;
when c_tag_iackin => null;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
p_out_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
tx_state <= IDLE;
afpga_dout <= (others => '0');
afpga_frame_out <= '0';
addr_ack <= '0';
else
case tx_state is
when IDLE =>
write_ack <= '0';
read_ack <= '0';
addr_ack <= '0';
afpga_frame_out <= '0';
afpga_dout <= (others => '0');
if addr_req = '1' then
afpga_dout(15 downto 8) <= c_tag_addr;
afpga_dout(7 downto 2) <= AM_latched;
afpga_dout(1) <= '0';
afpga_dout(0) <= LWORD_latched_n;
afpga_frame_out <= '1';
tx_state <= TX_ADDR0;
elsif read_req = '1' and read_ack = '0' then
afpga_dout(15 downto 8) <= c_tag_read;
afpga_dout(1 downto 0) <= ds_latched;
afpga_frame_out <= '1';
read_ack <= '1';
tx_state <= IDLE;
elsif write_req = '1' and write_ack = '0' then
afpga_dout(15 downto 8) <= c_tag_write;
afpga_dout(1 downto 0) <= ds_latched;
afpga_frame_out <= '1';
tx_state <= TX_WRITE0;
else
afpga_frame_out <= '1';
afpga_dout(15 downto 8) <= c_tag_aux;
afpga_dout(5 downto 0) <= vme_i.ga;
afpga_dout(6) <= vme_i.iack_n;
afpga_dout(7) <= vme_i.iackin_n;
tx_state <= IDLE;
end if;
when TX_WRITE0 =>
afpga_dout <= data_latched(63 downto 48);
afpga_frame_out <= '0';
tx_state <= TX_WRITE1;
when TX_WRITE1 =>
afpga_dout <= data_latched(47 downto 32);
afpga_frame_out <= '0';
tx_state <= TX_WRITE2;
when TX_WRITE2 =>
afpga_dout <= data_latched(31 downto 16);
afpga_frame_out <= '0';
tx_state <= TX_WRITE3;
when TX_WRITE3 =>
afpga_dout <= data_latched(15 downto 0);
write_ack <= '1';
tx_state <= IDLE;
when TX_ADDR0 =>
afpga_dout <= ADDR_latched(31 downto 16);
afpga_frame_out <= '0';
tx_state <= TX_ADDR1;
addr_ack <= '1';
when TX_ADDR1 =>
afpga_dout <= ADDR_latched(15 downto 1) & '0';
afpga_frame_out <= '0';
addr_ack <= '0';
tx_state <= IDLE;
end case;
end if;
end if;
end process;
vme_o.dtack_n <= '1';
vme_o.berr_n <= '1';
vme_o.dtack_oe <= '1';
vme_o.data_dir <= '0';
vme_o.addr_dir <= '0';
vme_o.addr_oe_n <= '0';
vme_o.data_oe_n <= '0';
end rtl;
hdl/top/svec7_sfpga/svec7_sfpga_bridge2.vhd 0 → 100644
View file @ 29b98259
library ieee;
use ieee.STD_LOGIC_1164.all;
use ieee.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity svec7_sfpga_bridge is
generic(
g_clock_period : integer
);
port (
afpga_rst_n_i : in std_logic;
afpga_clk_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_o : out std_logic;
vme_i : in t_vme64x_in;
vme_o : out t_vme64x_out
);
end svec7_sfpga_bridge;
architecture rtl of svec7_sfpga_bridge is
constant c_tag_addr : std_logic_vector(7 downto 0) := x"a0";
constant c_tag_read : std_logic_vector(7 downto 0) := x"a1";
constant c_tag_write : std_logic_vector(7 downto 0) := x"a2";
constant c_tag_read_cpl : std_logic_vector(7 downto 0) := x"a3";
constant c_tag_irq : std_logic_vector(7 downto 0) := x"a4";
constant c_tag_iackin : std_logic_vector(7 downto 0) := x"a5";
constant c_tag_iackout : std_logic_vector(7 downto 0) := x"a6";
constant c_tag_aux : std_logic_vector(7 downto 0) := x"a7";
constant c_tag_release : std_logic_vector(7 downto 0) := x"a8";
signal as_fedge_p : std_logic;
signal as_redge_p : std_logic;
signal ds_fedge_p : std_logic_vector(1 downto 0);
signal ds_synced : std_logic_vector(1 downto 0);
signal ADDR_latched : std_logic_vector(31 downto 1);
signal LWORD_latched_n : std_logic;
signal AM_latched : std_logic_vector(5 downto 0);
signal WRITE_latched : std_logic;
signal data_latched : std_logic_vector(63 downto 0);
signal ds_latched : std_logic_vector(1 downto 0);
signal release_req : std_logic;
signal release_ack : std_logic;
signal addr_req, addr_ack : std_logic;
signal write_req, write_ack : std_logic;
signal read_req, read_ack : std_logic;
signal rdata_req, rdata_ack : std_logic;
signal rx_dtack, rx_berr : std_logic;
signal as_n_synced : std_logic;
signal ds_count : unsigned(2 downto 0);
-- Calculate the number of LATCH DS states necessary to match the timing
-- rule 2.39 page 113 VMEbus specification ANSI/IEEE STD1014-1987.
-- (max skew for the slave is 20 ns)
constant c_num_latchDS : natural range 1 to 8 :=
(20 + g_CLOCK_PERIOD - 1) / g_CLOCK_PERIOD;
signal afpga_dout : std_logic_vector(15 downto 0);
signal afpga_din : std_logic_vector(15 downto 0);
signal afpga_frame_out : std_logic;
signal afpga_frame_in : std_logic_vector(1 downto 0);
signal afpga_clk_n : std_logic;
type t_ds_fsm_state is
(
IDLE,
REQ_READ,
REQ_WRITE,
REQ_WRITE_ACK);
type t_bridge_tx_state is
(IDLE,
TX_ADDR0,
TX_ADDR1,
TX_WRITE0,
TX_WRITE1,
TX_WRITE2,
TX_WRITE3);
type t_bridge_rx_state is
(
IDLE,
RX_DATA0,
RX_DATA1,
RX_DATA2,
RX_DATA3,
GEN_DTACK);
signal ds_state : t_ds_fsm_state;
signal tx_state : t_bridge_tx_state;
signal rx_state : t_bridge_rx_state;
begin
afpga_clk_n <= not afpga_clk_i;
gen_ddr_ios : for i in 0 to 7 generate
U_ODDR_Data : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_d_o(i),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_dout(2*i),
D1 => afpga_dout(2*i+1),
R => '0',
S => '0');
U_IDDR_Data : IDDR2
generic map (
DDR_ALIGNMENT => "C0" )
port map (
Q0 => afpga_din(2*i),
Q1 => afpga_din(2*i+1),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_d_i(i),
R => '0',
S => '0');
end generate gen_ddr_ios;
U_IDDR_Frame : IDDR2
generic map (
DDR_ALIGNMENT => "C0" )
port map (
Q0 => afpga_frame_in(0),
Q1 => afpga_frame_in(1),
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D => afpga_frame_i,
R => '0',
S => '0');
U_ODDR_Frame : ODDR2
generic map (
DDR_ALIGNMENT => "C0")
port map (
Q => afpga_frame_o,
C0 => afpga_clk_i,
C1 => afpga_clk_n,
CE => '1',
D0 => afpga_frame_out,
D1 => afpga_frame_out,
R => '0',
S => '0');
U_Sync1 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.as_n,
synced_o => as_n_synced,
npulse_o => as_fedge_p);
U_Sync2 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(0),
synced_o => ds_synced(0),
npulse_o => ds_fedge_p(0));
U_Sync3 : gc_sync_ffs
port map (
clk_i => afpga_clk_i,
rst_n_i => afpga_rst_n_i,
data_i => vme_i.ds_n(1),
synced_o => ds_synced(1),
npulse_o => ds_fedge_p(1));
p_latch_addr : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
addr_req <= '0';
release_req <= '0';
elsif as_redge_p = '1' then
release_req <= '1';
elsif as_fedge_p = '1' then
ADDR_latched <= vme_i.Addr;
LWORD_latched_n <= vme_i.LWORD_n;
AM_latched <= vme_i.am;
addr_req <= '1';
elsif addr_ack = '1' then
addr_req <= '0';
end if;
end if;
end process;
p_latch_data : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
read_req <= '0';
write_req <= '0';
ds_state <= IDLE;
else
case ds_state is
when IDLE =>
read_req <= '0';
write_req <= '0';
if ds_fedge_p /= "00" and as_n_synced = '0' then
if vme_i.write_n = '0' then
ds_state <= REQ_WRITE;
ds_count <= (others => '0');
else
ds_state <= REQ_READ;
read_req <= '1';
end if;
end if;
when REQ_READ =>
if read_ack = '1' or ds_synced = "11" then
ds_state <= IDLE;
read_req <= '0';
end if;
when REQ_WRITE =>
ds_count <= ds_count + 1;
if ds_synced = "11" then
ds_state <= IDLE;
elsif ds_count = c_num_latchDS then
write_req <= '1';
ds_latched <= vme_i.ds_n;
data_latched(63 downto 33) <= vme_i.addr;
data_latched(32) <= vme_i.LWORD_n;
data_latched(31 downto 0) <= vme_i.data;
ds_state <= REQ_WRITE_ACK;
end if;
when REQ_WRITE_ACK =>
if write_ack = '1' then
write_req <= '0';
ds_state <= IDLE;
end if;
end case;
end if;
end if;
end process;
p_in_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
rx_state <= IDLE;
case rx_state is
when IDLE =>
if afpga_frame_i = '1' then
case afpga_din(15 downto 8) is
when c_tag_read_cpl =>
rx_dtack <= afpga_din(0);
rx_berr <= afpga_din(1);
rx_state <= RX_DATA0;
when c_tag_iackin => null;
when others => null;
end case;
end if;
when others => null;
end case;
end if;
end if;
end process;
p_out_fsm : process(afpga_clk_i)
begin
if rising_edge(afpga_clk_i) then
if afpga_rst_n_i = '0' then
tx_state <= IDLE;
afpga_dout <= (others => '0');
afpga_frame_out <= '0';
addr_ack <= '0';
else
case tx_state is
when IDLE =>
write_ack <= '0';
read_ack <= '0';
addr_ack <= '0';
afpga_frame_out <= '0';
afpga_dout <= (others => '0');
if addr_req = '1' then
afpga_dout(15 downto 8) <= c_tag_addr;
afpga_dout(7 downto 2) <= AM_latched;
afpga_dout(1) <= '0';
afpga_dout(0) <= LWORD_latched_n;
afpga_frame_out <= '1';
tx_state <= TX_ADDR0;
elsif read_req = '1' and read_ack = '0' then
afpga_dout(15 downto 8) <= c_tag_read;
afpga_dout(1 downto 0) <= ds_latched;
afpga_frame_out <= '1';
read_ack <= '1';
tx_state <= IDLE;
elsif write_req = '1' and write_ack = '0' then
afpga_dout(15 downto 8) <= c_tag_write;
afpga_dout(1 downto 0) <= ds_latched;
afpga_frame_out <= '1';
tx_state <= TX_WRITE0;
else
afpga_frame_out <= '1';
afpga_dout(15 downto 8) <= c_tag_aux;
afpga_dout(5 downto 0) <= vme_i.ga;
afpga_dout(6) <= vme_i.iack_n;
afpga_dout(7) <= vme_i.iackin_n;
tx_state <= IDLE;
end if;
when TX_WRITE0 =>
afpga_dout <= data_latched(63 downto 48);
afpga_frame_out <= '0';
tx_state <= TX_WRITE1;
when TX_WRITE1 =>
afpga_dout <= data_latched(47 downto 32);
afpga_frame_out <= '0';
tx_state <= TX_WRITE2;
when TX_WRITE2 =>
afpga_dout <= data_latched(31 downto 16);
afpga_frame_out <= '0';
tx_state <= TX_WRITE3;
when TX_WRITE3 =>
afpga_dout <= data_latched(15 downto 0);
write_ack <= '1';
tx_state <= IDLE;
when TX_ADDR0 =>
afpga_dout <= ADDR_latched(31 downto 16);
afpga_frame_out <= '0';
tx_state <= TX_ADDR1;
addr_ack <= '1';
when TX_ADDR1 =>
afpga_dout <= ADDR_latched(15 downto 1) & '0';
afpga_frame_out <= '0';
addr_ack <= '0';
tx_state <= IDLE;
end case;
end if;
end if;
end process;
vme_o.dtack_n <= '1';
vme_o.berr_n <= '1';
vme_o.dtack_oe <= '1';
vme_o.data_dir <= '0';
vme_o.addr_dir <= '0';
vme_o.addr_oe_n <= '0';
vme_o.data_oe_n <= '0';
end rtl;
hdl/top/svec7_sfpga/svec7_sfpga_top.ucf 0 → 100644
View file @ 29b98259
#===============================================================================
# IO Location Constraints
#===============================================================================
#----------------------------------------
# VME interface
#----------------------------------------
NET "vme_write_n_i" LOC = B1;
NET "vme_rst_n_i" LOC = G6;
#NET "vme_retry_oe_o" LOC = D3;
#NET "vme_retry_n_o" LOC = D1;
NET "vme_lword_n_b" LOC = B3;
#NET "vme_iackout_n_o" LOC = E4;
#NET "vme_iackin_n_i" LOC = F6;
#NET "vme_iack_n_i" LOC = E3;
NET "vme_dtack_oe_o" LOC = C3;
NET "vme_dtack_n_o" LOC = C2;
NET "vme_ds_n_i[1]" LOC = N9;
NET "vme_ds_n_i[0]" LOC = P9;
NET "vme_data_oe_n_o" LOC = K6;
NET "vme_data_dir_o" LOC = F4;
#NET "vme_berr_o" LOC = C1;
NET "vme_as_n_i" LOC = F5;
NET "vme_addr_oe_n_o" LOC = K5;
NET "vme_addr_dir_o" LOC = B2;
#NET "vme_irq_n_o[6]" LOC = C11;
#NET "vme_irq_n_o[5]" LOC = C8;
#NET "vme_irq_n_o[4]" LOC = D8;
#NET "vme_irq_n_o[3]" LOC = C10;
#NET "vme_irq_n_o[2]" LOC = E10;
#NET "vme_irq_n_o[1]" LOC = E8;
#NET "vme_irq_n_o[0]" LOC = E7;
NET "vme_ga_i[5]" LOC = A3;
NET "vme_ga_i[4]" LOC = A10;
NET "vme_ga_i[3]" LOC = B10;
NET "vme_ga_i[2]" LOC = A9;
NET "vme_ga_i[1]" LOC = C9;
NET "vme_ga_i[0]" LOC = A8;
NET "vme_data_b[31]" LOC = F7;
NET "vme_data_b[30]" LOC = A6;
NET "vme_data_b[29]" LOC = B6;
NET "vme_data_b[28]" LOC = C5;
NET "vme_data_b[27]" LOC = D5;
NET "vme_data_b[26]" LOC = A5;
NET "vme_data_b[25]" LOC = B5;
NET "vme_data_b[24]" LOC = A4;
NET "vme_data_b[23]" LOC = T8;
NET "vme_data_b[22]" LOC = P8;
NET "vme_data_b[21]" LOC = N8;
NET "vme_data_b[20]" LOC = M9;
NET "vme_data_b[19]" LOC = T9;
NET "vme_data_b[18]" LOC = R9;
NET "vme_data_b[17]" LOC = M10;
NET "vme_data_b[16]" LOC = L10;
NET "vme_data_b[15]" LOC = N6;
NET "vme_data_b[14]" LOC = M6;
NET "vme_data_b[13]" LOC = T4;
NET "vme_data_b[12]" LOC = P4;
NET "vme_data_b[11]" LOC = L7;
NET "vme_data_b[10]" LOC = L8;
NET "vme_data_b[9]" LOC = P5;
NET "vme_data_b[8]" LOC = N5;
NET "vme_data_b[7]" LOC = T5;
NET "vme_data_b[6]" LOC = R5;
NET "vme_data_b[5]" LOC = T6;
NET "vme_data_b[4]" LOC = P6;
NET "vme_data_b[3]" LOC = T7;
NET "vme_data_b[2]" LOC = R7;
NET "vme_data_b[1]" LOC = M7;
NET "vme_data_b[0]" LOC = P7;
NET "vme_am_i[5]" LOC = B8;
NET "vme_am_i[4]" LOC = C6;
NET "vme_am_i[3]" LOC = D6;
NET "vme_am_i[2]" LOC = A7;
NET "vme_am_i[1]" LOC = C7;
NET "vme_am_i[0]" LOC = E6;
NET "vme_addr_b[31]" LOC = E1;
NET "vme_addr_b[30]" LOC = E2;
NET "vme_addr_b[29]" LOC = L5;
NET "vme_addr_b[28]" LOC = L4;
NET "vme_addr_b[27]" LOC = H3;
NET "vme_addr_b[26]" LOC = J4;
NET "vme_addr_b[25]" LOC = K3;
NET "vme_addr_b[24]" LOC = F1;
NET "vme_addr_b[23]" LOC = F2;
NET "vme_addr_b[22]" LOC = G1;
NET "vme_addr_b[21]" LOC = G3;
NET "vme_addr_b[20]" LOC = H1;
NET "vme_addr_b[19]" LOC = H2;
NET "vme_addr_b[18]" LOC = J1;
NET "vme_addr_b[17]" LOC = J3;
NET "vme_addr_b[16]" LOC = K1;
NET "vme_addr_b[15]" LOC = K2;
NET "vme_addr_b[14]" LOC = L1;
NET "vme_addr_b[13]" LOC = L3;
NET "vme_addr_b[12]" LOC = M1;
NET "vme_addr_b[11]" LOC = M2;
NET "vme_addr_b[10]" LOC = N1;
NET "vme_addr_b[9]" LOC = N3;
NET "vme_addr_b[8]" LOC = P1;
NET "vme_addr_b[7]" LOC = P2;
NET "vme_addr_b[6]" LOC = R1;
NET "vme_addr_b[5]" LOC = R2;
NET "vme_addr_b[4]" LOC = N4;
NET "vme_addr_b[3]" LOC = M5;
NET "vme_addr_b[2]" LOC = M3;
NET "vme_addr_b[1]" LOC = M4;
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" LOC = F14;
NET "boot_config_o" LOC = C15;
NET "boot_done_i" LOC = C16;
NET "boot_dout_o" LOC = F13;
NET "boot_status_i" LOC = E16;
NET "debugled_n_o[2]" LOC = P15;
NET "debugled_n_o[1]" LOC = L16;
#IO standards
NET "vme_write_n_i" IOSTANDARD="LVCMOS33";
NET "vme_rst_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_retry_oe_o" IOSTANDARD="LVCMOS33";
#NET "vme_retry_n_o" IOSTANDARD="LVCMOS33";
NET "vme_lword_n_b" IOSTANDARD="LVCMOS33";
#NET "vme_iackout_n_o" IOSTANDARD="LVCMOS33";
#NET "vme_iackin_n_i" IOSTANDARD="LVCMOS33";
#NET "vme_iack_n_i" IOSTANDARD="LVCMOS33";
NET "vme_dtack_oe_o" IOSTANDARD="LVCMOS33";
NET "vme_dtack_n_o" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ds_n_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_data_dir_o" IOSTANDARD="LVCMOS33";
#NET "vme_berr_o" IOSTANDARD="LVCMOS33";
NET "vme_as_n_i" IOSTANDARD="LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD="LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[6]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[5]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[4]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[3]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[2]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[1]" IOSTANDARD="LVCMOS33";
#NET "vme_irq_n_o[0]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[5]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[2]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_ga_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[31]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[30]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[29]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[28]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[27]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[26]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[25]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[24]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[23]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[22]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[21]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[20]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[19]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[18]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[17]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[16]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[15]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[14]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[13]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[12]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[11]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[10]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[9]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[8]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[7]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[6]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[5]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[4]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[3]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[2]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[1]" IOSTANDARD="LVCMOS33";
NET "vme_data_b[0]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[5]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[4]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[3]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[2]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[1]" IOSTANDARD="LVCMOS33";
NET "vme_am_i[0]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[31]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[30]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[29]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[28]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[27]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[26]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[25]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[24]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[23]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[22]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[21]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[20]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[19]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[18]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[17]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[16]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[15]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[14]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[13]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[12]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[11]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[10]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[9]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[8]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[7]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[6]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[5]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[4]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[3]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[2]" IOSTANDARD="LVCMOS33";
NET "vme_addr_b[1]" IOSTANDARD="LVCMOS33";
#----------------------------------------
# Application FPGA boot control
#----------------------------------------
NET "boot_clk_o" IOSTANDARD="LVCMOS33";
NET "boot_config_o" IOSTANDARD="LVCMOS33";
NET "boot_done_i" IOSTANDARD="LVCMOS33";
NET "boot_dout_o" IOSTANDARD="LVCMOS33";
NET "boot_status_i" IOSTANDARD="LVCMOS33";
NET "debugled_n_o[2]" IOSTANDARD="LVCMOS33";
NET "debugled_n_o[1]" IOSTANDARD="LVCMOS33";
NET "spi_sclk_o" IOSTANDARD="LVCMOS33";
NET "spi_cs_n_o" IOSTANDARD="LVCMOS33";
NET "spi_mosi_o" IOSTANDARD="LVCMOS33";
NET "spi_miso_i" IOSTANDARD="LVCMOS33";
NET "spi_sclk_o" LOC = R11;
NET "spi_cs_n_o" LOC = T3;
NET "spi_mosi_o" LOC = T10;
NET "spi_miso_i" LOC = P10;
# Clocks/resets
NET "rst_n_i" LOC = E15;
NET "lclk_n_i" LOC = H5;
NET "rst_n_i" IOSTANDARD="LVCMOS33";
NET "lclk_n_i" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" IOSTANDARD="LVCMOS33";
NET "pll_ce_o" LOC=G14;
NET "afpga_flash_sck_i" LOC=G16;
NET "afpga_flash_mosi_i" LOC=H15;
NET "afpga_flash_cs_n_i" LOC=H16;
NET "afpga_flash_miso_o" LOC=J14;
NET "afpga_flash_sck_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_mosi_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_cs_n_i" IOSTANDARD=LVCMOS33;
NET "afpga_flash_miso_o" IOSTANDARD=LVCMOS33;
#Created by Constraints Editor (xc6slx9-ftg256-2) - 2014/01/15
NET "lclk_n_i" TNM_NET = lclk_n_i;
TIMESPEC TS_lclk_n_i = PERIOD "lclk_n_i" 20 MHz HIGH 50%;
hdl/top/svec7_sfpga/svec7_sfpga_top.vhd 0 → 100644
View file @ 29b98259
-------------------------------------------------------------------------------
-- Title : SVEC System FPGA top level
-- Project : Simple VME64x FMC Carrier (SVEC)
-------------------------------------------------------------------------------
-- File : svec_sfpga_top.vhd
-- Author : Tomasz Włostowski
-- Company : CERN BE-CO-HT
-- Created : 2012-03-20
-- Last update : 2013-01-25
-- Platform : FPGA-generic
-- Standard : VHDL '93
-------------------------------------------------------------------------------
-- Description: Top level of the System FPGA. Contains a stripped-down VME64x
-- core and the Appliaction FPGA bootloader core. Used solely for booting up
-- the AFPGA. Possible boot configurations are: HOST -> AFPGA, FLASH -> AFPGA
-- and HOST -> FLASH.
-------------------------------------------------------------------------------
--
-- Copyright (c) 2013 CERN / BE-CO-HT
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.svec_bootloader_pkg.all;
use work.vme64x_pkg.all;
library UNISIM;
use UNISIM.vcomponents.all;
entity svec7_sfpga_top is
port
(
-------------------------------------------------------------------------
-- Standard SVEC ports (Clocks & Reset)
-------------------------------------------------------------------------
lclk_i : in std_logic; -- 20 MHz VCXO clock
rst_n_i : in std_logic;
-------------------------------------------------------------------------
-- VME Interface pins
-------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
vme_noga_i : in std_logic_vector(4 downto 0);
vme_use_ga_i : in std_logic;
afpga_clk_i : in std_logic;
afpga_rst_n_i : in std_logic;
afpga_d_i : in std_logic_vector(7 downto 0);
afpga_d_o : out std_logic_vector(7 downto 0);
afpga_frame_i : in std_logic;
afpga_frame_o : out std_logic;
-------------------------------------------------------------------------
-- AFPGA boot signals
-------------------------------------------------------------------------
boot_clk_o : out std_logic;
boot_config_o : out std_logic;
boot_done_i : in std_logic;
boot_dout_o : out std_logic;
boot_status_i : in std_logic;
-------------------------------------------------------------------------
-- SPI Flash Interface
-------------------------------------------------------------------------
spi_cs_n_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
spi_sclk_o : out std_logic;
debugled_n_o : out std_logic_vector(2 downto 1);
-------------------------------------------------------------------------
-- Slave SPI interface allowing the Application FPGA to access the SPI flash
-------------------------------------------------------------------------
afpga_flash_sck_i : in std_logic;
afpga_flash_mosi_i : in std_logic;
afpga_flash_cs_n_i : in std_logic;
afpga_flash_miso_o : out std_logic;
-- Onboard PLL enable signal. Must be one for the clock system to work.
pll_ce_o : out std_logic
);
end svec7_sfpga_top;
architecture rtl of svec7_sfpga_top is
constant c_PLL_RESET_DURATION : integer := 300;
component reset_gen
port (
clk_sys_i : in std_logic;
rst_vme_n_a_i : in std_logic;
rst_local_n_a_i : in std_logic;
rst_n_o : out std_logic);
end component;
component sfpga_bootloader
generic (
g_interface_mode : t_wishbone_interface_mode;
g_address_granularity : t_wishbone_address_granularity;
g_idr_value : std_logic_vector(31 downto 0));
port (
clk_sys_i : in std_logic;
rst_n_i : in std_logic;
wb_cyc_i : in std_logic;
wb_stb_i : in std_logic;
wb_we_i : in std_logic;
wb_adr_i : in std_logic_vector(c_wishbone_address_width - 1 downto 0);
wb_sel_i : in std_logic_vector((c_wishbone_data_width + 7) / 8 - 1 downto 0);
wb_dat_i : in std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_dat_o : out std_logic_vector(c_wishbone_data_width-1 downto 0);
wb_ack_o : out std_logic;
wb_stall_o : out std_logic;
xlx_cclk_o : out std_logic := '0';
xlx_din_o : out std_logic;
xlx_program_b_o : out std_logic := '1';
xlx_init_b_i : in std_logic;
xlx_done_i : in std_logic;
xlx_suspend_o : out std_logic;
xlx_m_o : out std_logic_vector(1 downto 0);
boot_trig_p1_o : out std_logic := '0';
boot_exit_p1_o : out std_logic := '0';
boot_en_i : in std_logic;
spi_cs_n_o : out std_logic;
spi_sclk_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic);
end component;
component chipscope_ila
port (
CONTROL : inout std_logic_vector(35 downto 0);
CLK : in std_logic;
TRIG0 : in std_logic_vector(31 downto 0);
TRIG1 : in std_logic_vector(31 downto 0);
TRIG2 : in std_logic_vector(31 downto 0);
TRIG3 : in std_logic_vector(31 downto 0));
end component;
component chipscope_icon
port (
CONTROL0 : inout std_logic_vector (35 downto 0));
end component;
-- signal VME_DATA_o_int : std_logic_vector(31 downto 0);
-- signal vme_dtack_oe_int, VME_DTACK_n_int : std_logic;
-- signal VME_DATA_OE_N_int : std_logic;
signal wb_vme_in : t_wishbone_master_out;
signal wb_vme_out : t_wishbone_master_in;
signal passive : std_logic;
-- VME bootloader is inactive by default
signal boot_en : std_logic := '1';
signal boot_trig_p1, boot_exit_p1 : std_logic;
signal CONTROL : std_logic_vector(35 downto 0);
signal CLK : std_logic;
signal TRIG0 : std_logic_vector(31 downto 0);
signal TRIG1 : std_logic_vector(31 downto 0);
signal TRIG2 : std_logic_vector(31 downto 0);
signal TRIG3 : std_logic_vector(31 downto 0);
signal boot_config_int : std_logic;
signal erase_afpga_n, erase_afpga_n_d0 : std_logic;
signal pllout_clk_fb_sys, pllout_clk_sys, clk_sys : std_logic;
signal rst_n_sys : std_logic;
signal go_passive : std_logic;
signal vme_idle : std_logic;
signal pll_reset_count : unsigned(15 downto 0);
signal spi_cs_n_int, spi_mosi_int, spi_sclk_int : std_logic;
signal pass_flash: std_logic;
signal vme_in : t_vme64x_in;
signal vme_out_boot : t_vme64x_out;
signal vme_out_bridge : t_vme64x_out;
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n : std_logic;
signal vme_irq_n : std_logic_vector(7 downto 1);
signal addr_decoder_in : std_logic_vector(31 downto 1);
signal addr_decoder_out : std_logic_vector(31 downto 1);
signal decode_start : std_logic;
signal decode_done : std_logic;
signal r_am : std_logic_vector(5 downto 0);
signal decode_sel : std_logic;
signal cr_csr_addr : std_logic_vector(18 downto 2);
signal cr_csr_data_in : std_logic_vector(7 downto 0);
signal cr_csr_data_out : std_logic_vector(7 downto 0);
signal cr_csr_we : std_logic;
signal cr_csr_req : std_logic;
signal cr_csr_done : std_logic;
signal r_module_enable : std_logic;
signal r_bar : std_logic_vector(4 downto 0);
signal r_int_level : std_logic_vector(2 downto 0);
signal r_int_vector : std_logic_vector(7 downto 0);
signal r_irq_pending : std_logic;
signal r_irq_ack : std_logic;
begin
-- PLL for producing 83.3 MHz system clock (clk_sys) from a 20 MHz reference.
U_Sys_clk_pll : PLL_BASE
generic map (
BANDWIDTH => "OPTIMIZED",
CLK_FEEDBACK => "CLKFBOUT",
COMPENSATION => "INTERNAL",
DIVCLK_DIVIDE => 1,
CLKFBOUT_MULT => 50,
CLKFBOUT_PHASE => 0.000,
CLKOUT0_DIVIDE => 12, -- 83.3 MHz
CLKOUT0_PHASE => 0.000,
CLKOUT0_DUTY_CYCLE => 0.500,
CLKOUT1_DIVIDE => 16, -- 62.5 MHz
CLKOUT1_PHASE => 0.000,
CLKOUT1_DUTY_CYCLE => 0.500,
CLKOUT2_DIVIDE => 8,
CLKOUT2_PHASE => 0.000,
CLKOUT2_DUTY_CYCLE => 0.500,
CLKIN_PERIOD => 50.0,
REF_JITTER => 0.016)
port map (
CLKFBOUT => pllout_clk_fb_sys,
CLKOUT0 => pllout_clk_sys,
CLKOUT1 => open, --pllout_clk_sys,
CLKOUT2 => open,
CLKOUT3 => open,
CLKOUT4 => open,
CLKOUT5 => open,
LOCKED => open,
RST => '0',
CLKFBIN => pllout_clk_fb_sys,
CLKIN => lclk_i);
U_clk_sys_buf : BUFG
port map (
O => clk_sys,
I => pllout_clk_sys);
U_Powerup_Reset : reset_gen
port map (
clk_sys_i => clk_sys,
rst_vme_n_a_i => vme_sysreset_n_i,
rst_local_n_a_i => rst_n_i,
rst_n_o => rst_n_sys);
-------------------------------------------------------------------------------
-- Chipscope instantiation (for VME bus monitoring, I sincerely hate VMetro)
-------------------------------------------------------------------------------
chipscope_ila_1 : chipscope_ila
port map (
CONTROL => CONTROL,
CLK => clk_sys,
TRIG0 => TRIG0,
TRIG1 => TRIG1,
TRIG2 => TRIG2,
TRIG3 => TRIG3);
chipscope_icon_1 : chipscope_icon
port map (
CONTROL0 => CONTROL);
-- TRIG0(31 downto 1) <= VME_ADDR_b;
-- TRIG1(31 downto 0) <= VME_DATA_b;
-- TRIG2(5 downto 0) <= VME_AM_i;
-- trig2(7 downto 6) <= VME_DS_n_i;
-- trig2(13 downto 8) <= VME_GA_i;
-- trig2(14) <= VME_DTACK_n_o;
-- trig2(15) <= VME_DTACK_oe_o;
-- trig2(16) <= VME_LWORD_n_b;
-- trig2(17) <= VME_WRITE_n_i;
-- trig2(18) <= VME_AS_n_i;
-- trig2(19) <= VME_DATA_DIR_o;
-- trig2(20) <= VME_DATA_OE_N_o;
-- trig2(21) <= VME_addr_DIR_o;
-- trig2(22) <= VME_addr_OE_N_o;
-- trig2(23) <= rst_n_i;
-- trig2(24) <= '1';
-- trig2(25) <= VME_RST_n_i;
-- trig2(26) <= passive;
-- trig2(27) <= vme_idle;
-- trig2(28) <= rst_n_sys;
xvme64x_core_master_1: entity work.xvme64x_core_master
generic map (
g_CLOCK_PERIOD => 8)
port map (
afpga_clk_i => afpga_clk_i,
afpga_rst_n_i => afpga_rst_n_i,
vme_i => vme_in,
vme_o => vme_out_bridge,
afpga_d_i => afpga_d_i,
afpga_frame_i => afpga_frame_i,
afpga_d_o => afpga_d_o,
afpga_frame_o => afpga_frame_o);
vme_ga <= vme_gap_i & vme_ga_i;
vme_in.as_n <= vme_as_n_i;
vme_in.rst_n <= vme_sysreset_n_i;
vme_in.write_n <= vme_write_n_i;
vme_in.am <= vme_am_i;
vme_in.ds_n <= vme_ds_n_i;
vme_in.ga <= vme_ga;
vme_in.lword_n <= vme_lword_n_b;
vme_in.addr <= vme_addr_b;
vme_in.data <= vme_data_b;
vme_in.iack_n <= vme_iack_n_i;
vme_in.iackin_n <= vme_iackin_n_i;
-- U_Bridge : entity work.svec7_sfpga_bridge
-- generic map (
-- g_clock_period => 8)
-- port map (
-- afpga_rst_n_i => afpga_rst_n_i,
-- afpga_clk_i => afpga_clk_i,
-- afpga_d_i => afpga_d_i,
-- afpga_frame_i => afpga_frame_i,
-- afpga_d_o => afpga_d_o,
-- afpga_frame_o => afpga_frame_o,
-- vme_i => vme_in,
-- vme_o => vme_out_bridge);
U_MiniVME : entity work.xmini_vme
generic map (
g_user_csr_start => resize(x"70000", 21),
g_user_csr_end => resize(x"70020", 21))
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
vme_i => vme_in,
vme_o => vme_out_boot,
master_o => wb_vme_in,
master_i => wb_vme_out,
idle_o => vme_idle);
U_Bootloader_Core : sfpga_bootloader
generic map (
g_interface_mode => CLASSIC,
g_address_granularity => BYTE,
g_idr_value => c_CSR_SIGNATURE)
port map (
clk_sys_i => clk_sys,
rst_n_i => rst_n_sys,
wb_cyc_i => wb_vme_in.cyc,
wb_stb_i => wb_vme_in.stb,
wb_we_i => wb_vme_in.we,
wb_adr_i => wb_vme_in.adr,
wb_sel_i => wb_vme_in.sel,
wb_dat_i => wb_vme_in.dat,
wb_dat_o => wb_vme_out.dat,
wb_ack_o => wb_vme_out.ack,
wb_stall_o => wb_vme_out.stall,
xlx_cclk_o => boot_clk_o,
xlx_din_o => boot_dout_o,
xlx_program_b_o => boot_config_int,
xlx_init_b_i => boot_status_i,
xlx_done_i => boot_done_i,
boot_trig_p1_o => boot_trig_p1,
boot_exit_p1_o => boot_exit_p1,
boot_en_i => boot_en,
spi_cs_n_o => spi_cs_n_int,
spi_sclk_o => spi_sclk_int,
spi_mosi_o => spi_mosi_int,
spi_miso_i => spi_miso_i);
-- produces a longer pulse on PROGRAM_B pin of the Application FPGA when
-- the VME bootloader mode is activated
U_Extend_Erase_Pulse : gc_extend_pulse
generic map (
g_width => 100)
port map (
clk_i => clk_sys,
rst_n_i => rst_n_sys,
pulse_i => boot_trig_p1,
extended_o => erase_afpga_n);
-- Erase the application FPGA as soon as we have received a bootloader
-- trigger command - this is to prevent two VME cores from working simultaneously
-- on a single bus.
boot_config_o <= boot_config_int and (not erase_afpga_n);
p_enable_disable_bootloader : process(clk_sys)
begin
if rising_edge(clk_sys) then
if(rst_n_sys = '0') then
boot_en <= '0'; -- VME bootloader is inactive after reset
go_passive <= '0';
else
erase_afpga_n_d0 <= erase_afpga_n;
-- VME activation occurs after erasing the AFPGA
if(erase_afpga_n = '0' and erase_afpga_n_d0 = '1') then
boot_en <= '1';
go_passive <= '0';
elsif(boot_exit_p1 = '1') then
go_passive <= '1';
elsif (go_passive = '1' and vme_idle = '1') then
go_passive <= '0';
boot_en <= '0';
end if;
end if;
end if;
end process;
-- drive the PLL CE (powerup reset)
p_reset_cdcm61004_pll : process(clk_sys)
begin
if rising_edge(clk_sys) then
if rst_n_sys = '0' then
pll_reset_count <= (others => '0');
pll_ce_o <= '0';
else
if(pll_reset_count = c_PLL_RESET_DURATION) then
pll_ce_o <= '1';
else
pll_reset_count <= pll_reset_count + 1;
end if;
end if;
end if;
end process;
-- multiplex flash access between the AFPGA and SFPGA bootloader (if the
-- AFPGA is programmed, it's wired to the SPI flash).
spi_cs_n_o <= spi_cs_n_int when boot_done_i = '0' else afpga_flash_cs_n_i;
spi_sclk_o <= spi_sclk_int when boot_done_i = '0' else afpga_flash_sck_i;
spi_mosi_o <= spi_mosi_int when boot_done_i = '0' else afpga_flash_mosi_i;
afpga_flash_miso_o <= spi_miso_i;
-- When the VME bootloader is not active, do NOT drive any outputs and sit quiet.
passive <= not boot_en;
vme_berr_n <= vme_out_bridge.berr_n;
VME_DTACK_n_o <= vme_out_bridge.dtack_n;
vme_retry_n_o <= vme_out_bridge.retry_n;
vme_retry_oe_o <= vme_out_bridge.retry_oe;
vme_lword_n_b_out <= vme_out_bridge.lword_n;
vme_data_b_out <= vme_out_bridge.data;
vme_addr_b_out <= vme_out_bridge.addr;
vme_irq_n <= vme_out_bridge.irq_n;
vme_iackout_n_o <= vme_out_bridge.iackout_n;
VME_DTACK_oe_o <= vme_out_bridge.dtack_oe;
vme_data_dir_int <= vme_out_bridge.data_dir;
VME_DATA_OE_N_o <= vme_out_bridge.data_oe_n;
vme_addr_dir_int <= vme_out_bridge.addr_dir;
VME_addr_OE_N_o <= vme_out_bridge.addr_oe_n;
-- VME_ADDR_b <= (others => 'Z');
-- VME_DTACK_n_o <= VME_DTACK_n_int when passive = '0' else 'Z';
-- vme_dtack_oe_o <= vme_dtack_oe_int when passive = '0' else 'Z';
-- VME_DATA_DIR_o <= vme_data_dir_int when passive = '0' else 'Z';
-- VME_DATA_OE_N_o <= VME_DATA_OE_N_int when passive = '0' else 'Z';
-- VME_DATA_b <= VME_DATA_o_int when (passive = '0' and VME_DATA_OE_N_int = '0' and vme_data_dir_int = '1') else (others => 'Z');
-- VME_ADDR_OE_N_o <= '0' when passive = '0' else 'Z';
-- VME_ADDR_DIR_o <= '0' when passive = '0' else 'Z';
-- VME_LWORD_n_b <= 'Z';
debugled_n_o(1) <= '1';
debugled_n_o(2) <= not boot_en;
vme_berr_o <= not vme_berr_n;
vme_irq_o <= not vme_irq_n;
-- VME tri-state buffers
vme_data_b <= vme_data_b_out when vme_data_dir_int = '1' else (others => 'Z');
vme_addr_b <= vme_addr_b_out when vme_addr_dir_int = '1' else (others => 'Z');
vme_lword_n_b <= vme_lword_n_b_out when vme_addr_dir_int = '1' else 'Z';
vme_addr_dir_o <= vme_addr_dir_int;
vme_data_dir_o <= vme_data_dir_int;
end rtl;
hdl/top/svec7_test/svec7_test_top.vhd
View file @ 29b98259
......@@ -44,7 +44,7 @@ use unisim.vcomponents.all;
entity svec7_test_top is
generic (
g_WRPC_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy16.bram";
g_WRPC_INITF : string := "none"; --"../../../../ip_cores/wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the
-- testbench. Its purpose is to reduce some internal counters/timeouts
......@@ -61,11 +61,11 @@ entity svec7_test_top is
-- Local oscillators
clk_20m_vcxo_i : in std_logic; -- 20MHz VCXO clock
clk_62m5_pllref_p_i : in std_logic; -- 62.5 MHz PLL reference
clk_62m5_pllref_n_i : in std_logic;
clk_125m_pllref_p_i : in std_logic; -- 62.5 MHz PLL reference
clk_125m_pllref_n_i : in std_logic;
clk_125m_gtx_n_i : in std_logic; -- 125 MHz GTX reference
clk_125m_gtx_p_i : in std_logic;
clk_125m_gtp_n_i : in std_logic; -- 125 MHz GTX reference
clk_125m_gtp_p_i : in std_logic;
-- PLL_2AFPGA pins
clk_fpga2_p_i : in std_logic;
......@@ -76,37 +76,18 @@ entity svec7_test_top is
---------------------------------------------------------------------------
-- VME interface
-- VME Bridge interface
---------------------------------------------------------------------------
vme_write_n_i : in std_logic;
vme_sysreset_n_i : in std_logic;
vme_retry_oe_o : out std_logic;
vme_retry_n_o : out std_logic;
vme_lword_n_b : inout std_logic;
vme_iackout_n_o : out std_logic;
vme_iackin_n_i : in std_logic;
vme_iack_n_i : in std_logic;
vme_gap_i : in std_logic;
vme_dtack_oe_o : out std_logic;
vme_dtack_n_o : out std_logic;
vme_ds_n_i : in std_logic_vector(1 downto 0);
vme_data_oe_n_o : out std_logic;
vme_data_dir_o : out std_logic;
vme_berr_o : out std_logic;
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
vme_addr_b : inout std_logic_vector(31 downto 1);
vme_noga_i : in std_logic_vector(4 downto 0);
vme_use_ga_i : in std_logic;
vme_sysreset_n_i : in std_logic;
sfpga_clk_o : out std_logic;
sfpga_rst_n_o : out std_logic;
sfpga_frame_o : out std_logic;
sfpga_d_o : out std_logic_vector(7 downto 0);
sfpga_frame_i : in std_logic := '0';
sfpga_d_i : in std_logic_vector(7 downto 0) := x"00";
---------------------------------------------------------------------------
-- SPI interfaces to DACs
---------------------------------------------------------------------------
......@@ -289,7 +270,7 @@ architecture arch of svec7_test_top is
constant c_WB_SLAVE_GPIO : integer := 1;
constant c_WB_SLAVE_CLOCK_MON : integer := 2;
-- Convention metadata base address
-- Convention metadata base addr`ess
constant c_METADATA_ADDR : t_wishbone_address := x"0000_2000";
-- Primary wishbone crossbar layout
......@@ -323,7 +304,7 @@ architecture arch of svec7_test_top is
signal areset_n : std_logic;
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
signal clk_ref_62m5 : std_logic;
signal clk_ref_125m : std_logic;
signal clk_ext_ref : std_logic;
attribute keep : string;
......@@ -484,36 +465,22 @@ begin -- architecture arch
g_VERBOSE => false)
port map (
rst_n_i => areset_n,
clk_62m5_pllref_p_i => clk_62m5_pllref_p_i,
clk_62m5_pllref_n_i => clk_62m5_pllref_n_i,
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtx_n_i => clk_125m_gtx_n_i,
clk_125m_gtx_p_i => clk_125m_gtx_p_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
clk_10m_ext_i => clk_ext_ref,
pps_ext_i => pps_ext_in,
vme_write_n_i => vme_write_n_i,
vme_sysreset_n_i => vme_sysreset_n_i,
vme_retry_oe_o => vme_retry_oe_o,
vme_retry_n_o => vme_retry_n_o,
vme_lword_n_b => vme_lword_n_b,
vme_iackout_n_o => vme_iackout_n_o,
vme_iackin_n_i => vme_iackin_n_i,
vme_iack_n_i => vme_iack_n_i,
vme_gap_i => vme_gap_i,
vme_dtack_oe_o => vme_dtack_oe_o,
vme_dtack_n_o => vme_dtack_n_o,
vme_ds_n_i => vme_ds_n_i,
vme_data_oe_n_o => vme_data_oe_n_o,
vme_data_dir_o => vme_data_dir_o,
vme_berr_o => vme_berr_o,
vme_as_n_i => vme_as_n_i,
vme_addr_oe_n_o => vme_addr_oe_n_o,
vme_addr_dir_o => vme_addr_dir_o,
vme_irq_o => vme_irq_o,
vme_ga_i => vme_ga_i,
vme_data_b => vme_data_b,
vme_am_i => vme_am_i,
vme_addr_b => vme_addr_b,
vme_sysreset_n_i => vme_sysreset_n_i,
sfpga_frame_i => sfpga_frame_i,
sfpga_frame_o => sfpga_frame_o,
sfpga_d_i => sfpga_d_i,
sfpga_d_o => sfpga_d_o,
sfpga_clk_o => sfpga_clk_o,
sfpga_rst_n_o => sfpga_rst_n_o,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc1_scl_b => fmc1_scl_b,
......@@ -550,8 +517,8 @@ begin -- architecture arch
pcbrev_i => pcbrev_i,
clk_sys_62m5_o => clk_sys_62m5,
rst_sys_62m5_n_o => rst_sys_62m5_n,
clk_ref_62m5_o => clk_ref_62m5,
rst_ref_62m5_n_o => open,
clk_ref_125m_o => clk_ref_125m,
rst_ref_125m_n_o => open,
irq_user_i => irq_vector,
pps_p_o => pps,
pps_led_o => pps_led,
......@@ -661,8 +628,6 @@ begin -- architecture arch
fp_gpio34_a2b_o <= gpio_out(3);
gpio_in(4 downto 0) <= vme_noga_i;
gpio_in(5) <= vme_use_ga_i;
gen_fmc_iobufs : for i in 0 to 33 generate
......
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