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Simple VME FMC Carrier SVEC
Commit 1fdb8ecb authored by Tristan Gingold's avatar Tristan Gingold
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vmecore_test: adjust to xvme64x_core changes.

parent b0f15427
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Showing with 68 additions and 72 deletions
hdl/top/vmecore_test/svec_vmecore_test_top.ucf
View file @ 1fdb8ecb
......@@ -23,13 +23,13 @@ NET "vme_berr_o" LOC = R3;
NET "vme_as_n_i" LOC = P6;
NET "vme_addr_oe_n_o" LOC = N4;
NET "vme_addr_dir_o" LOC = N5;
NET "vme_irq_n_o[7]" LOC = R7;
NET "vme_irq_n_o[6]" LOC = AH2;
NET "vme_irq_n_o[5]" LOC = AF2;
NET "vme_irq_n_o[4]" LOC = N9;
NET "vme_irq_n_o[3]" LOC = N10;
NET "vme_irq_n_o[2]" LOC = AH4;
NET "vme_irq_n_o[1]" LOC = AG4;
NET "vme_irq_o[7]" LOC = R7;
NET "vme_irq_o[6]" LOC = AH2;
NET "vme_irq_o[5]" LOC = AF2;
NET "vme_irq_o[4]" LOC = N9;
NET "vme_irq_o[3]" LOC = N10;
NET "vme_irq_o[2]" LOC = AH4;
NET "vme_irq_o[1]" LOC = AG4;
NET "vme_gap_i" LOC = M6;
NET "vme_ga_i[4]" LOC = V9;
NET "vme_ga_i[3]" LOC = V10;
......@@ -123,13 +123,13 @@ NET "vme_berr_o" IOSTANDARD = "LVCMOS33";
NET "vme_as_n_i" IOSTANDARD = "LVCMOS33";
NET "vme_addr_oe_n_o" IOSTANDARD = "LVCMOS33";
NET "vme_addr_dir_o" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_n_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[7]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[6]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[5]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[4]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[3]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[2]" IOSTANDARD = "LVCMOS33";
NET "vme_irq_o[1]" IOSTANDARD = "LVCMOS33";
NET "vme_gap_i" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[4]" IOSTANDARD = "LVCMOS33";
NET "vme_ga_i[3]" IOSTANDARD = "LVCMOS33";
......@@ -370,10 +370,10 @@ NET "vme_sysreset_n_i" TIG;
# Force PPS output to always be placed as IOB register
#INST "cmp_xwrc_board_svec/cmp_board_common/cmp_xwr_core/wrpc/pps_gen/wrapped_ppsgen/pps_out_o" IOB = FORCE;
INST "vme_irq_n_o[7]" IOB=FORCE;
INST "vme_irq_n_o[6]" IOB=FORCE;
INST "vme_irq_n_o[5]" IOB=FORCE;
INST "vme_irq_n_o[4]" IOB=FORCE;
INST "vme_irq_n_o[3]" IOB=FORCE;
INST "vme_irq_n_o[2]" IOB=FORCE;
INST "vme_irq_n_o[1]" IOB=FORCE;
INST "vme_irq_o[7]" IOB=FORCE;
INST "vme_irq_o[6]" IOB=FORCE;
INST "vme_irq_o[5]" IOB=FORCE;
INST "vme_irq_o[4]" IOB=FORCE;
INST "vme_irq_o[3]" IOB=FORCE;
INST "vme_irq_o[2]" IOB=FORCE;
INST "vme_irq_o[1]" IOB=FORCE;
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
View file @ 1fdb8ecb
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2017-11-14
-- Last update: 2017-11-24
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -87,7 +87,7 @@ entity svec_vmecore_test_top is
vme_as_n_i : in std_logic;
vme_addr_oe_n_o : out std_logic;
vme_addr_dir_o : out std_logic;
vme_irq_n_o : out std_logic_vector(7 downto 1);
vme_irq_o : out std_logic_vector(7 downto 1);
vme_ga_i : in std_logic_vector(4 downto 0);
vme_data_b : inout std_logic_vector(31 downto 0);
vme_am_i : in std_logic_vector(5 downto 0);
......@@ -187,9 +187,11 @@ architecture top of svec_vmecore_test_top is
signal vme_data_b_out : std_logic_vector(31 downto 0);
signal vme_addr_b_out : std_logic_vector(31 downto 1);
signal vme_lword_n_b_out : std_logic;
signal Vme_data_dir_int : std_logic;
signal vme_data_dir_int : std_logic;
signal vme_addr_dir_int : std_logic;
signal vme_ga : std_logic_vector(5 downto 0);
signal vme_berr_n_o : std_logic;
signal vme_irq_n_o : std_logic_vector(7 downto 1);
-- LEDs and GPIO
signal pps : std_logic;
......@@ -205,8 +207,6 @@ architecture top of svec_vmecore_test_top is
signal powerup_reset_cnt : unsigned(7 downto 0) := "00000000";
signal powerup_rst_n : std_logic := '0';
signal sys_locked : std_logic;
signal s_irq : std_logic;
begin -- architecture top
p_powerup_reset : process(clk_sys)
......@@ -288,50 +288,50 @@ begin -- architecture top
-- VME64x Core and buffers
-----------------------------------------------------------------------------
inst_vme_core : vme64x_core
-- BERR and IRQ vme signals are inverted by the drivers. See schematics.
vme_berr_o <= not vme_berr_n_o;
vme_irq_o <= not vme_irq_n_o;
inst_vme_core : xvme64x_core
generic map (
g_CLOCK_PERIOD => 8,
g_USER_CSR_EXT => False)
g_DECODE_AM => True,
g_USER_CSR_EXT => False,
g_MANUFACTURER_ID => c_CERN_ID,
g_BOARD_ID => c_SVEC_ID,
g_REVISION_ID => c_SVEC_REVISION_ID,
g_PROGRAM_ID => c_PROGRAM_ID)
port map (
clk_i => clk_sys,
rst_n_i => local_reset_n,
VME_AS_n_i => vme_as_n_i,
VME_RST_n_i => vme_sysreset_n_i,
VME_WRITE_n_i => vme_write_n_i,
VME_AM_i => vme_am_i,
VME_DS_n_i => vme_ds_n_i,
VME_GA_i => vme_ga,
VME_BERR_o => vme_berr_o,
VME_DTACK_n_o => vme_dtack_n_o,
VME_RETRY_n_o => vme_retry_n_o,
VME_RETRY_OE_o => vme_retry_oe_o,
VME_LWORD_n_i => vme_lword_n_b,
VME_LWORD_n_o => vme_lword_n_b_out,
VME_ADDR_i => vme_addr_b,
VME_DATA_o => vme_data_b_out,
VME_ADDR_o => vme_addr_b_out,
VME_DATA_i => vme_data_b,
VME_IRQ_o => vme_irq_n_o,
VME_IACK_n_i => vme_iack_n_i,
VME_IACKIN_n_i => vme_iackin_n_i,
VME_IACKOUT_n_o => vme_iackout_n_o,
VME_DTACK_OE_o => vme_dtack_oe_o,
VME_DATA_DIR_o => vme_data_dir_int,
VME_DATA_OE_N_o => vme_data_oe_n_o,
VME_ADDR_DIR_o => vme_addr_dir_int,
VME_ADDR_OE_N_o => vme_addr_oe_n_o,
DAT_i => master_in.dat,
DAT_o => master_out.dat,
ADR_o => master_out.adr,
CYC_o => master_out.cyc,
ERR_i => master_in.err,
SEL_o => master_out.sel,
STB_o => master_out.stb,
ACK_i => master_in.ack,
WE_o => master_out.we,
STALL_i => master_in.stall,
irq_i => s_irq);
vme_i.as_n => vme_as_n_i,
vme_i.rst_n => vme_sysreset_n_i,
vme_i.write_n => vme_write_n_i,
vme_i.am => vme_am_i,
vme_i.ds_n => vme_ds_n_i,
vme_i.ga => vme_ga,
vme_i.lword_n => vme_lword_n_b,
vme_i.addr => vme_addr_b,
vme_i.data => vme_data_b,
vme_i.iack_n => vme_iack_n_i,
vme_i.iackin_n => vme_iackin_n_i,
vme_o.berr_n => vme_berr_n_o,
vme_o.dtack_n => vme_dtack_n_o,
vme_o.retry_n => vme_retry_n_o,
vme_o.retry_oe => vme_retry_oe_o,
vme_o.lword_n => vme_lword_n_b_out,
vme_o.data => vme_data_b_out,
vme_o.addr => vme_addr_b_out,
vme_o.irq_n => vme_irq_n_o,
vme_o.iackout_n => vme_iackout_n_o,
vme_o.dtack_oe => vme_dtack_oe_o,
vme_o.data_dir => vme_data_dir_int,
vme_o.data_oe_n => vme_data_oe_n_o,
vme_o.addr_dir => vme_addr_dir_int,
vme_o.addr_oe_n => vme_addr_oe_n_o,
wb_i => master_in,
wb_o => master_out);
vme_ga <= vme_gap_i & vme_ga_i;
......@@ -385,6 +385,5 @@ begin -- architecture top
rst_n_i => local_reset_n,
slave_i => master_out,
slave_o => master_in,
leds_o => svec_led,
irq_o => s_irq);
leds_o => svec_led);
end architecture top;
hdl/top/vmecore_test/vmecore_test.vhd
View file @ 1fdb8ecb
......@@ -42,9 +42,7 @@ entity vmecore_test is
slave_i : in t_wishbone_slave_in;
slave_o : out t_wishbone_slave_out;
leds_o : out std_logic_vector(15 downto 0);
irq_o : out std_logic
);
leds_o : out std_logic_vector(15 downto 0));
end vmecore_test;
......@@ -221,11 +219,10 @@ begin
end process;
leds_o <= leds;
irq_o <= '1' when counter = 1 else '0';
slave_o.int <= '1' when counter = 1 else '0';
-- drive unused WB slave_o outputs
slave_o.stall <= '0';
slave_o.rty <= '0';
slave_o.int <= '0';
end rtl;
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