Skip to content

S
Simple VME FMC Carrier SVEC
Commit b0f15427 authored by Tristan Gingold's avatar Tristan Gingold
Browse files
Options

Update Manifest.py and vmecore_test after last change in vme64x_core.

parent 6890d830
Hide whitespace changes
Inline Side-by-side
Showing with 5 additions and 11 deletions
hdl/syn/vmecore_test/Manifest.py
View file @ b0f15427
......@@ -13,6 +13,3 @@ modules = {
"../../top/vmecore_test",
],
}
fetchto="../../ip_cores"
hdl/top/vmecore_test/Manifest.py
View file @ b0f15427
fetchto = "../../ip_cores"
files = [
"svec_vmecore_test_top.vhd",
"svec_vmecore_test_top.ucf",
"vmecore_test.vhd",
]
modules = {
"git" : [ "git://ohwr.org/hdl-core-lib/general-cores.git",
"git://ohwr.org/hdl-core-lib/vme64x-core.git" ]
modules = { "local": [ "../../ip_cores/general-cores",
"../../ip_cores/vme64x-core" ]
}
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
View file @ b0f15427
......@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2017-10-09
-- Last update: 2017-11-14
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
......@@ -42,7 +42,7 @@ use ieee.numeric_std.all;
library work;
use work.gencores_pkg.all;
use work.wishbone_pkg.all;
use work.vme64x_pack.all;
use work.vme64x_pkg.all;
library unisim;
use unisim.vcomponents.all;
......@@ -288,7 +288,7 @@ begin -- architecture top
-- VME64x Core and buffers
-----------------------------------------------------------------------------
inst_vme_core : vme64xcore_top
inst_vme_core : vme64x_core
generic map (
g_CLOCK_PERIOD => 8,
g_USER_CSR_EXT => False)
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment