vmecore_test: modify tb for 2esst

00515ebb · Tristan Gingold · 56654022 · 00515ebb · 00515ebb · 00515ebb
Commit 00515ebb authored Jun 04, 2020 by Tristan Gingold
4 changed files
--- a/hdl/testbench/tb_vmecore_test/tb_vmecore_test.vhd
+++ b/hdl/testbench/tb_vmecore_test/tb_vmecore_test.vhd
@@ -88,6 +88,8 @@ begin
    variable d8 : byte_t;
    variable d16 : word_t;
    variable d32 : lword_t;
+    variable arr64 : qword_array_t (31 downto 0);
  begin
    --  Each scenario starts with a reset.
    --  VME reset
@@ -109,7 +111,7 @@ begin
    -- Set ADER
    write8_conf (vme_in, vme_out, vme_timeout, x"7_ff77", x"10");
-    write8_conf (vme_in, vme_out, vme_timeout, x"7_ff7f", c_AM_A24 & "00");
+    write8_conf (vme_in, vme_out, vme_timeout, x"7_ff7f", c_AM_2EVME_6U & "00");
    read8_conf  (vme_in, vme_out, vme_timeout, x"7_ff77", d8);
    assert d8 = x"10" report "bad ADER0 value" severity error;
@@ -122,6 +124,13 @@ begin
      severity error;
    report "read data: " & hex (d8);
+    --  2eSST transfer at 267
+    read64_2esst (vme_in, vme_out, vme_timeout, x"00_10_00_00",
+                  c_XAM_A32_2ESST, "0001", arr64);
+    for i in arr64'range loop
+      write(output, hex(arr64(i)) & LF);
+    end loop;
    -- dump_CR (vme_in, vme_out, vme_timeout);
    report "Dump patterns";

--- a/hdl/top/vmecore_test/Manifest.py
+++ b/hdl/top/vmecore_test/Manifest.py
@@ -5,5 +5,6 @@ files = [
 ]
 modules = { 'git': [ "git://ohwr.org/project/general-cores.git",
-                     "git://ohwr.org/project/vme64x-core.git" ]
+                     "git://ohwr.org/project/vme64x-core.git" ],
+            'system': [ 'xilinx', 'vhdl' ],
 }
--- a/hdl/top/vmecore_test/svec_vmecore_test_top.vhd
+++ b/hdl/top/vmecore_test/svec_vmecore_test_top.vhd
@@ -7,7 +7,7 @@
 -- Author(s)  : Tristan Gingold  <tristan.gingold@cern.ch>
 -- Company    : CERN (BE-CO-HT)
 -- Created    : 2017-09-19
-- Last update: 2020-05-29
+-- Last update: 2020-06-04
 -- Standard   : VHDL'93
 -------------------------------------------------------------------------------
 -- Description: Top-level file for the test design .
@@ -283,12 +283,12 @@ begin  -- architecture top
    process
    begin
      clk_sys <= '0';
-      wait for 8 ns;
+      wait for 4 ns;
      clk_sys <= '1';
-      wait for 8 ns;
+      wait for 4 ns;
    end process;
-    local_reset_n <= '0', '1' after 16 ns;
+    local_reset_n <= '0', '1' after 8 ns;
  end generate;
  -----------------------------------------------------------------------------
@@ -301,15 +301,18 @@ begin  -- architecture top
  inst_vme_core : xvme64x_core
    generic map (
-      g_CLOCK_PERIOD => 8,
+      g_CLOCK_PERIOD   => 8,
-      g_DECODE_AM => True,
+      g_VME_2e         => True,
-      g_USER_CSR_EXT => False,
+      g_DECODE_AM      => False,
+      g_USER_CSR_EXT   => False,
      g_wb_granularity => WORD,
+      g_WB_MODE        => PIPELINED,
      g_MANUFACTURER_ID => c_CERN_ID,
      g_BOARD_ID        => c_SVEC_ID,
      g_REVISION_ID     => c_SVEC_REVISION_ID,
-      g_PROGRAM_ID      => c_SVEC_PROGRAM_ID)
+      g_PROGRAM_ID      => c_SVEC_PROGRAM_ID,
+      g_DECODER         => c_vme64x_decoders_2e_default)
    port map (
      clk_i           => clk_sys,
      rst_n_i         => local_reset_n,

--- a/hdl/top/vmecore_test/vmecore_test.vhd
+++ b/hdl/top/vmecore_test/vmecore_test.vhd
@@ -75,8 +75,10 @@ architecture rtl of vmecore_test is
 begin
  --  Pattern of the pattern ram.
-  pattern (31 downto 16) <= not slave_i.adr(15 downto 0);
+  pattern (7 downto 0)  <= slave_i.adr(7 downto 0);
-  pattern (15 downto 0)  <= slave_i.adr(15 downto 0);
+  pattern (15 downto 8) <= not slave_i.adr(7 downto 0);
+  pattern (23 downto 16)  <= slave_i.adr(7 downto 0);
+  pattern (31 downto 24) <= not slave_i.adr(7 downto 0);
  process (clk_sys_i)
    procedure pattern_write