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Simple VME FMC Carrier SVEC
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Simple VME FMC Carrier SVEC
Commits
00515ebb
Commit
00515ebb
authored
Jun 04, 2020
by
Tristan Gingold
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vmecore_test: modify tb for 2esst
parent
56654022
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4 changed files
with
27 additions
and
12 deletions
+27
-12
tb_vmecore_test.vhd
hdl/testbench/tb_vmecore_test/tb_vmecore_test.vhd
+10
-1
Manifest.py
hdl/top/vmecore_test/Manifest.py
+2
-1
svec_vmecore_test_top.vhd
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
+11
-8
vmecore_test.vhd
hdl/top/vmecore_test/vmecore_test.vhd
+4
-2
No files found.
hdl/testbench/tb_vmecore_test/tb_vmecore_test.vhd
View file @
00515ebb
...
...
@@ -88,6 +88,8 @@ begin
variable
d8
:
byte_t
;
variable
d16
:
word_t
;
variable
d32
:
lword_t
;
variable
arr64
:
qword_array_t
(
31
downto
0
);
begin
-- Each scenario starts with a reset.
-- VME reset
...
...
@@ -109,7 +111,7 @@ begin
-- Set ADER
write8_conf
(
vme_in
,
vme_out
,
vme_timeout
,
x"7_ff77"
,
x"10"
);
write8_conf
(
vme_in
,
vme_out
,
vme_timeout
,
x"7_ff7f"
,
c_AM_
A24
&
"00"
);
write8_conf
(
vme_in
,
vme_out
,
vme_timeout
,
x"7_ff7f"
,
c_AM_
2EVME_6U
&
"00"
);
read8_conf
(
vme_in
,
vme_out
,
vme_timeout
,
x"7_ff77"
,
d8
);
assert
d8
=
x"10"
report
"bad ADER0 value"
severity
error
;
...
...
@@ -122,6 +124,13 @@ begin
severity
error
;
report
"read data: "
&
hex
(
d8
);
-- 2eSST transfer at 267
read64_2esst
(
vme_in
,
vme_out
,
vme_timeout
,
x"00_10_00_00"
,
c_XAM_A32_2ESST
,
"0001"
,
arr64
);
for
i
in
arr64
'range
loop
write
(
output
,
hex
(
arr64
(
i
))
&
LF
);
end
loop
;
-- dump_CR (vme_in, vme_out, vme_timeout);
report
"Dump patterns"
;
...
...
hdl/top/vmecore_test/Manifest.py
View file @
00515ebb
...
...
@@ -5,5 +5,6 @@ files = [
]
modules
=
{
'git'
:
[
"git://ohwr.org/project/general-cores.git"
,
"git://ohwr.org/project/vme64x-core.git"
]
"git://ohwr.org/project/vme64x-core.git"
],
'system'
:
[
'xilinx'
,
'vhdl'
],
}
hdl/top/vmecore_test/svec_vmecore_test_top.vhd
View file @
00515ebb
...
...
@@ -7,7 +7,7 @@
-- Author(s) : Tristan Gingold <tristan.gingold@cern.ch>
-- Company : CERN (BE-CO-HT)
-- Created : 2017-09-19
-- Last update: 2020-0
5-29
-- Last update: 2020-0
6-04
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for the test design .
...
...
@@ -283,12 +283,12 @@ begin -- architecture top
process
begin
clk_sys
<=
'0'
;
wait
for
8
ns
;
wait
for
4
ns
;
clk_sys
<=
'1'
;
wait
for
8
ns
;
wait
for
4
ns
;
end
process
;
local_reset_n
<=
'0'
,
'1'
after
16
ns
;
local_reset_n
<=
'0'
,
'1'
after
8
ns
;
end
generate
;
-----------------------------------------------------------------------------
...
...
@@ -301,15 +301,18 @@ begin -- architecture top
inst_vme_core
:
xvme64x_core
generic
map
(
g_CLOCK_PERIOD
=>
8
,
g_DECODE_AM
=>
True
,
g_USER_CSR_EXT
=>
False
,
g_CLOCK_PERIOD
=>
8
,
g_VME_2e
=>
True
,
g_DECODE_AM
=>
False
,
g_USER_CSR_EXT
=>
False
,
g_wb_granularity
=>
WORD
,
g_WB_MODE
=>
PIPELINED
,
g_MANUFACTURER_ID
=>
c_CERN_ID
,
g_BOARD_ID
=>
c_SVEC_ID
,
g_REVISION_ID
=>
c_SVEC_REVISION_ID
,
g_PROGRAM_ID
=>
c_SVEC_PROGRAM_ID
)
g_PROGRAM_ID
=>
c_SVEC_PROGRAM_ID
,
g_DECODER
=>
c_vme64x_decoders_2e_default
)
port
map
(
clk_i
=>
clk_sys
,
rst_n_i
=>
local_reset_n
,
...
...
hdl/top/vmecore_test/vmecore_test.vhd
View file @
00515ebb
...
...
@@ -75,8 +75,10 @@ architecture rtl of vmecore_test is
begin
-- Pattern of the pattern ram.
pattern
(
31
downto
16
)
<=
not
slave_i
.
adr
(
15
downto
0
);
pattern
(
15
downto
0
)
<=
slave_i
.
adr
(
15
downto
0
);
pattern
(
7
downto
0
)
<=
slave_i
.
adr
(
7
downto
0
);
pattern
(
15
downto
8
)
<=
not
slave_i
.
adr
(
7
downto
0
);
pattern
(
23
downto
16
)
<=
slave_i
.
adr
(
7
downto
0
);
pattern
(
31
downto
24
)
<=
not
slave_i
.
adr
(
7
downto
0
);
process
(
clk_sys_i
)
procedure
pattern_write
...
...
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