SPEC7 Specification gathering
This wiki page describes different discussion points for the specification of the SPEC7.
Aim and Use cases
NIKHEF/JRP, CERN: as high-precision PCIe and stand-alone White Rabbit design
* Aim: the JRP want to disseminate UTC from metrology partners to European research institutes and industry partners with a target frequency instability of 1e-13 over 100 sec.
* Users will be first: research institutes, metrology institutes. Later: high performance users, telecom, ....
- All users profit from an inherent high performance, relatively cheap, design without the bother of buying an expensive stable external oscillator that the metrology users need.
* Other possible user for 1 GSPS ADC cards requiring HPC FMC
* Quantity: 100 in 5 years for metrology
* Priority
- optimise for performance
- (cost)
CERN: as SPEC replacement
* Aim: smooth replacement of existing SPEC (cheap and simple)
* Used by
-
DIO
-
ADC100M
-
TDC
-
Fine Delay
-
WorldFIP master
-
and other FMC mezzanines.
* Users
-
CERN
-
Many current SPEC users have their in-house designed FMC mezzanines. Should provide a compatible alternative.
* Quantity: 500 cards expected in 5 years
* Priority
- cost
- performance
Under discussion
FPGA family
- Kintex 7
-
FBG676 package allows 70T, 160T, 325T and 410T sizes on the same footprint.
- XC7K160T-2FBG676C (~260 Euro) (default type?)
- XC7K70T-2FBG676C: (~180 Euro)
- XC6SLX45T-3FGG484C on SPEC: (~84 Euro without STEP pricing)
- 8 GTX Transceivers max (4 used for PCIe, 2 for SFP, only 2
left for FMC).
- A 70T in FBG484 package cannot be used as has only 4 GTX Transceivers (No need to check if can be used on footprint of FBG676)
- Smallest Kintex7 with 16 GTX transceivers: XC7K325T-2FBG900C (~1100 Euro)
-
- Artix-7
- only if LPC
- low price
FMC HPC or LPC
- use case for HPC?
- HPC would be interesting for some applications like high-speed ADCs where you need to go massively parallel to avoid too high bandwidth requirements on the data lines.
- Test and debug using a Xilinx FMC-XM105 debug card
- For footprint compatible FPGA's; if a larger FPGA is mounted then IO pins are available as much as possible. For a smaller FPGA at least the LPC pins on the HCP connector will be available.
- HPC: need new tests tools for production test
Price idea:
- LPC ($12.68/connector), n layers, Kintex 70T FPGA
- HPC ($20.40/connector), n+2 layers, Kintex 325T FPGA -> 325T? Probably a 160T is large enough for most applications (160T should be default?)
- use case for LPC
- Existing FMC mezzanines: DIO, ADC100M, TDC, Fine Delay, masterFIP, in-house designs of current SPEC users.
FMC connector
- Vadj
- programmable IC, or just a few values and selection with jumpers?
SFP
- Double SFP for allowing redundant links?
- not possible to fit on PCIe front-panel
- Image of double FMC cage with LEDs
- Image of double decker FMC cage with LEDs":https://media.rs-online.com/t_large/R7871705-01.jpg
- Could maybe fit if would make 2-slot card when optional heatsink/fan solution that extends it into the neighboring slot. Double decker would not work here though.
- Compact SFP (CSFP)?
- Has two bidi standard SFPs in one SFP module
- CSFPs have a little different pinout comparing to the standard SFPs. Same mechanics as standard SFP (Wikipedia).
- Difference between SFP, bidi SFP and CSFP
- CSFP Delta CSFP-33-A4K1DBT (pinout on page 4)
- Check if use of CSFP would limit the use of standard SFP modules
RAM
- SO-DIMM socket for RAM
- Or directly assembled RAM IC?
- Use case: data memory for storing data coming from ADC card (e.g. fmc-adc-100m14b4cha
FLASH storage
- MicroSD slot?
- eMMC ?
USB
- mini USB connector (as on SPEC)
- micro USB-OTG (so it can act as host and as slave). But then we should rename the card to SPUEC or SUPEC (U for USB). Perhaps this is a crazy idea, but it is nice to think that users can plug'n'play the SPUEC/SUPEC on their laptop :) (FV)
- The current mini-USB can serve two UARTs over the same single mini-USB connector if we use a CP2105 - Dual UART bridge. Quite handy if you have a WRPC gui and other logic in your FPGA.
PCB
- 10 layer PCB so that layout can be optimised for low-jitter oscillator
Additional connectors
- High-speed connector for PPS in/out, 10MHz in, tx-abscal, rx-abscal, refclock. 6 signals to be transferred in a differential way Samtec Bulls-Eye connector (just a land pattern for 22 signals on the PCB).
Other remarks from NIKHEF
Some extra's that were on our list:
- We need high performance timing-IO signals (including absolute calibration signals) on (accessible) connectors. The current DIO is really bad for timing. We (Guido) should look into this. A possible candidate is a Samtec Bulls-Eye which is just a land pattern on your PCB. But we should study this since a Bulls-Eye is the perfect phase plane reference but the phase plane will not be very accessible from the outside world (i.e. on the PCI bracket).
- Timing signals should be re-clocked with high speed FFs outside the FPGA. I remember that this was an issue that you CERN guys also proposed earlier.
- We need to think of some digital interface (including connectors) to close an external PLL loop using an external high performance oscillator. Ideas are still vague at this moment but the interface as such should already be on the list.
Accepted
SATA
- Keep same SATA connectors as on SPEC.
- Is a connector specifically for internal use (i.e., not panel-mounted).
- Planned to be used on SPEC for daisy-chaining triggers between SPECs with FMC-ADCs with modified gateware.
- May be used as well for digital interface for external PLL loop
Rejected
22 January 2018