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SPEC7
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SPEC7
Commits
f11846a0
Commit
f11846a0
authored
Sep 07, 2020
by
Pascal Bos
Committed by
Peter Jansweijer
Sep 22, 2020
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added PS in ref design, adjusted BAR addresses.
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98bb01ed
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3 changed files
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4 deletions
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-4
proj_file_list.txt
hdl/spec7_ref_design/syn/proj_file_list.txt
+1
-2
proj_file_list.txt
hdl/spec7_write_design/syn/proj_file_list.txt
+0
-1
wr-cores
hdl/wr-cores
+1
-1
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hdl/spec7_ref_design/syn/proj_file_list.txt
View file @
f11846a0
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@@ -72,7 +72,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
...
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@@ -187,7 +186,7 @@
# bmm not supported by hdlmake? Need to add it manually...
../../wr-cores/platform/xilinx/wr_pcie/
P
cie.tcl
../../wr-cores/platform/xilinx/wr_pcie/
processing_system_p
cie.tcl
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
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hdl/spec7_write_design/syn/proj_file_list.txt
View file @
f11846a0
...
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@@ -73,7 +73,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
...
...
wr-cores
@
276cf6db
Subproject commit
ae69ccba78959ac817b637d83944fb28db31946e
Subproject commit
276cf6db4221e52a91b6d855e417d4c2c9508a1b
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