Commit f11846a0 authored by Pascal Bos's avatar Pascal Bos Committed by Peter Jansweijer

added PS in ref design, adjusted BAR addresses.

parent 98bb01ed
......@@ -72,7 +72,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
......@@ -187,7 +186,7 @@
# bmm not supported by hdlmake? Need to add it manually...
../../wr-cores/platform/xilinx/wr_pcie/Pcie.tcl
../../wr-cores/platform/xilinx/wr_pcie/processing_system_pcie.tcl
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
......
......@@ -73,7 +73,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
......
Subproject commit ae69ccba78959ac817b637d83944fb28db31946e
Subproject commit 276cf6db4221e52a91b6d855e417d4c2c9508a1b
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