Add even_odd detector. Detect the alignment of 10MHz and 125MHz at the first…

Add even_odd detector. Detect the alignment of 10MHz and 125MHz at the first 10MHz edge after PPS-in. Software reset the LTC6950 when misaligned.

Add even_odd detector. Detect the alignment of 10MHz and 125MHz at the first…
Add even_odd detector. Detect the alignment of 10MHz and 125MHz at the first 10MHz edge after PPS-in. Software reset the LTC6950 when misaligned.
98bb01ed · Peter Jansweijer · 13d56ae4 · 98bb01ed · 98bb01ed · 98bb01ed
Commit 98bb01ed authored Aug 19, 2020 by Peter Jansweijer
6 changed files
--- a/hdl/spec7_ref_design/sim/VCom_spec7_wr_ref_top_Functional.tcl
+++ b/hdl/spec7_ref_design/sim/VCom_spec7_wr_ref_top_Functional.tcl
@@ -3,6 +3,7 @@
 # From directory vcom -explicit -93 -work work ../../wr-cores/syn/spec7_ref_design
 # hdlmake list-files > proj_file_list.txt

+#vcom -explicit -93 -work work ../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
@@ -61,6 +62,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_p
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
+vcom -explicit -93 -work work ../../wr-cores/board/spec7/even_odd_det.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd

--- a/hdl/spec7_ref_design/syn/proj_file_list.txt
+++ b/hdl/spec7_ref_design/syn/proj_file_list.txt
@@ -60,6 +60,7 @@
 ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
+../../wr-cores/board/spec7/even_odd_det.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd

--- a/hdl/spec7_write_design/sim/VCom_spec7_write_top_Functional.tcl
+++ b/hdl/spec7_write_design/sim/VCom_spec7_write_top_Functional.tcl
@@ -63,6 +63,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_p
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
+vcom -explicit -93 -work work ../../wr-cores/board/spec7/even_odd_det.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd

--- a/hdl/spec7_write_design/sim/VSim_Functional.tcl
+++ b/hdl/spec7_write_design/sim/VSim_Functional.tcl
@@ -37,6 +37,7 @@ do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072

 vsim -voptargs="+acc=lnprv" \
  -G/spec7_write_top/g_simulation=$g_simulation \
+  -G/spec7_write_top/g_use_pps_in_single=False \
  -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram \
  -t ps -L unisim -lib work work.spec7_write_top


--- a/hdl/spec7_write_design/syn/proj_file_list.txt
+++ b/hdl/spec7_write_design/syn/proj_file_list.txt
@@ -61,6 +61,7 @@
 ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
+../../wr-cores/board/spec7/even_odd_det.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_checksum.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_eth_rx.vhd
 ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_internals_pkg.vhd

--- a/wr-cores @ ae69ccba
+++ b/wr-cores @ ae69ccba
-Subproject commit 0d9c9faed5f8e586c16db6f86cd2353d9933ba20
+Subproject commit ae69ccba78959ac817b637d83944fb28db31946e