Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
S
SPEC7
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
5
Issues
5
List
Board
Labels
Milestones
Merge Requests
0
Merge Requests
0
CI / CD
CI / CD
Pipelines
Jobs
Schedules
Charts
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Jobs
Commits
Issue Boards
Open sidebar
Projects
SPEC7
Commits
c2053a22
Commit
c2053a22
authored
Jun 27, 2021
by
Javier D. Garcia-Lasheras
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
ps7_uart_1 connected to XDMA AXI Lite and XDMA AXI Bypass access to PS DDR
parent
7ab6647e
Expand all
Hide whitespace changes
Inline
Side-by-side
Showing
1 changed file
with
243 additions
and
70 deletions
+243
-70
processing_system_pcie.bd
hdl/ip/processing_system_pcie.bd
+243
-70
No files found.
hdl/ip/processing_system_pcie.bd
View file @
c2053a22
This diff is collapsed.
Click to expand it.
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment