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SPEC7
Commit 7ab6647e authored by Peter Jansweijer's avatar Peter Jansweijer
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remove even_odd_det, add bufg for clk_ref62m5

parent a0cbb7b4
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hdl/board/xwrc_board_spec7.vhd
View file @ 7ab6647e
......@@ -282,13 +282,11 @@ architecture struct of xwrc_board_spec7 is
signal clk_dmtd : std_logic := '0';
-- PLLs, clocks
signal clk_ref_div2 : std_logic := '0';
signal clk_ref_62m5 : std_logic := '0';
signal clk_ref_sync : std_logic := '0';
signal sync_enable : std_logic;
signal even_odd_n : std_logic;
signal sync_polarity : std_logic;
signal sync_done : std_logic;
signal sync_clk_ref_62m5 : std_logic;
signal clk_ref_locked : std_logic;
signal clk_sys_62m5 : std_logic;
signal clk_10m_ext : std_logic;
......@@ -345,20 +343,6 @@ architecture struct of xwrc_board_spec7 is
constant c_num_gpio_pins : integer := 17;
signal gpio_out, gpio_in, gpio_oen : std_logic_vector(c_num_gpio_pins-1 downto 0);
component even_odd_det is
port (
rst_n_i : in std_logic;
clk_ref_i : in std_logic;
clk_10m_ext_i : in std_logic;
clk_sys_62m5_i : in std_logic;
pps_i : in std_logic;
even_odd_n_o : out std_logic;
enable_sync_i : in std_logic;
sync_done_o : out std_logic;
sync_o : out std_logic
);
end component even_odd_det;
begin -- architecture struct
-----------------------------------------------------------------------------
......@@ -405,18 +389,6 @@ begin -- architecture struct
I => clk_125m_gtx_buf,
O => clk_ref_125m);
cmp_even_odd_det: even_odd_det
port map (
rst_n_i => areset_n_i,
clk_ref_i => clk_ref_125m,
clk_10m_ext_i => clk_10m_ext_i,
clk_sys_62m5_i => clk_sys_62m5,
pps_i => pps_ext_i,
even_odd_n_o => even_odd_n,
enable_sync_i => sync_enable,
sync_done_o => sync_done,
sync_o => sync_clk_ref_62m5);
---------------------------------------------------------------------------
-- PLL sync signal synchronizes the LTC6950 but it waits for the proper
-- 10 MHz cycle before re-enabling the clock. This means that it shifts
......@@ -435,14 +407,15 @@ begin -- architecture struct
process(clk_ref_125m)
begin
if rising_edge(clk_ref_125m) then
if sync_clk_ref_62m5 = '1' then
clk_ref_62m5 <= '0';
else
clk_ref_62m5 <= not clk_ref_62m5;
end if;
clk_ref_div2 <= not clk_ref_div2;
end if;
end process;
cmp_clk_ref62m5_buf : BUFG
port map (
O => clk_ref_62m5,
I => clk_ref_div2);
---------------------------------------------------------------------------
-- The PLL on the SPEC7 needs to be initialized before it outputs clk_125m_gtx_p/n_i.
-- Avoid a deadlock. The clk_dmtd is always present and is first used to bring alive
......@@ -470,7 +443,7 @@ begin -- architecture struct
port map(
clk_gtx_i => clk_125m_gtx_buf,
clk_dmtd_i => clk_dmtd,
clk_ref_i => clk_ref_125m,
clk_ref_i => clk_ref_62m5,
tx_data_i => phy16_from_wrc.tx_data,
tx_k_i => phy16_from_wrc.tx_k,
tx_disparity_o => phy16_to_wrc.tx_disparity,
......@@ -808,7 +781,6 @@ begin -- architecture struct
pll_reset_n_o <= gpio_out(4);
gpio_in(5) <= pll_lock_i;
gpio_in(6) <= pll_status_i;
sync_enable <= gpio_out(7); -- trigger PLL sync sequence
-- External clock multiplexers
pll_wr_mode_o <= gpio_out(9 downto 8);
......@@ -821,8 +793,8 @@ begin -- architecture struct
eeprom_sda <= '0' when (gpio_out(12) = '0') else 'Z';
gpio_in(12) <= eeprom_sda;
gpio_in(13) <= even_odd_n; -- 10MHz/1PPS phase w.r.t. clk_ref_125m
gpio_in(14) <= sync_done;
gpio_in(13) <= '0';
gpio_in(14) <= '0';
-- AUXiliary I2C tri-states
aux_scl <= '0' when (gpio_out(15) = '0') else 'Z';
......
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ 7ab6647e
......@@ -23,7 +23,7 @@ create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_port
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_dmtd_reg/Q]
# Set divide by 2 property for generated clk_ref (former platform xilinx: g_phy_lpcalib = TRUE)
create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_ref_62m5_reg/Q]
create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_clk_ref62m5_buf/O]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
......
wr-cores @ 06448c06
Subproject commit 909a40763bfe58d23826e8f5bea70935e3682629
Subproject commit 06448c066a65d2221c9eefeed22d45b300a0dc25
sw/precompiled/wrps-sw-v5_spec7/GitLog.txt
View file @ 7ab6647e
wrpc-sw.git: a96ebd1c394c56c7d6321f9b5a2baabac0bff47e (HEAD -> peter_210324_spec7_wrpc-v5, origin/peter_210324_spec7_wrpc-v5)
wrpc-sw.git: 09798d30989942dcb501abd0520dc0aa82311ecc (HEAD -> peter_210324_spec7_wrpc-v5, origin/peter_210324_spec7_wrpc-v5)
ppsi.git: 196097cd54f7656e668a601757e4f98a5a625c60 (HEAD -> peter_direct_dmtd_v5, origin/peter_direct_dmtd_v5)
sw/precompiled/wrps-sw-v5_spec7/wrc.bram
View file @ 7ab6647e
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sw/precompiled/wrps-sw-v5_spec7/wrc.mif
View file @ 7ab6647e
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