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Commit 8d25772f authored by Peter Jansweijer's avatar Peter Jansweijer
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remove unused spec7_golden_image. Tandem PROM stage 1: spec7_tandem_boot, stage 2: spec7_ref_design

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hdl/syn/spec7_golden_image/.gitignore deleted 100644 → 0
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/syn/spec7_golden_image/Manifest.py deleted 100644 → 0
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board = "spec7"
target = "xilinx"
action = "synthesis"
syn_device = "xc7z035"
syn_grade = "-1"
syn_package = "fbg676"
syn_top = "spec7_golden_image_top"
syn_project = "spec7_golden_image_top.xpr"
syn_tool = "vivado"
modules = { "local" : "../../top/spec7_golden_image/"}
\ No newline at end of file
hdl/syn/spec7_golden_image/README.TXT deleted 100644 → 0
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Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/syn/spec7_golden_image/do_vivado.cmd deleted 100644 → 0
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/syn/spec7_golden_image/do_vivado_gen_bin_mcs.cmd deleted 100644 → 0
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rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/syn/spec7_golden_image/do_vivado_prog.cmd deleted 100644 → 0
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/syn/spec7_golden_image/do_vivado_tcl.cmd deleted 100644 → 0
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/syn/spec7_golden_image/proj_file_list.txt deleted 100644 → 0
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# From directory ....spec7/hdl/syn/spec7_golden_image
# hdlmake list-files > proj_file_list.txt
../../top/spec7_golden_image/spec7_golden_image_top.vhd
../../top/spec7_golden_image/spec7_golden_image_top.xdc
# bmm not supported by hdlmake? Need to add it manually...
../../ip/processing_system_pcie.bd
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
hdl/syn/spec7_golden_image/proj_properties.tcl deleted 100644 → 0
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
set spec7_design spec7_golden_image_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
set proj_name spec7_golden_image_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design"
}
hdl/top/spec7_golden_image/Manifest.py deleted 100644 → 0
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files = [
"spec7_golden_image_top.vhd",
"spec7_golden_image_top.xdc",
]
hdl/top/spec7_golden_image/spec7_golden_image_top.vhd deleted 100644 → 0
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-------------------------------------------------------------------------------
-- Title : Golden Image for SPEC7
-- : based on ZYNQ Z030/Z035/Z045
-- Project : WR PTP Core and EMPIR 17IND14 WRITE
-- URL : http://www.ohwr.org/projects/wr-cores/wiki/Wrpc_core
-- : http://empir.npl.co.uk/write/
-------------------------------------------------------------------------------
-- File : spec7_golden_image_top.vhd
-- Author(s) : Peter Jansweijer <peterj@nikhef.nl>, Mamta Ramendra Shukla <mamta.ramendra.shukla@cern.ch>
-- Company : Nikhef, CERN
-- Created : 2021-06-15
-- Last update: 2021-06-15
-- Standard : VHDL'93
-------------------------------------------------------------------------------
-- Description: Top-level file for Golden Image for SPEC7.
-- See also EMPIR 17IND14 WRITE Project (http://empir.npl.co.uk/write/)
--
-- This Golden Image is a bare minimal PCIe core that connects to the Zynq
-- Processing System (PS).
-- The design serves as a first bootstrap. Once loaded, it enables further
-- FPGA Programmable Logic (PL) configuration via PCIe, Ethernet or SD card.
--
-------------------------------------------------------------------------------
-- Copyright (c) 2021 Nikhef, CERN
-------------------------------------------------------------------------------
-- GNU LESSER GENERAL PUBLIC LICENSE
--
-- This source file is free software; you can redistribute it
-- and/or modify it under the terms of the GNU Lesser General
-- Public License as published by the Free Software Foundation;
-- either version 2.1 of the License, or (at your option) any
-- later version.
--
-- This source is distributed in the hope that it will be
-- useful, but WITHOUT ANY WARRANTY; without even the implied
-- warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
-- PURPOSE. See the GNU Lesser General Public License for more
-- details.
--
-- You should have received a copy of the GNU Lesser General
-- Public License along with this source; if not, download it
-- from http://www.gnu.org/licenses/lgpl-2.1.html
--
-------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
--library work;
--use work.gencores_pkg.all;
--use work.wishbone_pkg.all;
--use work.wr_board_pkg.all;
--use work.wr_spec7_pkg.all;
--use work.axi4_pkg.all;
library unisim;
use unisim.vcomponents.all;
entity spec7_golden_image_top is
generic (
g_design : string := "spec7_golden_image_top"
);
port (
---------------------------------------------------------------------------`
-- Clocks/resets
---------------------------------------------------------------------------
-- Local oscillators
clk_125m_dmtd_p_i : in std_logic; -- 124.992 MHz PLL reference
clk_125m_dmtd_n_i : in std_logic;
clk_125m_gtx_n_i : in std_logic; -- 125 MHz GTX reference (either from WR
clk_125m_gtx_p_i : in std_logic; -- Oscillators of stable external oscillator)
---------------------------------------------------------------------------
-- SPI interface to DACs
---------------------------------------------------------------------------
dac_refclk_cs_n_o : out std_logic;
dac_refclk_sclk_o : out std_logic;
dac_refclk_din_o : out std_logic;
dac_dmtd_cs_n_o : out std_logic;
dac_dmtd_sclk_o : out std_logic;
dac_dmtd_din_o : out std_logic;
-------------------------------------------------------------------------------
-- PLL Control signals
-------------------------------------------------------------------------------
pll_status_i : in std_logic;
pll_mosi_o : out std_logic;
pll_miso_i : in std_logic;
pll_sck_o : out std_logic;
pll_cs_n_o : out std_logic;
pll_sync_o : out std_logic;
pll_lock_i : in std_logic;
pll_wr_mode_o : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- SFP I/O for transceiver
---------------------------------------------------------------------------
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic;
---------------------------------------------------------------------------
-- UART
---------------------------------------------------------------------------
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
---------------------------------------------------------------------------
-- No Flash memory SPI interface
---------------------------------------------------------------------------
---------------------------------------------------------------------------
-- Miscellanous SPEC7 pins
---------------------------------------------------------------------------
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
reset_n_i : in std_logic;
suicide_n_o : out std_logic;
wdog_n_o : out std_logic;
-- blink 1-PPS.
led_pps_o : out std_logic;
---------------------------------------------------------------------------
-- EEPROM interface
---------------------------------------------------------------------------
-- I2C interface for accessing
-- EEPROM (24AA64 Addr 1010.000x) and
-- Unique ID (24AA025EU48, Addr 1010.001x).
scl_b : inout std_logic;
sda_b : inout std_logic;
---------------------------------------------------------------------------
-- PCIe interface
---------------------------------------------------------------------------
pci_clk_n : in std_logic;
pci_clk_p : in std_logic;
perst_n : in std_logic;
rxn : in std_logic_vector(1 downto 0);
rxp : in std_logic_vector(1 downto 0);
txn : out std_logic_vector(1 downto 0);
txp : out std_logic_vector(1 downto 0);
---------------------------------------------------------------------------
-- Processing System interface
---------------------------------------------------------------------------
DDR_addr : inout std_logic_vector ( 14 downto 0 );
DDR_ba : inout std_logic_vector ( 2 downto 0 );
DDR_cas_n : inout std_logic;
DDR_ck_n : inout std_logic;
DDR_ck_p : inout std_logic;
DDR_cke : inout std_logic;
DDR_cs_n : inout std_logic;
DDR_dm : inout std_logic_vector ( 3 downto 0 );
DDR_dq : inout std_logic_vector ( 31 downto 0 );
DDR_dqs_n : inout std_logic_vector ( 3 downto 0 );
DDR_dqs_p : inout std_logic_vector ( 3 downto 0 );
DDR_odt : inout std_logic;
DDR_ras_n : inout std_logic;
DDR_reset_n : inout std_logic;
DDR_we_n : inout std_logic;
FIXED_IO_ddr_vrn : inout std_logic;
FIXED_IO_ddr_vrp : inout std_logic;
FIXED_IO_mio : inout std_logic_vector ( 53 downto 0 );
FIXED_IO_ps_clk : inout std_logic;
FIXED_IO_ps_porb : inout std_logic;
FIXED_IO_ps_srstb : inout std_logic;
------------------------------------------------------------------------------
-- Digital I/O Bulls-Eye connector pins
------------------------------------------------------------------------------
-- A09,A10 ABSCAL_TXTS (Bank 35 C17,C16)
be_abscal_txts_p_o : out std_logic;
be_abscal_txts_n_o : out std_logic;
-- A01,A02 PPS_out (Bank 35 G16,G15)
be_pps_p_o : out std_logic;
be_pps_n_o : out std_logic;
-- B01,B02 PPS_in (Bank 35 G14,F14)
be_pps_p_i : in std_logic;
be_pps_n_i : in std_logic;
-- A03,A04 10MHz_out (Bank 35 F15,E15)
be_clk_10m_p_o : out std_logic;
be_clk_10m_n_o : out std_logic;
-- B03,B04 10MHZ_in (Bank 13 AF24,AF25)
be_clk_10m_p_i : in std_logic;
be_clk_10m_n_i : in std_logic;
-- B11 Single ended PPS_in (Bank 13 AE23)
be_pps_i : in std_logic;
---------------------------------------------------------------------------
-- Digital I/O FMC connector pins
---------------------------------------------------------------------------
fmc_prsnt_m2c_l : in std_logic;
fmc_sda : inout std_logic;
fmc_scl : inout std_logic;
fmc_clk0_m2c_p : in std_logic;
fmc_clk0_m2c_n : in std_logic;
fmc_clk1_m2c_p : in std_logic;
fmc_clk1_m2c_n : in std_logic;
fmc_la00_cc_p : inout std_logic;
fmc_la00_cc_n : inout std_logic;
fmc_la01_cc_p : inout std_logic;
fmc_la01_cc_n : inout std_logic;
fmc_la02_p : inout std_logic;
fmc_la02_n : inout std_logic;
fmc_la03_p : inout std_logic;
fmc_la03_n : inout std_logic;
fmc_la04_p : inout std_logic;
fmc_la04_n : inout std_logic;
fmc_la05_p : inout std_logic;
fmc_la05_n : inout std_logic;
fmc_la06_p : inout std_logic;
fmc_la06_n : inout std_logic;
fmc_la07_p : inout std_logic;
fmc_la07_n : inout std_logic;
fmc_la08_p : inout std_logic;
fmc_la08_n : inout std_logic;
fmc_la09_p : inout std_logic;
fmc_la09_n : inout std_logic;
fmc_la10_p : inout std_logic;
fmc_la10_n : inout std_logic;
fmc_la11_p : inout std_logic;
fmc_la11_n : inout std_logic;
fmc_la12_p : inout std_logic;
fmc_la12_n : inout std_logic;
fmc_la13_p : inout std_logic;
fmc_la13_n : inout std_logic;
fmc_la14_p : inout std_logic;
fmc_la14_n : inout std_logic;
fmc_la15_p : inout std_logic;
fmc_la15_n : inout std_logic;
fmc_la16_p : inout std_logic;
fmc_la16_n : inout std_logic;
fmc_la17_cc_p : inout std_logic;
fmc_la17_cc_n : inout std_logic;
fmc_la18_cc_p : inout std_logic;
fmc_la18_cc_n : inout std_logic;
fmc_la19_p : inout std_logic;
fmc_la19_n : inout std_logic;
fmc_la20_p : inout std_logic;
fmc_la20_n : inout std_logic;
fmc_la21_p : inout std_logic;
fmc_la21_n : inout std_logic;
fmc_la22_p : inout std_logic;
fmc_la22_n : inout std_logic;
fmc_la23_p : inout std_logic;
fmc_la23_n : inout std_logic;
fmc_la24_p : inout std_logic;
fmc_la24_n : inout std_logic;
fmc_la25_p : inout std_logic;
fmc_la25_n : inout std_logic;
fmc_la26_p : inout std_logic;
fmc_la26_n : inout std_logic;
fmc_la27_p : inout std_logic;
fmc_la27_n : inout std_logic;
fmc_la28_p : inout std_logic;
fmc_la28_n : inout std_logic;
fmc_la29_p : inout std_logic;
fmc_la29_n : inout std_logic;
fmc_la30_p : inout std_logic;
fmc_la30_n : inout std_logic;
fmc_la31_p : inout std_logic;
fmc_la31_n : inout std_logic;
fmc_la32_p : inout std_logic;
fmc_la32_n : inout std_logic;
fmc_la33_p : inout std_logic;
fmc_la33_n : inout std_logic;
fmc_gbtclk0_m2c_p : in std_logic;
fmc_gbtclk0_m2c_n : in std_logic
-- fmc_dp0_c2m_p : out std_logic;
-- fmc_dp0_c2m_n : out std_logic;
-- fmc_dp0_m2c_p : in std_logic;
-- fmc_dp0_m2c_n : in std_logic;
-- fmc_dp1_c2m_p : out std_logic;
-- fmc_dp1_c2m_n : out std_logic;
-- fmc_dp1_m2c_p : in std_logic;
-- fmc_dp1_m2c_n : in std_logic;
-- fmc_dp2_c2m_p : out std_logic;
-- fmc_dp2_c2m_n : out std_logic;
-- fmc_dp2_m2c_p : in std_logic;
-- fmc_dp2_m2c_n : in std_logic;
-- fmc_dp3_c2m_p : out std_logic;
-- fmc_dp3_c2m_n : out std_logic;
-- fmc_dp3_m2c_p : in std_logic;
-- fmc_dp3_m2c_n : in std_logic
);
end entity spec7_golden_image_top;
architecture top of spec7_golden_image_top is
-- -----------------------------------------------------------------------------
-- -- Constants
-- -----------------------------------------------------------------------------
--
-- -- Number of masters on the wishbone crossbar
-- constant c_NUM_WB_MASTERS : integer := 2;
--
-- -- Number of slaves on the primary wishbone crossbar
-- constant c_NUM_WB_SLAVES : integer := 1;
--
-- -- Primary Wishbone master(s) offsets
-- constant c_WB_MASTER_PCIE : integer := 0;
-- constant c_WB_MASTER_ETHBONE : integer := 1;
--
-- -- Primary Wishbone slave(s) offsets
-- constant c_WB_SLAVE_WRC : integer := 0;
--
-- -- sdb header address on primary crossbar
-- constant c_SDB_ADDRESS : t_wishbone_address := x"00040000";
--
-- -- f_xwb_bridge_manual_sdb(size, sdb_addr)
-- -- Note: sdb_addr is the sdb records address relative to the bridge base address
-- constant c_wrc_bridge_sdb : t_sdb_bridge :=
-- f_xwb_bridge_manual_sdb(x"0003ffff", x"00030000");
--
-- -- Primary wishbone crossbar layout
-- constant c_WB_LAYOUT : t_sdb_record_array(c_NUM_WB_SLAVES - 1 downto 0) := (
-- c_WB_SLAVE_WRC => f_sdb_embed_bridge(c_wrc_bridge_sdb, x"00000000"));
-----------------------------------------------------------------------------
-- Signals
-----------------------------------------------------------------------------
-- clock and reset
signal clk_sys_62m5 : std_logic;
signal clk_125m_dmtd_buf : std_logic;
signal clk_sys_125m : std_logic;
-- signal rst_sys_62m5_n : std_logic;
-- signal rst_ref_62m5_n : std_logic;
-- signal clk_ref_62m5 : std_logic;
-- signal clk_ref_div2 : std_logic;
-- signal clk_10m_out : std_logic;
-- signal clk_500m : std_logic;
-- signal clk_ext_10m : std_logic;
--
-- -- DAC signals for reference clock
-- signal dac_refclk_sclk_int_o : std_logic;
-- signal dac_refclk_din_int_o : std_logic;
-- signal dac_refclk_cs_n_int_o : std_logic;
--
-- -- SFP
-- signal sfp_sda_in : std_logic;
-- signal sfp_sda_out : std_logic;
-- signal sfp_scl_in : std_logic;
-- signal sfp_scl_out : std_logic;
--
-- -- LEDs and GPIO
-- signal wrc_abscal_txts_out : std_logic;
-- signal wrc_abscal_rxts_out : std_logic;
-- signal wrc_pps_out : std_logic;
-- signal wrc_pps_led : std_logic;
-- signal pps_led_ext : std_logic;
-- signal svec_led : std_logic_vector(15 downto 0);
-- signal wrc_pps_in : std_logic;
--
-- --Axi4
-- signal m_axil_i : t_axi4_lite_master_in_32;
-- signal m_axil_o : t_axi4_lite_master_out_32;
-- signal araddr : std_logic_vector(31 downto 0);
-- signal awaddr : std_logic_vector(31 downto 0);
--
-- --Wishbone
-- signal wb_master_i : t_wishbone_master_in;
-- signal wb_master_o : t_wishbone_master_out;
--PCIe
signal pci_clk : std_logic;
-- component pll_62m5_500m is
-- port (
-- areset_n_i : in std_logic;
-- clk_62m5_pllref_i : in std_logic;
-- clk_500m_o : out std_logic;
-- pll_500m_locked_o : out std_logic
-- );
-- end component pll_62m5_500m;
--
-- component gen_10mhz is
-- port (
-- clk_500m_i : in std_logic;
-- rst_n_i : in std_logic;
-- pps_i : in std_logic;
-- clk_10mhz_o : out std_logic
-- );
-- end component gen_10mhz;
begin -- architecture top
-- -- Never trigger PS_POR or PROGRAM_B
-- suicide_n_o <= '1';
-- wdog_n_o <= '1';
-- -- fmc_prsnt_m2c_l isn't used but must be defined as input.
-- -- fmc_pg_c2m isn't used
pci_clk_buf : IBUFDS_GTE2
port map(
I => pci_clk_p,
IB => pci_clk_n,
O => pci_clk,
ODIV2 => open,
CEB => '0'
);
cmp_gtx_dedicated_clk : IBUFDS_GTE2
generic map(
CLKCM_CFG => true,
CLKRCV_TRST => true,
CLKSWING_CFG => "11")
port map (
O => clk_125m_dmtd_buf,
ODIV2 => open,
CEB => '0',
I => clk_125m_dmtd_p_i,
IB => clk_125m_dmtd_n_i);
-- GTX clock buffer
cmp_gtx_buf_i : BUFG
port map (
I => clk_125m_dmtd_buf,
O => clk_sys_125m);
---------------------------------------------------------------------------
-- clk_sys_62m5 = clk_125m_dmtd_buf (125.000 MHz Div2)
---------------------------------------------------------------------------
process(clk_sys_125m)
begin
if rising_edge(clk_sys_125m) then
clk_sys_62m5 <= not clk_sys_62m5;
end if;
end process;
Pcie: processing_system_pcie_wrapper
port map (
DDR_addr =>DDR_addr ,
DDR_ba =>DDR_ba ,
DDR_cas_n =>DDR_cas_n ,
DDR_ck_n =>DDR_ck_n ,
DDR_ck_p =>DDR_ck_p ,
DDR_cke =>DDR_cke ,
DDR_cs_n =>DDR_cs_n ,
DDR_dm =>DDR_dm ,
DDR_dq =>DDR_dq ,
DDR_dqs_n =>DDR_dqs_n ,
DDR_dqs_p =>DDR_dqs_p ,
DDR_odt =>DDR_odt ,
DDR_ras_n =>DDR_ras_n ,
DDR_reset_n =>DDR_reset_n ,
DDR_we_n =>DDR_we_n ,
FIXED_IO_ddr_vrn =>FIXED_IO_ddr_vrn ,
FIXED_IO_ddr_vrp =>FIXED_IO_ddr_vrp ,
FIXED_IO_mio =>FIXED_IO_mio ,
FIXED_IO_ps_clk =>FIXED_IO_ps_clk ,
FIXED_IO_ps_porb =>FIXED_IO_ps_porb ,
FIXED_IO_ps_srstb =>FIXED_IO_ps_srstb,
M00_AXI_0_araddr => open,
M00_AXI_0_arburst => open,
M00_AXI_0_arcache => open,
M00_AXI_0_arlen => open,
M00_AXI_0_arlock => open,
M00_AXI_0_arprot => open,
M00_AXI_0_arqos => open,
M00_AXI_0_arready => open,
M00_AXI_0_arsize => open,
M00_AXI_0_arvalid => open,
M00_AXI_0_awaddr => open,
M00_AXI_0_awburst => open,
M00_AXI_0_awcache => open,
M00_AXI_0_awlen => open,
M00_AXI_0_awlock => open,
M00_AXI_0_awprot => open,
M00_AXI_0_awqos => open,
M00_AXI_0_awready => open,
M00_AXI_0_awsize => open,
M00_AXI_0_awvalid => open,
M00_AXI_0_bready => open,
M00_AXI_0_bresp => open,
M00_AXI_0_bvalid => open,
M00_AXI_0_rdata => open,
M00_AXI_0_rlast => open,
M00_AXI_0_rready => open,
M00_AXI_0_rresp => open,
M00_AXI_0_rvalid => open,
M00_AXI_0_wdata => open,
M00_AXI_0_wlast => open,
M00_AXI_0_wready => open,
M00_AXI_0_wstrb => open,
M00_AXI_0_wvalid => open,
aclk1_0 => clk_sys_62m5,
pcie_clk => pci_clk,
pcie_mgt_0_rxn => rxn,
pcie_mgt_0_rxp => rxp,
pcie_mgt_0_txn => txn,
pcie_mgt_0_txp => txp,
pcie_rst_n => perst_n,
user_lnk_up_0 => open,
usr_irq_ack_0 => open,
usr_irq_req_0 => "0"
);
-- m_axil_o.araddr(31 downto 28) <= x"0";
-- m_axil_o.araddr(27 downto 0) <= araddr(27 downto 0); --compensates for the PCI 0x4XXXXXXX offset
-- m_axil_o.awaddr(31 downto 28) <= x"0"; --not my cleanest fix....
-- m_axil_o.awaddr(27 downto 0) <= awaddr(27 downto 0);
-----------------------------------------------------------------------------
-- Axi to Wishbone converter
-----------------------------------------------------------------------------
--AXI2WB : xwb_axi4lite_bridge
-- port map(
-- clk_sys_i => clk_sys_62m5,
-- rst_n_i => reset_n_i,
--
-- axi4_slave_i => m_axil_o,
-- axi4_slave_o => m_axil_i,
-- wb_master_o => wb_master_o,
-- wb_master_i => wb_master_i
-- );
-----------------------------------------------------------------------------
-- The WR PTP core board package (WB Slave + WB Master)
-----------------------------------------------------------------------------
-- cmp_xwrc_board_spec7 : xwrc_board_spec7
-- generic map (
-- g_simulation => g_simulation,
-- g_with_external_clock_input => TRUE,
-- g_dpram_initf => g_dpram_initf,
-- g_fabric_iface => PLAIN)
-- port map (
-- areset_n_i => reset_n_i,
-- clk_125m_dmtd_n_i => clk_125m_dmtd_n_i,
-- clk_125m_dmtd_p_i => clk_125m_dmtd_p_i,
-- clk_125m_gtx_n_i => clk_125m_gtx_n_i,
-- clk_125m_gtx_p_i => clk_125m_gtx_p_i,
-- clk_10m_ext_i => clk_ext_10m,
-- clk_sys_62m5_o => clk_sys_62m5,
-- clk_ref_62m5_o => clk_ref_62m5,
-- rst_sys_62m5_n_o => rst_sys_62m5_n,
-- rst_ref_62m5_n_o => rst_ref_62m5_n,
--
-- dac_refclk_cs_n_o => dac_refclk_cs_n_int_o,
-- dac_refclk_sclk_o => dac_refclk_sclk_int_o,
-- dac_refclk_din_o => dac_refclk_din_int_o,
-- dac_dmtd_cs_n_o => dac_dmtd_cs_n_o,
-- dac_dmtd_sclk_o => dac_dmtd_sclk_o,
-- dac_dmtd_din_o => dac_dmtd_din_o,
--
-- pll_status_i => pll_status_i,
-- pll_mosi_o => pll_mosi_o,
-- pll_miso_i => pll_miso_i,
-- pll_sck_o => pll_sck_o,
-- pll_cs_n_o => pll_cs_n_o,
-- pll_sync_o => pll_sync_o,
-- pll_reset_n_o => open,
-- pll_lock_i => pll_lock_i,
-- pll_wr_mode_o => pll_wr_mode_o,
--
-- sfp_txp_o => sfp_txp_o,
-- sfp_txn_o => sfp_txn_o,
-- sfp_rxp_i => sfp_rxp_i,
-- sfp_rxn_i => sfp_rxn_i,
-- sfp_det_i => sfp_mod_def0_i,
-- sfp_sda_i => sfp_sda_in,
-- sfp_sda_o => sfp_sda_out,
-- sfp_scl_i => sfp_scl_in,
-- sfp_scl_o => sfp_scl_out,
-- sfp_rate_select_o => sfp_rate_select_o,
-- sfp_tx_fault_i => sfp_tx_fault_i,
-- sfp_tx_disable_o => sfp_tx_disable_o,
-- sfp_los_i => sfp_los_i,
--
-- eeprom_scl => scl_b,
-- eeprom_sda => sda_b,
--
-- aux_scl => fmc_la23_p,
-- aux_sda => fmc_la06_p,
--
-- onewire_i => '1', -- No onewire, Unique ID now via
-- onewire_oen_o => open, -- 24AA025EU48 (I2C Addr 1010.001x)
--
-- -- Uart
-- uart_rxd_i => uart_rxd_i,
-- uart_txd_o => uart_txd_o,
--
-- -- Wishbone
-- wb_slave_i => wb_master_o,
-- wb_slave_o => wb_master_i,
--
-- abscal_txts_o => wrc_abscal_txts_out,
-- abscal_rxts_o => wrc_abscal_rxts_out,
--
-- pps_ext_i => wrc_pps_in,
-- pps_p_o => wrc_pps_out,
-- pps_led_o => wrc_pps_led,
-- led_link_o => led_link_o,
-- led_act_o => led_act_o);
--
-- -- DAC signals for on board reference clock
-- dac_refclk_sclk_o <= dac_refclk_sclk_int_o;
-- dac_refclk_din_o <= dac_refclk_din_int_o;
-- dac_refclk_cs_n_o <= dac_refclk_cs_n_int_o;
--
-- -- Tristates for SFP EEPROM
-- sfp_mod_def1_b <= '0' when sfp_scl_out = '0' else 'Z';
-- sfp_mod_def2_b <= '0' when sfp_sda_out = '0' else 'Z';
-- sfp_scl_in <= sfp_mod_def1_b;
-- sfp_sda_in <= sfp_mod_def2_b;
--
-- ------------------------------------------------------------------------------
-- -- Digital I/O Bulls-Eye connections
-- ------------------------------------------------------------------------------
-- -- A01, A02 PPS_OUT (Bank 35 G16,G15)
-- -- A03, A04 10MHz_out (Bank 35 F15,E15)
-- -- A05, A06 125 MHz Reference Clock Out (WR Oscillators)
-- -- A07, A08 TX Spare GTX Out (Bank 112 GTX3 R2, R1)
-- -- A09, A10 ABSCAL_TXTS (Bank 35 C17,C16)
-- -- A11, A12 General Purpose Spare Out (Bank 35 K15,J15)
-- -- B01, B02 PPS_IN (Bank 35 G14,F14)
-- -- B03, B04 10MHZ_in (Bank 35 J14,H14)
-- -- B05, B06 125 MHz Reference Clock In (Bank 111 W6,W5)
-- -- B07, B08 RX Spare GTX Out (Bank 112 GTX3 T4, T3)
-- -- B09, B10 NC
-- -- B11, B12 PPS_IN single ended, NC (Bank 13 AE23, )
--
-- cmp_obuf_be_abscal_txts : OBUFDS
-- port map (
-- I => wrc_abscal_txts_out,
-- O => be_abscal_txts_p_o,
-- OB => be_abscal_txts_n_o);
--
-- cmp_obuf_be_pps_out : OBUFDS
-- port map (
-- I => wrc_pps_out,
-- O => be_pps_p_o,
-- OB => be_pps_n_o);
--
-- -- Div by 2 reference clock to LEMO connector
-- process(clk_ref_62m5)
-- begin
-- if rising_edge(clk_ref_62m5) then
-- clk_ref_div2 <= not clk_ref_div2;
-- end if;
-- end process;
--
-- ------------------------------------------------------------------------------
-- -- 10MHz output generation
-- ------------------------------------------------------------------------------
-- -- A 500 MHz reference clock is necessary since 10 MHz = 50 ns '1', 50 ns '0'
-- -- and 50 ns is divisible by 2 ns (not by 8 or 4 ns!) hence 500 MHz.
-- cmp_pll_62m5_500m: pll_62m5_500m
-- port map (
-- areset_n_i => rst_ref_62m5_n,
-- clk_62m5_pllref_i => clk_ref_62m5,
-- clk_500m_o => clk_500m,
-- pll_500m_locked_o => open
-- );
--
-- cmp_gen_10mhz: gen_10mhz
-- port map (
-- clk_500m_i => clk_500m,
-- rst_n_i => rst_ref_62m5_n,
-- pps_i => wrc_pps_out,
-- clk_10mhz_o => clk_10m_out
-- );
--
-- cmp_obuf_be_10mhz_out : OBUFDS
-- port map (
-- I => clk_10m_out,
-- O => be_clk_10m_p_o,
-- OB => be_clk_10m_n_o);
--
-- ------------------------------------------------------------------------------
-- -- LEDs
-- ------------------------------------------------------------------------------
-- U_Extend_PPS : gc_extend_pulse
-- generic map (
-- g_width => 10000000)
-- port map (
-- clk_i => clk_ref_62m5,
-- rst_n_i => rst_ref_62m5_n,
-- pulse_i => wrc_pps_led,
-- extended_o => pps_led_ext);
--
-- led_pps_o <= pps_led_ext;
-- fmc_la01_cc_p <= pps_led_ext; -- dio_led_top_o
-- fmc_la01_cc_n <= '0'; -- dio_led_bot_o
--
-- ------------------------------------------------------------------------------
-- -- Common FMC pin mapping Reference Design (spec7_ref_top)
-- ------------------------------------------------------------------------------
-- -- Configure DIO Output Enable
-- -- Configure Digital I/Os 0 to 3 as outputs
-- fmc_la30_p <= '0'; -- dio_oe_n_o(0)
-- fmc_la24_n <= '0'; -- dio_oe_n_o(1)
-- fmc_la15_n <= '0'; -- dio_oe_n_o(2)
-- -- Configure Digital I/Os 3 and 4 as inputs for external reference
-- fmc_la11_p <= '1'; -- dio_oe_n_o(3) for external 1-PPS
-- fmc_la05_p <= '1'; -- dio_oe_n_o(4) for external 10MHz clock
--
-- -- Configure DIO termination
-- -- All DIO connectors are not terminated
-- fmc_la30_n <= '0'; -- dio_term_n_o[0]
-- fmc_la06_n <= '0'; -- dio_term_n_o[1]
-- fmc_la05_n <= '0'; -- dio_term_n_o[2]
-- fmc_la09_p <= '0'; -- dio_term_n_o[3]
-- fmc_la09_n <= '0'; -- dio_term_n_o[4]
--
-- U_obuf_dio_o_0 : OBUFDS
-- port map (
-- I => wrc_pps_out,
-- O => fmc_la29_p, -- dio_p_o[0] <=> DIO Lemo 1
-- OB => fmc_la29_n); -- dio_n_o[0] <=> DIO Lemo 1
--
-- U_obuf_dio_o_1 : OBUFDS
-- port map (
-- I => wrc_abscal_rxts_out,
-- O => fmc_la28_p, -- dio_p_o[1] <=> DIO Lemo 2
-- OB => fmc_la28_n); -- dio_n_o[1] <=> DIO Lemo 2
--
-- U_obuf_dio_o_2 : OBUFDS
-- port map (
-- I => wrc_abscal_txts_out,
-- O => fmc_la08_p, -- dio_p_o[2] <=> DIO Lemo 3
-- OB => fmc_la08_n); -- dio_n_o[2] <=> DIO Lemo 3
--
-- ------------------------------------------------------------------------------
-- -- Design specific generates:
-- ------------------------------------------------------------------------------
-- ------------------------------------------------------------------------------
-- -- It depends on the design what input signals are used for external 10 MHz
-- -- and 1 PPS input.
-- -- spec7_ref_top : use DIO Lemo-5 10MHZ_in, Lemo-4 PPS_in
-- -- spec7_hpsec_top : use B03,B04 10MHZ_in, B01,B02 PPS_in
-- -- clk_ext_10m is also used as input to IDDR in the "even_odd_det" which poses
-- -- routing restrictions (i.e. clk_ext_10m for refrence and hpsec design can't
-- -- be OR-ed).
-- -- Note that output signals are available on FMC as well as Bulls-Eye
-- ------------------------------------------------------------------------------
-- ------------------------------------------------------------------------------
-- -- Design Specific FMC pin mapping Reference Design (spec7_ref_top)
-- ------------------------------------------------------------------------------
-- gen_ref_design : if (g_design = "spec7_ref_top") generate
--
-- U_ibuf_dio_i_3: IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => wrc_pps_in,
-- I => fmc_la03_p, -- dio_p_i[3] <=> DIO Lemo 4
-- IB => fmc_la03_n); -- dio_n_i[3] <=> DIO Lemo 4
--
-- cmp_ibugds_extref: IBUFGDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => clk_ext_10m,
-- I => fmc_clk1_m2c_p, -- dio_clk_p_i <=> DIO Lemo 5
-- IB => fmc_clk1_m2c_n); -- dio_clk_n_i <=> DIO Lemo 5
--
-- end generate gen_ref_design;
--
-- ------------------------------------------------------------------------------
-- -- Design Specific Bulls-Eye pin mapping HPSEC Design (spec7_hpsec_top)
-- ------------------------------------------------------------------------------
-- gen_hpsec_design : if (g_design = "spec7_hpsec_top") generate
--
-- -- Type of PPS_IN input:
-- -- Differential LVDS OR Single ended 5V capable
-- gen_pps_in_single : if (g_use_pps_in = "single") generate
-- begin
-- wrc_pps_in <= be_pps_i;
-- end generate gen_pps_in_single;
--
-- gen_pps_in_diff : if (g_use_pps_in = "diff") generate
-- begin
-- cmp_ibuf_pps_in: IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => wrc_pps_in,
-- I => be_pps_p_i,
-- IB => be_pps_n_i);
-- end generate gen_pps_in_diff;
--
-- cmp_ibufds_10mhz_in: IBUFDS
-- generic map (
-- DIFF_TERM => true)
-- port map (
-- O => clk_ext_10m,
-- I => be_clk_10m_p_i,
-- IB => be_clk_10m_n_i);
--
-- end generate gen_hpsec_design;
--
-- ------------------------------------------------------------------------------
-- -- Design Specific Bulls-Eye / FMC pin mapping HPSEC Design (spec7_hpsec_top)
-- ------------------------------------------------------------------------------
-- -- Forward DAC SPI via the FMC connnector to the HPSEC. It is safe to always
-- -- output these signals even with fmc-dio-5chttla plugged since LA02, LA04 and
-- -- LA07 are either not used or input on fmc-dio-5chttla.
-- ------------------------------------------------------------------------------
-- dac_refclk_sclk_diff : OBUFDS
-- port map (
-- I => dac_refclk_sclk_int_o,
-- O => fmc_la02_p, -- dac_refclk_sclk_p_o
-- OB => fmc_la02_n); -- dac_refclk_sclk_n_o
--
-- dac_refclk_din_diff : OBUFDS
-- port map (
-- I => dac_refclk_din_int_o,
-- O => fmc_la04_p, -- dac_refclk_din_p_o
-- OB => fmc_la04_n); -- dac_refclk_din_n_o
--
-- dac_refclk_cs_diff : OBUFDS
-- port map (
-- I => dac_refclk_cs_n_int_o,
-- O => fmc_la07_p, -- dac_refclk_cs_n_p_o
-- OB => fmc_la07_n); -- dac_refclk_cs_n_n_o
end architecture top;
hdl/top/spec7_golden_image/spec7_golden_image_top.xdc deleted 100644 → 0
View file @ 666a6346
# ---------------------------------------------------------------------------`
# -- Clocks/resets
# ---------------------------------------------------------------------------
# -- Local oscillators
# Bank 112 -- 125.000 MHz GTX reference
set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
# Bank 111 -- 125.000 MHz GTX reference
#set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
#set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
# Bank 35 (HP) VCCO - 1.8 V -- 124.992 MHz DMTD clock
set_property PACKAGE_PIN D15 [get_ports clk_125m_dmtd_p_i]
set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_p_i]
set_property PACKAGE_PIN D14 [get_ports clk_125m_dmtd_n_i]
set_property IOSTANDARD LVDS [get_ports clk_125m_dmtd_n_i]
create_clock -period 8.000 -name clk_125m_gtx -waveform {0.000 4.000} [get_ports clk_125m_gtx_p_i]
create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_ports clk_125m_dmtd_p_i]
# Set divide by 2 property for generated clk_dmtd (former platform xilinx: g_direct_dmtd = TRUE)
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_dmtd_reg/Q]
# Set divide by 2 property for generated clk_ref (former platform xilinx: g_phy_lpcalib = TRUE)
create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_ref_62m5_reg/Q]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
create_clock -period 16.000 -name RXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/RXOUTCLK]
create_clock -period 16.000 -name TXOUTCLK -waveform {0.000 8.000} [get_pins cmp_xwrc_board_spec7/cmp_gtx_lp/U_GTX_INST/gtxe2_i/TXOUTCLK]
# kent ie niet:
#create_clock -period 100.000 -name clk_ext_10m -waveform {0.000 50.000} [get_nets clk_ext_10m]
#create_clock -period 100.000 -name dio_clk -waveform {0.000 50.000} [get_ports dio_clk_p_i]
create_clock -period 100.000 -name fmc_clk_ext_10m -waveform {0.000 50.000} [get_ports fmc_clk1_m2c_p]
create_clock -period 100.000 -name be_clk_ext_10m -waveform {0.000 50.000} [get_ports be_clk_10m_p_i]
set_clock_groups -asynchronous \
-group clk_125m_gtx \
-group clk_ref_62m5_div2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
-group TXOUTCLK \
-group fmc_clk_ext_10m \
-group be_clk_ext_10m \
-group clk_ext_mul
# clk_ref_62m5_div2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
# Setup requirement at edge 8, hold requirement at edge 7
# See also:
# https://www.xilinx.com/video/hardware/timing-exception-multicycle-path-constraints.html
# See: "Multicycle Path and Positive phase shift" (due to the clk_ref_62m5_div2 to clk_500 delay through MMCME2_ADV)
set_multicycle_path 2 -setup -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 1 -hold -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
# ---------------------------------------------------------------------------
# -- SPI interface to on board DACs
# ---------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN G10 [get_ports dac_dmtd_din_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_din_o]
set_property PACKAGE_PIN E10 [get_ports dac_dmtd_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_sclk_o]
set_property PACKAGE_PIN F12 [get_ports dac_dmtd_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_dmtd_cs_n_o]
set_property PACKAGE_PIN D11 [get_ports dac_refclk_din_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_din_o]
set_property PACKAGE_PIN F10 [get_ports dac_refclk_sclk_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_sclk_o]
set_property PACKAGE_PIN D10 [get_ports dac_refclk_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports dac_refclk_cs_n_o]
# -------------------------------------------------------------------------------
# -- PLL Control signals
# -------------------------------------------------------------------------------
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B11 [get_ports pll_status_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_status_i]
set_property PACKAGE_PIN C14 [get_ports pll_mosi_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_mosi_o]
set_property PACKAGE_PIN C11 [get_ports pll_miso_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_miso_i]
set_property PACKAGE_PIN A15 [get_ports pll_sck_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sck_o]
set_property PACKAGE_PIN A14 [get_ports pll_cs_n_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_cs_n_o]
set_property PACKAGE_PIN B14 [get_ports pll_sync_o]
set_property IOSTANDARD LVCMOS18 [get_ports pll_sync_o]
set_property PACKAGE_PIN A12 [get_ports pll_lock_i]
set_property IOSTANDARD LVCMOS18 [get_ports pll_lock_i]
set_property PACKAGE_PIN B12 [get_ports {pll_wr_mode_o[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[0]}]
set_property PACKAGE_PIN C12 [get_ports {pll_wr_mode_o[1]}]
set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
set_property PACKAGE_PIN AA2 [get_ports {txp[0]}]
set_property PACKAGE_PIN Y3 [get_ports {rxn[1]}]
set_property PACKAGE_PIN Y4 [get_ports {rxp[1]}]
set_property PACKAGE_PIN W1 [get_ports {txn[1]}]
set_property PACKAGE_PIN W2 [get_ports {txp[1]}]
set_property PACKAGE_PIN R6 [get_ports pci_clk_p]
set_property PACKAGE_PIN R5 [get_ports pci_clk_n]
create_clock -period 10.000 -name pci_clk_p [get_ports pci_clk_p]
set_property PACKAGE_PIN D13 [get_ports perst_n]
set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# ---------------------------------------------------------------------------
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN V3 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN V4 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN U1 [get_ports sfp_txn_o]
set_property PACKAGE_PIN U2 [get_ports sfp_txp_o]
# Bank 35 (HP) VCCO - 1.8 V
# sfp detect
set_property PACKAGE_PIN H13 [get_ports sfp_mod_def0_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_mod_def0_i]
# scl
set_property PACKAGE_PIN E11 [get_ports sfp_mod_def1_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_mod_def1_b]
# sda
set_property PACKAGE_PIN G11 [get_ports sfp_mod_def2_b]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_mod_def2_b]
set_property PACKAGE_PIN F13 [get_ports sfp_rate_select_o]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_rate_select_o]
set_property PACKAGE_PIN J13 [get_ports sfp_tx_fault_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_tx_fault_i]
set_property PACKAGE_PIN G12 [get_ports sfp_tx_disable_o]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_tx_disable_o]
set_property PACKAGE_PIN K13 [get_ports sfp_los_i]
set_property IOSTANDARD LVCMOS18 [get_ports sfp_los_i]
# ---------------------------------------------------------------------------
# -- UART
# ---------------------------------------------------------------------------
# Signal uart_txd_o is an output in the design and must be connected to pin 20/12 (RXD_I) of CP2105GM
# Signal uart_rxd_i is an input in the design and must be connected to pin 21/13 (TXD_O) of CP2105GM
# Rx signals are pulled down so the USB on the CLB and the USB on the G-Board can be OR-ed
# Bank 12 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN W14 [get_ports uart_rxd_i]
set_property IOSTANDARD LVCMOS25 [get_ports uart_rxd_i]
set_property PACKAGE_PIN W17 [get_ports uart_txd_o]
set_property IOSTANDARD LVCMOS25 [get_ports uart_txd_o]
# ---------------------------------------------------------------------------
# -- Miscellaneous spec7 pins
# ---------------------------------------------------------------------------
# Bank 13 (HR) VCCO - 2.5 V
# LED_TOP
set_property PACKAGE_PIN AA25 [get_ports led_link_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_link_o]
# LED_BOT
set_property PACKAGE_PIN AB25 [get_ports led_act_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_act_o]
# LED_0
set_property PACKAGE_PIN AC26 [get_ports led_pps_o]
set_property IOSTANDARD LVCMOS25 [get_ports led_pps_o]
# LED_1
#set_property PACKAGE_PIN AB26 [get_ports led_1]
#set_property IOSTANDARD LVCMOS25 [get_ports led_1]
# LED_2
#set_property PACKAGE_PIN AE26 [get_ports led_2]
#set_property IOSTANDARD LVCMOS25 [get_ports led_2]
# LED_3
#set_property PACKAGE_PIN AE25 [get_ports led_3]
#set_property IOSTANDARD LVCMOS25 [get_ports led_3]
# Button
# Bank 13 (HR) VCCO - 2.5 V
#set_property PACKAGE_PIN V18 [get_ports button]
#set_property IOSTANDARD LVCMOS25 [get_ports button]
# Fans
# Bank 13 (HR) VCCO - 2.5 V
#set_property PACKAGE_PIN AD26 [get_ports fan_zynq_en]
#set_property IOSTANDARD LVCMOS25 [get_ports fan_zynq_en]
#set_property PACKAGE_PIN AD25 [get_ports fan_fmc_en]
#set_property IOSTANDARD LVCMOS25 [get_ports fan_fmc_en]
# Reset
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AA20 [get_ports reset_n_i]
set_property IOSTANDARD LVCMOS25 [get_ports reset_n_i]
# Suicide & Watchdog
# Bank 13 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AC22 [get_ports suicide_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports suicide_n_o]
set_property PACKAGE_PIN AC21 [get_ports wdog_n_o]
set_property IOSTANDARD LVCMOS25 [get_ports wdog_n_o]
# SI570
# Bank 12 (HR) VCCO - 2.5 V
#set_property PACKAGE_PIN AD14 [get_ports si570_clk_n]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_clk_n]
#set_property PACKAGE_PIN AC14 [get_ports si570_clk_p]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_clk_p]
#set_property PACKAGE_PIN Y15 [get_ports si570_sda]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_sda]
#set_property PACKAGE_PIN Y16 [get_ports si570_scl]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_scl]
#set_property PACKAGE_PIN W15 [get_ports si570_oe]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_oe]
#set_property PACKAGE_PIN W16 [get_ports si570_tune]
#set_property IOSTANDARD LVCMOS25 [get_ports si570_tune]
# I2C interface for accessing
# EEPROM (24AA64 Addr 1010.000x) and
# Unique ID (24AA025EU48, Addr 1010.001x).
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN B17 [get_ports scl_b]
set_property IOSTANDARD LVCMOS18 [get_ports scl_b]
set_property PACKAGE_PIN A17 [get_ports sda_b]
set_property IOSTANDARD LVCMOS18 [get_ports sda_b]
# ---------------------------------------------------------------------------
# -- Bulls-Eye connector
# ---------------------------------------------------------------------------
# PPS_OUT
# Bulls-Eye A01, A02
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN G16 [get_ports be_pps_p_o]
set_property IOSTANDARD LVDS [get_ports be_pps_p_o]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN G15 [get_ports be_pps_n_o]
set_property IOSTANDARD LVDS [get_ports be_pps_n_o]
# 10MHz_out
# Bulls-Eye A03, A04
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN F15 [get_ports be_clk_10m_p_o]
set_property IOSTANDARD LVDS [get_ports be_clk_10m_p_o]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN E15 [get_ports be_clk_10m_n_o]
set_property IOSTANDARD LVDS [get_ports be_clk_10m_n_o]
# 125MHz Reference Clock Out
# Bulls-Eye A05, A06 (connected to LTC6950)
# TX Spare GTX Out (Bank 112 GTX3)
# Bulls-Eye A07, A08
#set_property PACKAGE_PIN R2 [get_ports BE_TXP]
#set_property PACKAGE_PIN R1 [get_ports BE_TXN]
# ABSCAL_TXTS
# Bulls-Eye A09, A10
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN C17 [get_ports be_abscal_txts_p_o]
set_property IOSTANDARD LVDS [get_ports be_abscal_txts_p_o]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN C16 [get_ports be_abscal_txts_n_o]
set_property IOSTANDARD LVDS [get_ports be_abscal_txts_n_o]
# General Purpose Spare Out
# Bulls-Eye A11, A12
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN K15 [get_ports be_spare_p_o]
#set_property IOSTANDARD LVDS [get_ports be_spare_p_o]
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN J15 [get_ports be_spare_n_o]
#set_property IOSTANDARD LVDS [get_ports be_spare_n_o]
# PPS_IN
# Bulls-Eye B01, B02
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN G14 [get_ports be_pps_p_i]
set_property IOSTANDARD LVDS [get_ports be_pps_p_i]
# Bank 35 (HP) VCCO - 1.8 V
set_property PACKAGE_PIN F14 [get_ports be_pps_n_i]
set_property IOSTANDARD LVDS [get_ports be_pps_n_i]
# 10MHZ_IN
# Bulls-Eye B03, B04 (via LTC6950)
# Bank 35 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AF24 [get_ports be_clk_10m_p_i]
set_property IOSTANDARD LVDS_25 [get_ports be_clk_10m_p_i]
# Bank 35 (HR) VCCO - 2.5 V
set_property PACKAGE_PIN AF25 [get_ports be_clk_10m_n_i]
set_property IOSTANDARD LVDS_25 [get_ports be_clk_10m_n_i]
# Signal be_clk_ext_10m (HPSEC Design) is soly used for sampling the phase
# relation w.r.t. refclock. The signals be_clk_10m_p/n_i are routed to a
# non-clock capable pins. Hence:
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ext_10m]
# Reference Clock In (Bank 111)
# Bulls-Eye B05, B06
#set_property PACKAGE_PIN W6 [get_ports be_refclk_p]
#set_property PACKAGE_PIN W5 [get_ports be_refclk_n]
# RX Spare GTX Out (Bank 112 GTX3)
# Bulls-Eye B07, B08
#set_property PACKAGE_PIN T4 [get_ports be_rxp]
#set_property PACKAGE_PIN T3 [get_ports be_rxn]
# CLK_DMTD In (Debug purposes only)
# Bulls-Eye B09, B10
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN J14 [get_ports clk_dmtd_p_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_p_i]
# Bank 35 (HP) VCCO - 1.8 V
#set_property PACKAGE_PIN H14 [get_ports clk_dmtd_n_i]
#set_property IOSTANDARD LVDS [get_ports clk_dmtd_n_i]
# Bank 13 (HR) VCCO - 2.5 V
# Bulls-Eye B11 (PPS Single Ended)
set_property PACKAGE_PIN AE23 [get_ports be_pps_i]
set_property IOSTANDARD LVCMOS25 [get_ports be_pps_i]
# ---------------------------------------------------------------------------
# -- FMC connector
# ---------------------------------------------------------------------------
# Bank 13 VCCO - 2.5 V
set_property PACKAGE_PIN V19 [get_ports fmc_prsnt_m2c_l]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_prsnt_m2c_l]
# Bank 13 VCCO - 2.5 V
set_property PACKAGE_PIN AE20 [get_ports fmc_sda]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_sda]
set_property PACKAGE_PIN AE21 [get_ports fmc_scl]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_scl]
# FMC SIGNALS CLK LPC
# Bank 12 VCCO - 2.5 V
set_property PACKAGE_PIN AC13 [get_ports fmc_clk0_m2c_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_clk0_m2c_p]
set_property DIFF_TERM TRUE [get_ports fmc_clk0_m2c_p]
set_property PACKAGE_PIN AD13 [get_ports fmc_clk0_m2c_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_clk0_m2c_n]
set_property DIFF_TERM TRUE [get_ports fmc_clk0_m2c_n]
# Bank 13 VCCO - 2.5 V
set_property PACKAGE_PIN AC23 [get_ports fmc_clk1_m2c_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_clk1_m2c_p]
set_property DIFF_TERM TRUE [get_ports fmc_clk1_m2c_p]
set_property PACKAGE_PIN AC24 [get_ports fmc_clk1_m2c_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_clk1_m2c_n]
set_property DIFF_TERM TRUE [get_ports fmc_clk1_m2c_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 1
set_property PACKAGE_PIN AC12 [get_ports fmc_la00_cc_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la00_cc_p]
set_property DIFF_TERM TRUE [get_ports fmc_la00_cc_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 3
set_property PACKAGE_PIN AD11 [get_ports fmc_la00_cc_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la00_cc_n]
set_property DIFF_TERM TRUE [get_ports fmc_la00_cc_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 5
set_property PACKAGE_PIN AB15 [get_ports fmc_la01_cc_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la01_cc_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la01_cc_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 7
set_property PACKAGE_PIN AB14 [get_ports fmc_la01_cc_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la01_cc_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la01_cc_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 9
set_property PACKAGE_PIN AE17 [get_ports fmc_la02_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la02_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la02_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 11
set_property PACKAGE_PIN AF17 [get_ports fmc_la02_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la02_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la02_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 13
set_property PACKAGE_PIN AA24 [get_ports fmc_la03_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la03_p]
set_property DIFF_TERM TRUE [get_ports fmc_la03_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 15
set_property PACKAGE_PIN AB24 [get_ports fmc_la03_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la03_n]
set_property DIFF_TERM TRUE [get_ports fmc_la03_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 17
set_property PACKAGE_PIN AE16 [get_ports fmc_la04_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la04_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la04_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 19
set_property PACKAGE_PIN AE15 [get_ports fmc_la04_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la04_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la04_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 21
set_property PACKAGE_PIN W20 [get_ports fmc_la05_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la05_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 23
set_property PACKAGE_PIN Y20 [get_ports fmc_la05_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la05_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la05_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 25
set_property PACKAGE_PIN W18 [get_ports fmc_la06_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la06_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 27
set_property PACKAGE_PIN W19 [get_ports fmc_la06_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la06_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la06_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 29
set_property PACKAGE_PIN AB17 [get_ports fmc_la07_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la07_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la07_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 31
set_property PACKAGE_PIN AB16 [get_ports fmc_la07_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la07_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la07_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 33
set_property PACKAGE_PIN Y17 [get_ports fmc_la08_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la08_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la08_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 35
set_property PACKAGE_PIN AA17 [get_ports fmc_la08_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la08_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la08_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 37
set_property PACKAGE_PIN AA19 [get_ports fmc_la09_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la09_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la09_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 39
set_property PACKAGE_PIN AB19 [get_ports fmc_la09_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la09_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la09_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 2
set_property PACKAGE_PIN Y18 [get_ports fmc_la10_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la10_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la10_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 4
set_property PACKAGE_PIN AA18 [get_ports fmc_la10_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la10_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la10_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 6
set_property PACKAGE_PIN AF15 [get_ports fmc_la11_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la11_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la11_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 8
set_property PACKAGE_PIN AF14 [get_ports fmc_la11_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la11_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la11_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 10
set_property PACKAGE_PIN AC17 [get_ports fmc_la12_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la12_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la12_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 12
set_property PACKAGE_PIN AC16 [get_ports fmc_la12_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la12_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la12_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 14
set_property PACKAGE_PIN AA22 [get_ports fmc_la13_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la13_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la13_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 16
set_property PACKAGE_PIN AA23 [get_ports fmc_la13_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la13_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la13_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 18
set_property PACKAGE_PIN AB21 [get_ports fmc_la14_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la14_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la14_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 20
set_property PACKAGE_PIN AB22 [get_ports fmc_la14_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la14_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la14_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 22
set_property PACKAGE_PIN AD16 [get_ports fmc_la15_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la15_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la15_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 24
set_property PACKAGE_PIN AD15 [get_ports fmc_la15_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la15_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la15_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 26
set_property PACKAGE_PIN AA15 [get_ports fmc_la16_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la16_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la16_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 28
set_property PACKAGE_PIN AA14 [get_ports fmc_la16_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la16_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la16_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 30
set_property PACKAGE_PIN AD20 [get_ports fmc_la17_cc_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la17_cc_p]
set_property DIFF_TERM TRUE [get_ports fmc_la17_cc_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 32
set_property PACKAGE_PIN AD21 [get_ports fmc_la17_cc_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la17_cc_n]
set_property DIFF_TERM TRUE [get_ports fmc_la17_cc_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 34
set_property PACKAGE_PIN AD23 [get_ports fmc_la18_cc_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la18_cc_p]
set_property DIFF_TERM TRUE [get_ports fmc_la18_cc_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J1 pin 36
set_property PACKAGE_PIN AD24 [get_ports fmc_la18_cc_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la18_cc_n]
set_property DIFF_TERM TRUE [get_ports fmc_la18_cc_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 38
set_property PACKAGE_PIN Y12 [get_ports fmc_la19_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la19_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la19_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J1 pin 40
set_property PACKAGE_PIN Y11 [get_ports fmc_la19_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la19_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la19_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 1
set_property PACKAGE_PIN W13 [get_ports fmc_la20_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la20_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la20_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 3
set_property PACKAGE_PIN Y13 [get_ports fmc_la20_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la20_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la20_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 5
set_property PACKAGE_PIN AA13 [get_ports fmc_la21_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la21_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la21_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 7
set_property PACKAGE_PIN AA12 [get_ports fmc_la21_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la21_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la21_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 9
set_property PACKAGE_PIN Y10 [get_ports fmc_la22_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la22_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la22_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 11
set_property PACKAGE_PIN AA10 [get_ports fmc_la22_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la22_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la22_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 13
set_property PACKAGE_PIN AE22 [get_ports fmc_la23_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la23_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la23_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 15
set_property PACKAGE_PIN AF22 [get_ports fmc_la23_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la23_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la23_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 2
set_property PACKAGE_PIN AE13 [get_ports fmc_la24_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la24_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la24_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 4
set_property PACKAGE_PIN AF13 [get_ports fmc_la24_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la24_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la24_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 6
set_property PACKAGE_PIN AB11 [get_ports fmc_la25_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la25_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la25_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J20 pin 8
set_property PACKAGE_PIN AB10 [get_ports fmc_la25_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la25_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la25_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 10
set_property PACKAGE_PIN AD18 [get_ports fmc_la26_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la26_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 12
set_property PACKAGE_PIN AD19 [get_ports fmc_la26_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la26_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la26_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 14
set_property PACKAGE_PIN AC18 [get_ports fmc_la27_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la27_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J20 pin 16
set_property PACKAGE_PIN AC19 [get_ports fmc_la27_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la27_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la27_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J16 pin 5
set_property PACKAGE_PIN AE12 [get_ports fmc_la28_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la28_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la28_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J16 pin 7
set_property PACKAGE_PIN AF12 [get_ports fmc_la28_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la28_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la28_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J16 pin 9
set_property PACKAGE_PIN AF19 [get_ports fmc_la29_p]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la29_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la29_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J16 pin 11
set_property PACKAGE_PIN AF20 [get_ports fmc_la29_n]
set_property IOSTANDARD LVDS_25 [get_ports fmc_la29_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la29_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J16 pin 6
set_property PACKAGE_PIN AE11 [get_ports fmc_la30_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la30_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la30_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J16 pin 8
set_property PACKAGE_PIN AF10 [get_ports fmc_la30_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la30_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la30_n]
# Bank 13 VCCO - 2.5 V FMC_XM105 J16 pin 10
set_property PACKAGE_PIN AE18 [get_ports fmc_la31_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_p]
# Bank 13 VCCO - 2.5 V FMC_XM105 J16 pin 12
set_property PACKAGE_PIN AF18 [get_ports fmc_la31_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la31_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la31_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 3
set_property PACKAGE_PIN AB12 [get_ports fmc_la32_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 4
set_property PACKAGE_PIN AC11 [get_ports fmc_la32_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la32_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la32_n]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 5
set_property PACKAGE_PIN AE10 [get_ports fmc_la33_p]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la33_p]
#set_property DIFF_TERM TRUE [get_ports fmc_la33_p]
# Bank 12 VCCO - 2.5 V FMC_XM105 J15 pin 6
set_property PACKAGE_PIN AD10 [get_ports fmc_la33_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la33_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la33_n]
# Bank 111 GTX
set_property PACKAGE_PIN AA6 [get_ports fmc_gbtclk0_m2c_p]
set_property PACKAGE_PIN AA5 [get_ports fmc_gbtclk0_m2c_n]
#set_property PACKAGE_PIN AD8 [get_ports fmc_dp0_m2c_p]
#set_property PACKAGE_PIN AD7 [get_ports fmc_dp0_m2c_n]
#set_property PACKAGE_PIN AF8 [get_ports fmc_dp0_c2m_p]
#set_property PACKAGE_PIN AF7 [get_ports fmc_dp0_c2m_n]
#set_property PACKAGE_PIN AE6 [get_ports fmc_dp1_m2c_p]
#set_property PACKAGE_PIN AE5 [get_ports fmc_dp1_m2c_n]
#set_property PACKAGE_PIN AF4 [get_ports fmc_dp1_c2m_p]
#set_property PACKAGE_PIN AF3 [get_ports fmc_dp1_c2m_n]
#set_property PACKAGE_PIN AC6 [get_ports fmc_dp2_m2c_p]
#set_property PACKAGE_PIN AC5 [get_ports fmc_dp2_m2c_n]
#set_property PACKAGE_PIN AE2 [get_ports fmc_dp2_c2m_p]
#set_property PACKAGE_PIN AE1 [get_ports fmc_dp2_c2m_n]
#set_property PACKAGE_PIN AD4 [get_ports fmc_dp3_m2c_p]
#set_property PACKAGE_PIN AD3 [get_ports fmc_dp3_m2c_n]
#set_property PACKAGE_PIN AC2 [get_ports fmc_dp3_c2m_p]
#set_property PACKAGE_PIN AC1 [get_ports fmc_dp3_c2m_n]
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