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SPEC7
Commits
8d25772f
Commit
8d25772f
authored
Aug 31, 2021
by
Peter Jansweijer
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remove unused spec7_golden_image. Tandem PROM stage 1: spec7_tandem_boot, stage 2: spec7_ref_design
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.gitignore
hdl/syn/spec7_golden_image/.gitignore
+0
-12
Manifest.py
hdl/syn/spec7_golden_image/Manifest.py
+0
-14
README.TXT
hdl/syn/spec7_golden_image/README.TXT
+0
-27
do_vivado.cmd
hdl/syn/spec7_golden_image/do_vivado.cmd
+0
-10
do_vivado_gen_bin_mcs.cmd
hdl/syn/spec7_golden_image/do_vivado_gen_bin_mcs.cmd
+0
-9
do_vivado_prog.cmd
hdl/syn/spec7_golden_image/do_vivado_prog.cmd
+0
-9
do_vivado_tcl.cmd
hdl/syn/spec7_golden_image/do_vivado_tcl.cmd
+0
-16
proj_file_list.txt
hdl/syn/spec7_golden_image/proj_file_list.txt
+0
-11
proj_properties.tcl
hdl/syn/spec7_golden_image/proj_properties.tcl
+0
-31
Manifest.py
hdl/top/spec7_golden_image/Manifest.py
+0
-4
spec7_golden_image_top.vhd
hdl/top/spec7_golden_image/spec7_golden_image_top.vhd
+0
-847
spec7_golden_image_top.xdc
hdl/top/spec7_golden_image/spec7_golden_image_top.xdc
+0
-655
No files found.
hdl/syn/spec7_golden_image/.gitignore
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/.Xil
/work
/*.bak
/*.jou
/*.log
/*.prm
/*.mcs
/*.bin
/*.bit
/spec7_write_top_bd.bmm
/revisiondate_log.txt
/hdl_version.xdc
hdl/syn/spec7_golden_image/Manifest.py
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board
=
"spec7"
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc7z035"
syn_grade
=
"-1"
syn_package
=
"fbg676"
syn_top
=
"spec7_golden_image_top"
syn_project
=
"spec7_golden_image_top.xpr"
syn_tool
=
"vivado"
modules
=
{
"local"
:
"../../top/spec7_golden_image/"
}
\ No newline at end of file
hdl/syn/spec7_golden_image/README.TXT
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Synthesis and Place&Route README.TXT January 25, 2018
--------------------------------------------------------
Scripts:
--------
1) do_vivado.cmd start vivado (calling viv_do_all.tcl)
2) do_vivado_tcl.cmd start vivado tcl console.
You may want to type:
a) "start_gui" to start the vivado gui
b) "source proj_properties.tcl" to find the path to the scripts and next
"source $script_dir/viv_do_all.tcl"
3) do_elf.cmd combines the software and the empty "%DesName%.bit" file. Uses "software.elf", "%DesName%.bit"
and "%DesName%_bd.bmm" and merges them into "%DesName%_elf.bit"
4) do_vivado_prog.cmd download the configuration ("%DesName%_elf.bit") into the Evaluation board via the USB
download cable.
Project info and sources:
--------
proj_properties.tcl contains the project properties (name, device etc.)
proj_file_list.txt a text file with all project sources. Remember that the wr-cores files are listed
using "hdlmake list-files > proj_file_list.txt" in
directory "../../wr-cores/syn/clbv3_ref_design"
Scripts that are called by the scripts above or can be executed separately on the tcl command line:
--------
viv_do_synt.tcl sourced by viv_do_all.tcl, starts vivado synthesis run
viv_do_impl.tcl sourced by viv_do_all.tcl, starts vivado implementation run
viv_do_program.tcl sourced by do_vivado_prog.cmd
hdl/syn/spec7_golden_image/do_vivado.cmd
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rem do_vivado.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del *.log
del *.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_all.tcl
hdl/syn/spec7_golden_image/do_vivado_gen_bin_mcs.cmd
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rem prog.cmd PeterJ, 23-JUl-2018.
@prompt $$$s
rem ### Clean up old log files and stuff
del vivado_gen_bin_mcs.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_gen_bin_mcs.tcl -log vivado_gen_bin_mcs.log
hdl/syn/spec7_golden_image/do_vivado_prog.cmd
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rem prog.cmd PeterJ, 23-Jan-2018.
@prompt $$$s
rem ### Cleanup old log files and stuff
del vivado_prog.log
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode batch -source ..\..\..\sw\scripts\viv_do_program.tcl -log vivado_prog.log
hdl/syn/spec7_golden_image/do_vivado_tcl.cmd
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rem do_vivado_tcl.cmd PeterJ, 19-Jan-2018.
@prompt $$$s
rem ### Usually one wants to start Vivado in tcl mode to inspect an existing design,
rem ### therefore don't delete log files and setting. Else remove "rem" statements in the lines below.
rem set DesName=clbv3_wr_ref_top
rem set LogName=%DesName%-vivado
rem ### Cleanup old log files and stuff (
rem del vivado*.log
rem del vivado*.jou
rem ### note that environment variable "VIVADO" must be set to something like "E:\Xilinx\Vivado\2017.1\bin\"
rem ### in your (User) Environment Variables
"%VIVADO%\vivado.bat" -mode tcl
hdl/syn/spec7_golden_image/proj_file_list.txt
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# From directory ....spec7/hdl/syn/spec7_golden_image
# hdlmake list-files > proj_file_list.txt
../../top/spec7_golden_image/spec7_golden_image_top.vhd
../../top/spec7_golden_image/spec7_golden_image_top.xdc
# bmm not supported by hdlmake? Need to add it manually...
../../ip/processing_system_pcie.bd
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
hdl/syn/spec7_golden_image/proj_properties.tcl
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#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
set
spec7_design spec7_golden_image_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance
)
set
device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
set
proj_name spec7_golden_image_top
set
proj_dir work
set
script_dir
[
pwd
]
/../../../sw/scripts
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl
)
if
{
$argc
== 0 ||
$argv
!=
"no_update_revision"
}
{
source
$script
_dir/revisiondate.tcl
set generics
"g_design=
$spec7
_design"
}
hdl/top/spec7_golden_image/Manifest.py
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files
=
[
"spec7_golden_image_top.vhd"
,
"spec7_golden_image_top.xdc"
,
]
hdl/top/spec7_golden_image/spec7_golden_image_top.vhd
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hdl/top/spec7_golden_image/spec7_golden_image_top.xdc
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