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Commit 666a6346 authored by Peter Jansweijer's avatar Peter Jansweijer
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remove deprecated petalinux project

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sw/embedded/testos/.gitignore deleted 100644 → 0
View file @ 3588acb2
*/*/config.old
*/*/rootfs_config.old
build/
images/linux/
pre-built/linux/
.petalinux/*
!.petalinux/metadata
*.o
*.jou
*.log
project-spec/meta-plnx-generated/
/components/plnx_workspace
sw/embedded/testos/.petalinux/metadata deleted 100644 → 0
View file @ 3588acb2
PETALINUX_VER=2019.1
project_id=44f2553df2cb882a1cda53b02b1f4bc8
sw/embedded/testos/config.project deleted 100644 → 0
View file @ 3588acb2
#
# Automatically generated file; DO NOT EDIT.
# PetaLinux SDK Project Configuration
#
CONFIG_PROJECT_ADDITIONAL_COMPONENTS_SEARCH_PATH=""
#
# Subsystems of the project
#
CONFIG_PROJECT_SUBSYSTEM_LINUX_INSTANCE_LINUX=y
CONFIG_PROJECT_SUBSYSTEMS=y
sw/embedded/testos/project-spec/attributes deleted 100644 → 0
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#Virtual Providers
#defconfigs
UBOOT_DEFAULT_DEFCONFIG="zynq_zc702_config"
sw/embedded/testos/project-spec/configs/config deleted 100644 → 0
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#
# Automatically generated file; DO NOT EDIT.
# misc/config System Configuration
#
CONFIG_SUBSYSTEM_TYPE_LINUX=y
CONFIG_SYSTEM_ZYNQ=y
#
# Linux Components Selection
#
CONFIG_SUBSYSTEM_COMPONENT_DEVICE__TREE_NAME_DEVICE__TREE__GENERATOR=y
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_FSBL=y
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_NAME_ZYNQ_FSBL=y
CONFIG_SUBSYSTEM_COMPONENT_BOOTLOADER_AUTO_PS_INIT=y
CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_U__BOOT__XLNX=y
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_REMOTE is not set
# CONFIG_SUBSYSTEM_COMPONENT_U__BOOT_NAME_EXT__LOCAL__SRC is not set
CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_LINUX__XLNX=y
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_REMOTE is not set
# CONFIG_SUBSYSTEM_COMPONENT_LINUX__KERNEL_NAME_EXT__LOCAL__SRC is not set
#
# Auto Config Settings
#
CONFIG_SUBSYSTEM_AUTOCONFIG_FSBL=y
CONFIG_SUBSYSTEM_AUTOCONFIG_DEVICE__TREE=y
# CONFIG_SUBSYSTEM_DEVICE_TREE_MANUAL_INCLUDE is not set
CONFIG_SUBSYSTEM_DEVICE_TREE_INCLUDE_DIR="${STAGING_KERNEL_DIR}/include"
CONFIG_SUBSYSTEM_AUTOCONFIG_KERNEL=y
CONFIG_SUBSYSTEM_AUTOCONFIG_U__BOOT=y
CONFIG_SUBSYSTEM_HARDWARE_AUTO=y
CONFIG_SUBSYSTEM_PROCESSOR0_IP_NAME="ps7_cortexa9_0"
CONFIG_SUBSYSTEM_PROCESSOR_PS7_CORTEXA9_0_SELECT=y
CONFIG_SUBSYSTEM_ARCH_ARM=y
#
# Memory Settings
#
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SELECT=y
# CONFIG_SUBSYSTEM_MEMORY_SIMPLE_SELECT is not set
# CONFIG_SUBSYSTEM_MEMORY_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_BASEADDR=0x0
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_SIZE=0x40000000
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_KERNEL_BASEADDR=0x0
CONFIG_SUBSYSTEM_MEMORY_PS7_DDR_0_BANKLESS_U__BOOT_TEXTBASE_OFFSET=0x400000
CONFIG_SUBSYSTEM_MEMORY_IP_NAME="PS7_DDR_0"
#
# Serial Settings
#
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_SELECT=y
# CONFIG_SUBSYSTEM_SERIAL_MANUAL_SELECT is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_600 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_9600 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_28800 is not set
CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_115200=y
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_230400 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_460800 is not set
# CONFIG_SUBSYSTEM_SERIAL_PS7_UART_0_BAUDRATE_921600 is not set
CONFIG_SUBSYSTEM_SERIAL_IP_NAME="ps7_uart_0"
#
# Ethernet Settings
#
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_SELECT=y
# CONFIG_SUBSYSTEM_ETHERNET_MANUAL_SELECT is not set
# CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC_AUTO is not set
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC="00:0a:35:00:1e:53"
CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_USE_DHCP=y
#
# Flash Settings
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_SELECT=y
# CONFIG_SUBSYSTEM_FLASH_MANUAL_SELECT is not set
# CONFIG_SUBSYSTEM_FLASH__ADVANCED_AUTOCONFIG is not set
#
# partition 0
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_NAME="boot"
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0x500000
#
# partition 1
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_NAME="bootenv"
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART1_SIZE=0x20000
#
# partition 2
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_NAME="kernel"
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2_SIZE=0xA80000
#
# partition 3
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="spare"
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x0
#
# partition 4
#
CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART4_NAME=""
CONFIG_SUBSYSTEM_FLASH_IP_NAME="ps7_qspi_0"
#
# SD/SDIO Settings
#
CONFIG_SUBSYSTEM_PRIMARY_SD_PS7_SD_0_SELECT=y
# CONFIG_SUBSYSTEM_PRIMARY_SD_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_SD_PS7_SD_0_SELECT=y
#
# RTC Settings
#
CONFIG_SUBSYSTEM_RTC_MANUAL_SELECT=y
CONFIG_SUBSYSTEM_I2C_PS7_I2C_0_SELECT=y
CONFIG_SUBSYSTEM_USB_PS7_USB_0_SELECT=y
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG=y
#
# boot image settings
#
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOT_IMAGE_NAME="BOOT.BIN"
#
# u-boot env partition settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_BOOTENV_PART_NAME="bootenv"
#
# kernel image settings
#
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_FLASH_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_SD_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_KERNEL_IMAGE_NAME="image.ub"
#
# jffs2 rootfs image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_FLASH_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_PART_NAME="jffs2"
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_JFFS2_IMAGE_NAME="rootfs.jffs2"
#
# dtb image settings
#
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_BOOTIMAGE_SELECT=y
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_FLASH_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_SD_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_ETHERNET_SELECT is not set
# CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_MEDIA_MANUAL_SELECT is not set
CONFIG_SUBSYSTEM_IMAGES_ADVANCED_AUTOCONFIG_DTB_IMAGE_NAME="system.dtb"
CONFIG_SUBSYSTEM_ENDIAN_LITTLE=y
#
# DTG Settings
#
CONFIG_SUBSYSTEM_MACHINE_NAME="template"
#
# Kernel Bootargs
#
CONFIG_SUBSYSTEM_BOOTARGS_AUTO=y
CONFIG_SUBSYSTEM_BOOTARGS_EARLYPRINTK=y
CONFIG_SUBSYSTEM_DEVICETREE_FLAGS=""
# CONFIG_SUBSYSTEM_DTB_OVERLAY is not set
# CONFIG_SUBSYSTEM_REMOVE_PL_DTB is not set
#
# FPGA Manager
#
# CONFIG_SUBSYSTEM_FPGA_MANAGER is not set
#
# u-boot Configuration
#
CONFIG_SUBSYSTEM_UBOOT_CONFIG_PETALINUX=y
# CONFIG_SUBSYSTEM_UBOOT_CONFIG_OTHER is not set
CONFIG_SUBSYSTEM_UBOOT_CONFIG_TARGET="zynq_zc702_config"
CONFIG_SUBSYSTEM_NETBOOT_OFFSET=0x10000000
CONFIG_SUBSYSTEM_U__BOOT_TFTPSERVER_IP="AUTO"
#
# Image Packaging Configuration
#
# CONFIG_SUBSYSTEM_ROOTFS_INITRAMFS is not set
# CONFIG_SUBSYSTEM_ROOTFS_INITRD is not set
# CONFIG_SUBSYSTEM_ROOTFS_JFFS2 is not set
# CONFIG_SUBSYSTEM_ROOTFS_NFS is not set
CONFIG_SUBSYSTEM_ROOTFS_SD=y
# CONFIG_SUBSYSTEM_ROOTFS_OTHER is not set
CONFIG_SUBSYSTEM_SDROOT_DEV="/dev/mmcblk0p2"
CONFIG_SUBSYSTEM_UIMAGE_NAME="image.ub"
CONFIG_SUBSYSTEM_DTB_PADDING_SIZE=0x1000
# CONFIG_SUBSYSTEM_COPY_TO_TFTPBOOT is not set
#
# Firmware Version Configuration
#
CONFIG_SUBSYSTEM_HOSTNAME="spec7"
CONFIG_SUBSYSTEM_PRODUCT="spec7"
CONFIG_SUBSYSTEM_FW_VERSION="1.00"
#
# Yocto Settings
#
CONFIG_YOCTO_MACHINE_NAME="plnx-zynq7"
#
# TMPDIR Location
#
CONFIG_TMP_DIR_LOCATION="${PROOT}/build/tmp"
#
# Parallel thread execution
#
CONFIG_YOCTO_BB_NUMBER_THREADS=""
CONFIG_YOCTO_PARALLEL_MAKE=""
#
# Add pre-mirror url
#
CONFIG_PRE_MIRROR_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/downloads"
#
# Local sstate feeds settings
#
#
# Default sstate feeds ${PETALINUX}/components/yocto always added
#
CONFIG_YOCTO_LOCAL_SSTATE_FEEDS_URL=""
# CONFIG_YOCTO_ENABLE_DEBUG_TWEAKS is not set
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS=y
#
# Network sstate feeds URL
#
CONFIG_YOCTO_NETWORK_SSTATE_FEEDS_URL="http://petalinux.xilinx.com/sswreleases/rel-v${PETALINUX_VER%%.*}/arm/sstate-cache"
# CONFIG_YOCTO_BB_NO_NETWORK is not set
#
# User Layers
#
CONFIG_USER_LAYER_0=""
CONFIG_SUBSYSTEM_BOOTARGS_GENERATED="console=ttyPS0,115200 earlyprintk root=/dev/mmcblk0p2 rw rootwait"
sw/embedded/testos/project-spec/configs/rootfs_config deleted 100644 → 0
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sw/embedded/testos/project-spec/hw-description/ps7_init.h deleted 100644 → 0
View file @ 3588acb2
/******************************************************************************
*
* Copyright (C) 2010-2019 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
* copies of the Software, and to permit persons to whom the Software is
* furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF
* OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 100000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
sw/embedded/testos/project-spec/hw-description/ps7_init_gpl.h deleted 100644 → 0
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/******************************************************************************
*
* Copyright (C) 2010-2019 <Xilinx Inc.>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License along
* with this program; if not, see <http://www.gnu.org/licenses/>
*
*
******************************************************************************/
/****************************************************************************/
/**
*
* @file ps7_init_gpl.h
*
* This file can be included in FSBL code
* to get prototype of ps7_init() function
* and error codes
*
*****************************************************************************/
#ifdef __cplusplus
extern "C" {
#endif
//typedef unsigned int u32;
/** do we need to make this name more unique ? **/
//extern u32 ps7_init_data[];
extern unsigned long * ps7_ddr_init_data;
extern unsigned long * ps7_mio_init_data;
extern unsigned long * ps7_pll_init_data;
extern unsigned long * ps7_clock_init_data;
extern unsigned long * ps7_peripherals_init_data;
#define OPCODE_EXIT 0U
#define OPCODE_CLEAR 1U
#define OPCODE_WRITE 2U
#define OPCODE_MASKWRITE 3U
#define OPCODE_MASKPOLL 4U
#define OPCODE_MASKDELAY 5U
#define NEW_PS7_ERR_CODE 1
/* Encode number of arguments in last nibble */
#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 )
#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr
#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val
#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val
#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask
#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask
/* Returns codes of PS7_Init */
#define PS7_INIT_SUCCESS (0) // 0 is success in good old C
#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now
#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out
#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init
#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit
#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init
/* Silicon Versions */
#define PCW_SILICON_VERSION_1 0
#define PCW_SILICON_VERSION_2 1
#define PCW_SILICON_VERSION_3 2
/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */
#define PS7_POST_CONFIG
/* Freq of all peripherals */
#define APU_FREQ 666666687
#define DDR_FREQ 533333374
#define DCI_FREQ 10158730
#define QSPI_FREQ 200000000
#define SMC_FREQ 10000000
#define ENET0_FREQ 125000000
#define ENET1_FREQ 10000000
#define USB0_FREQ 60000000
#define USB1_FREQ 60000000
#define SDIO_FREQ 100000000
#define UART_FREQ 100000000
#define SPI_FREQ 10000000
#define I2C_FREQ 111111115
#define WDT_FREQ 111111115
#define TTC_FREQ 50000000
#define CAN_FREQ 10000000
#define PCAP_FREQ 200000000
#define TPIU_FREQ 200000000
#define FPGA0_FREQ 50000000
#define FPGA1_FREQ 10000000
#define FPGA2_FREQ 10000000
#define FPGA3_FREQ 10000000
/* For delay calculation using global registers*/
#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200
#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204
#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208
#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218
int ps7_config( unsigned long*);
int ps7_init();
int ps7_post_config();
int ps7_debug();
char* getPS7MessageInfo(unsigned key);
void perf_start_clock(void);
void perf_disable_clock(void);
void perf_reset_clock(void);
void perf_reset_and_start_timer();
int get_number_of_cycles_for_delay(unsigned int delay);
#ifdef __cplusplus
}
#endif
sw/embedded/testos/project-spec/meta-user/COPYING.MIT deleted 100644 → 0
View file @ 3588acb2
Permission is hereby granted, free of charge, to any person obtaining a copy
of this software and associated documentation files (the "Software"), to deal
in the Software without restriction, including without limitation the rights
to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
copies of the Software, and to permit persons to whom the Software is
furnished to do so, subject to the following conditions:
The above copyright notice and this permission notice shall be included in
all copies or substantial portions of the Software.
THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
THE SOFTWARE.
sw/embedded/testos/project-spec/meta-user/README deleted 100644 → 0
View file @ 3588acb2
This README file contains information on the contents of the
meta-user layer.
Please see the corresponding sections below for details.
Dependencies
============
This layer depends on:
URI: git://git.openembedded.org/bitbake
branch: master
URI: git://git.openembedded.org/openembedded-core
layers: meta
branch: master
URI: git://git.yoctoproject.org/xxxx
layers: xxxx
branch: master
Patches
=======
Please submit any patches against the meta-user layer to the
xxxx mailing list (xxxx@zzzz.org) and cc: the maintainer:
Maintainer: XXX YYYYYY <xxx.yyyyyy@zzzzz.com>
Table of Contents
=================
I. Adding the meta-user layer to your build
II. Misc
I. Adding the meta-user layer to your build
=================================================
--- replace with specific instructions for the meta-user layer ---
In order to use this layer, you need to make the build system aware of
it.
Assuming the meta-user layer exists at the top-level of your
yocto build tree, you can add it to the build system by adding the
location of the meta-user layer to bblayers.conf, along with any
other layers needed. e.g.:
BBLAYERS ?= " \
/path/to/yocto/meta \
/path/to/yocto/meta-poky \
/path/to/yocto/meta-yocto-bsp \
/path/to/yocto/meta-meta-user \
"
II. Misc
========
--- replace with specific information about the meta-user layer ---
sw/embedded/testos/project-spec/meta-user/conf/layer.conf deleted 100644 → 0
View file @ 3588acb2
# We have a conf and classes directory, add to BBPATH
BBPATH .= ":${LAYERDIR}"
# We have recipes-* directories, add to BBFILES
BBFILES += "${LAYERDIR}/recipes-*/*/*.bb \
${LAYERDIR}/recipes-*/*/*.bbappend"
BBFILE_COLLECTIONS += "meta-user"
BBFILE_PATTERN_meta-user = "^${LAYERDIR}/"
BBFILE_PRIORITY_meta-user = "6"
LAYERSERIES_COMPAT_meta-user = "thud"
sw/embedded/testos/project-spec/meta-user/conf/petalinuxbsp.conf deleted 100644 → 0
View file @ 3588acb2
#User Configuration
#OE_TERMINAL = "tmux"
# Add EXTRA_IMAGEDEPENDS default components
EXTRA_IMAGEDEPENDS_append_versal = " virtual/psm-firmware virtual/plm arm-trusted-firmware u-boot-zynq-scr"
EXTRA_IMAGEDEPENDS_append_zynqmp = " virtual/fsbl virtual/pmu-firmware arm-trusted-firmware"
EXTRA_IMAGEDEPENDS_append_zynq = " virtual/fsbl"
EXTRA_IMAGEDEPENDS_append_microblaze = " virtual/fsboot virtual/elfrealloc"
# prevent U-Boot from deploying the boot.bin
SPL_BINARY = ""
#Remove all qemu contents
IMAGE_CLASSES_remove = "image-types-xilinx-qemu qemuboot-xilinx"
IMAGE_FSTYPES_remove = "wic.qemu-sd"
EXTRA_IMAGEDEPENDS_remove = "qemu-helper-native virtual/boot-bin"
SIGGEN_UNLOCKED_RECIPES_append_versal = " initscripts"
sw/embedded/testos/project-spec/meta-user/recipes-apps/gpio-demo/files/Makefile deleted 100644 → 0
View file @ 3588acb2
APP = gpio-demo
# Add any other object files to this list below
APP_OBJS = gpio-demo.o
all: $(APP)
$(APP): $(APP_OBJS)
$(CC) $(LDFLAGS) -o $@ $(APP_OBJS) $(LDLIBS)
clean:
-rm -f $(APP) *.elf *.gdb *.o
sw/embedded/testos/project-spec/meta-user/recipes-apps/gpio-demo/files/gpio-demo.c deleted 100644 → 0
View file @ 3588acb2
/*
*
* gpio-demo app
*
* Copyright (C) 2013 - 2016 Xilinx, Inc. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without restriction,
* including without limitation the rights to use, copy, modify, merge,
* publish, distribute, sublicense, and/or sell copies of the Software,
* and to permit persons to whom the Software is furnished to do so,
* subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included
* in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
* IN NO EVENT SHALL XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*
* Except as contained in this notice, the name of the Xilinx shall not be used
* in advertising or otherwise to promote the sale, use or other dealings in this
* Software without prior written authorization from Xilinx.
*
*/
#include <stdio.h>
#include <stdlib.h>
#include <unistd.h>
#include <string.h>
#include <errno.h>
#include <fcntl.h>
#include <signal.h>
#define GPIO_ROOT "/sys/class/gpio"
#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
static enum {NONE, IN, OUT, CYLON, KIT} gpio_opt = NONE;
static const unsigned long cylon[] = {
0x00000080, 0x00000040, 0x00000020, 0x00000010,
0x00000008, 0x00000004, 0x00000002, 0x00000001,
0x00000002, 0x00000004, 0x00000008,
0x00000010, 0x00000020, 0x00000040, 0x00000080,
};
static const unsigned long kit[] = {
0x000000e0, 0x00000070, 0x00000038, 0x0000001c,
0x0000000e, 0x00000007, 0x00000003, 0x00000001,
0x00000003, 0x00000007, 0x0000000e,
0x0000001c, 0x00000038, 0x00000070, 0x000000e0,
};
static int gl_gpio_base = 0;
static void usage (char *argv0)
{
char *basename = strrchr(argv0, '/');
if (!basename)
basename = argv0;
fprintf(stderr,
"Usage: %s [-g GPIO_BASE] COMMAND\n"
"\twhere COMMAND is one of:\n"
"\t\t-i\t\tInput value from GPIO and print it\n"
"\t\t-o\tVALUE\tOutput value to GPIO\n"
"\t\t-c\t\tCylon test pattern\n"
"\t\t-k\t\t KIT test pattern\n"
"\tGPIO_BASE indicates which GPIO chip to talk to (The number can be \n"
"\tfound at /sys/class/gpio/gpiochipN).\n"
"\tThe highest gpiochipN is the first gpio listed in the dts file, \n"
"\tand the lowest gpiochipN is the last gpio listed in the dts file.\n"
"\tE.g.If the gpiochip240 is the LED_8bit gpio, and I want to output '1' \n"
"\tto the LED_8bit gpio, the command should be:\n"
"\t\tgpio-demo -g 240 -o 1\n"
"\n"
"\tgpio-demo written by Xilinx Inc.\n"
"\n"
, basename);
exit(-2);
}
static int open_gpio_channel(int gpio_base)
{
char gpio_nchan_file[128];
int gpio_nchan_fd;
int gpio_max;
int nchannel;
char nchannel_str[5];
char *cptr;
int c;
char channel_str[5];
char *gpio_export_file = "/sys/class/gpio/export";
int export_fd=0;
/* Check how many channels the GPIO chip has */
sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
if (gpio_nchan_fd < 0) {
fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
return -1;
}
read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
close(gpio_nchan_fd);
nchannel=(int)strtoul(nchannel_str, &cptr, 0);
if (cptr == nchannel_str) {
fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
exit(1);
}
/* Open files for each GPIO channel */
export_fd=open(gpio_export_file, O_WRONLY);
if (export_fd < 0) {
fprintf(stderr, "Cannot open GPIO to export %d\n", gpio_base);
return -1;
}
gpio_max = gpio_base + nchannel;
for(c = gpio_base; c < gpio_max; c++) {
sprintf(channel_str, "%d", c);
write(export_fd, channel_str, (strlen(channel_str)+1));
}
close(export_fd);
return nchannel;
}
static int close_gpio_channel(int gpio_base)
{
char gpio_nchan_file[128];
int gpio_nchan_fd;
int gpio_max;
int nchannel;
char nchannel_str[5];
char *cptr;
int c;
char channel_str[5];
char *gpio_unexport_file = "/sys/class/gpio/unexport";
int unexport_fd=0;
/* Check how many channels the GPIO chip has */
sprintf(gpio_nchan_file, "%s/gpiochip%d/ngpio", GPIO_ROOT, gpio_base);
gpio_nchan_fd = open(gpio_nchan_file, O_RDONLY);
if (gpio_nchan_fd < 0) {
fprintf(stderr, "Failed to open %s: %s\n", gpio_nchan_file, strerror(errno));
return -1;
}
read(gpio_nchan_fd, nchannel_str, sizeof(nchannel_str));
close(gpio_nchan_fd);
nchannel=(int)strtoul(nchannel_str, &cptr, 0);
if (cptr == nchannel_str) {
fprintf(stderr, "Failed to change %s into GPIO channel number\n", nchannel_str);
exit(1);
}
/* Close opened files for each GPIO channel */
unexport_fd=open(gpio_unexport_file, O_WRONLY);
if (unexport_fd < 0) {
fprintf(stderr, "Cannot close GPIO by writing unexport %d\n", gpio_base);
return -1;
}
gpio_max = gpio_base + nchannel;
for(c = gpio_base; c < gpio_max; c++) {
sprintf(channel_str, "%d", c);
write(unexport_fd, channel_str, (strlen(channel_str)+1));
}
close(unexport_fd);
return 0;
}
static int set_gpio_direction(int gpio_base, int nchannel, char *direction)
{
char gpio_dir_file[128];
int direction_fd=0;
int gpio_max;
int c;
gpio_max = gpio_base + nchannel;
for(c = gpio_base; c < gpio_max; c++) {
sprintf(gpio_dir_file, "/sys/class/gpio/gpio%d/direction",c);
direction_fd=open(gpio_dir_file, O_RDWR);
if (direction_fd < 0) {
fprintf(stderr, "Cannot open the direction file for GPIO %d\n", c);
return 1;
}
write(direction_fd, direction, (strlen(direction)+1));
close(direction_fd);
}
return 0;
}
static int set_gpio_value(int gpio_base, int nchannel, int value)
{
char gpio_val_file[128];
int val_fd=0;
int gpio_max;
char val_str[2];
int c;
gpio_max = gpio_base + nchannel;
for(c = gpio_base; c < gpio_max; c++) {
sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
val_fd=open(gpio_val_file, O_RDWR);
if (val_fd < 0) {
fprintf(stderr, "Cannot open the value file of GPIO %d\n", c);
return -1;
}
sprintf(val_str,"%d", (value & 1));
write(val_fd, val_str, sizeof(val_str));
close(val_fd);
value >>= 1;
}
return 0;
}
static int get_gpio_value(int gpio_base, int nchannel)
{
char gpio_val_file[128];
int val_fd=0;
int gpio_max;
char val_str[2];
char *cptr;
int value = 0;
int c;
gpio_max = gpio_base + nchannel;
for(c = gpio_max-1; c >= gpio_base; c--) {
sprintf(gpio_val_file, "/sys/class/gpio/gpio%d/value",c);
val_fd=open(gpio_val_file, O_RDWR);
if (val_fd < 0) {
fprintf(stderr, "Cannot open GPIO to export %d\n", c);
return -1;
}
read(val_fd, val_str, sizeof(val_str));
value <<= 1;
value += (int)strtoul(val_str, &cptr, 0);
if (cptr == optarg) {
fprintf(stderr, "Failed to change %s into integer", val_str);
}
close(val_fd);
}
return value;
}
void signal_handler(int sig)
{
switch (sig) {
case SIGTERM:
case SIGHUP:
case SIGQUIT:
case SIGINT:
close_gpio_channel(gl_gpio_base);
exit(0) ;
default:
break;
}
}
int main(int argc, char *argv[])
{
extern char *optarg;
char *cptr;
int gpio_value = 0;
int nchannel = 0;
int c;
int i;
opterr = 0;
while ((c = getopt(argc, argv, "g:io:ck")) != -1) {
switch (c) {
case 'g':
gl_gpio_base = (int)strtoul(optarg, &cptr, 0);
if (cptr == optarg)
usage(argv[0]);
break;
case 'i':
gpio_opt = IN;
break;
case 'o':
gpio_opt = OUT;
gpio_value = (int)strtoul(optarg, &cptr, 0);
if (cptr == optarg)
usage(argv[0]);
break;
case 'c':
gpio_opt = CYLON;
break;
case 'k':
gpio_opt = KIT;
break;
case '?':
usage(argv[0]);
default:
usage(argv[0]);
}
}
if (gl_gpio_base == 0) {
usage(argv[0]);
}
nchannel = open_gpio_channel(gl_gpio_base);
signal(SIGTERM, signal_handler); /* catch kill signal */
signal(SIGHUP, signal_handler); /* catch hang up signal */
signal(SIGQUIT, signal_handler); /* catch quit signal */
signal(SIGINT, signal_handler); /* catch a CTRL-c signal */
switch (gpio_opt) {
case IN:
set_gpio_direction(gl_gpio_base, nchannel, "in");
gpio_value=get_gpio_value(gl_gpio_base, nchannel);
fprintf(stdout,"0x%08X\n", gpio_value);
break;
case OUT:
set_gpio_direction(gl_gpio_base, nchannel, "out");
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
break;
case CYLON:
#define CYLON_DELAY_USECS (10000)
set_gpio_direction(gl_gpio_base, nchannel, "out");
for (;;) {
for(i=0; i < ARRAY_SIZE(cylon); i++) {
gpio_value=(int)cylon[i];
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
}
usleep(CYLON_DELAY_USECS);
}
case KIT:
#define KIT_DELAY_USECS (10000)
set_gpio_direction(gl_gpio_base, nchannel, "out");
for (;;) {
for (i=0; i<ARRAY_SIZE(kit); i++) {
gpio_value=(int)kit[i];
set_gpio_value(gl_gpio_base, nchannel, gpio_value);
}
usleep(KIT_DELAY_USECS);
}
default:
break;
}
close_gpio_channel(gl_gpio_base);
return 0;
}
sw/embedded/testos/project-spec/meta-user/recipes-bsp/device-tree/device-tree.bbappend deleted 100644 → 0
View file @ 3588acb2
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://system-user.dtsi"
sw/embedded/testos/project-spec/meta-user/recipes-bsp/u-boot/u-boot-xlnx_%.bbappend deleted 100644 → 0
View file @ 3588acb2
FILESEXTRAPATHS_prepend := "${THISDIR}/files:"
SRC_URI += "file://platform-top.h"
sw/embedded/testos/readme.txt deleted 100644 → 0
View file @ 3588acb2
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