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SPEC7
Commit 7ada704a authored by Peter Jansweijer's avatar Peter Jansweijer
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add generic g_dac_bits (default 16)

parent 6a36bede
Pipeline #3242 failed with stage
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    hdl/board/wr_spec7_pkg.vhd
    View file @ 7ada704a
    ......@@ -132,7 +132,7 @@ package wr_spec7_pkg is
    wrs_rx_cfg_i : in t_rx_streamer_cfg := c_rx_streamer_cfg_default;
    aux_diag_i : in t_generic_word_array(g_diag_ro_size-1 downto 0) := (others => (others => '0'));
    aux_diag_o : out t_generic_word_array(g_diag_rw_size-1 downto 0);
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......
    hdl/board/wrc_board_spec7.vhd
    View file @ 7ada704a
    ......@@ -261,7 +261,7 @@ entity wrc_board_spec7 is
    ---------------------------------------------------------------------------
    -- Aux clocks control
    ---------------------------------------------------------------------------
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......
    hdl/board/xwrc_board_spec7.vhd
    View file @ 7ada704a
    ......@@ -76,7 +76,8 @@ entity xwrc_board_spec7 is
    g_diag_ver : integer := 0;
    -- size the generic diag interface
    g_diag_ro_size : integer := 0;
    g_diag_rw_size : integer := 0
    g_diag_rw_size : integer := 0;
    g_dac_bits : integer := 16
    );
    port (
    ---------------------------------------------------------------------------
    ......@@ -226,7 +227,7 @@ entity xwrc_board_spec7 is
    ---------------------------------------------------------------------------
    -- Aux clocks control
    ---------------------------------------------------------------------------
    tm_dac_value_o : out std_logic_vector(23 downto 0);
    tm_dac_value_o : out std_logic_vector(31 downto 0);
    tm_dac_wr_o : out std_logic_vector(g_aux_clks-1 downto 0);
    tm_clk_aux_lock_en_i : in std_logic_vector(g_aux_clks-1 downto 0) := (others => '0');
    tm_clk_aux_locked_o : out std_logic_vector(g_aux_clks-1 downto 0);
    ......@@ -307,9 +308,9 @@ architecture struct of xwrc_board_spec7 is
    -- PLL DACs
    signal dac_dmtd_load : std_logic;
    signal dac_dmtd_data : std_logic_vector(15 downto 0);
    signal dac_dmtd_data : std_logic_vector(g_dac_bits-1 downto 0);
    signal dac_refclk_load : std_logic;
    signal dac_refclk_data : std_logic_vector(15 downto 0);
    signal dac_refclk_data : std_logic_vector(g_dac_bits-1 downto 0);
    signal sit5359_scl_pad_oen, sit5359_sda_pad_oen : std_logic;
    signal sit5359_scl_pad_in, sit5359_sda_pad_in : std_logic;
    ......@@ -609,7 +610,7 @@ begin -- architecture struct
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    value_i => dac_dmtd_data,
    value_i => dac_dmtd_data(g_dac_bits-1 downto g_dac_bits-16),
    cs_sel_i => "1",
    load_i => dac_dmtd_load,
    sclk_divsel_i => "001",
    ......@@ -619,7 +620,8 @@ begin -- architecture struct
    cmp_sit5359_wr_interface: entity work.xwr_sit5359_interface
    generic map (
    g_simulation => g_simulation)
    g_simulation => g_simulation,
    g_dac_bits => g_dac_bits)
    port map (
    clk_sys_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    ......@@ -647,7 +649,7 @@ begin -- architecture struct
    port map (
    clk_i => clk_sys_62m5,
    rst_n_i => rst_62m5_n,
    value_i => dac_refclk_data,
    value_i => dac_refclk_data(g_dac_bits-1 downto g_dac_bits-16),
    cs_sel_i => "1",
    load_i => dac_refclk_load,
    sclk_divsel_i => "001",
    ......@@ -683,6 +685,7 @@ begin -- architecture struct
    g_diag_ver => g_diag_ver,
    g_diag_ro_size => g_diag_ro_size,
    g_diag_rw_size => g_diag_rw_size,
    g_dac_bits => g_dac_bits,
    g_streamers_op_mode => g_streamers_op_mode,
    g_tx_streamer_params => g_tx_streamer_params,
    g_rx_streamer_params => g_rx_streamer_params,
    ......
    wr-cores @ 37fa98d1
    Subproject commit 55007fa1f97b70684a2d52cd7cfbb517db42c0a6
    Subproject commit 37fa98d109871fb7854106aee2941c60cf69ed24
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