sit5359 test via XM105 Xilinx debug card

6a36bede · Peter Jansweijer · e284ea80 · 6a36bede · 6a36bede · 6a36bede
Commit 6a36bede authored Jan 10, 2022 by Peter Jansweijer
13 changed files
--- a/hdl/board/wr_spec7_pkg.vhd
+++ b/hdl/board/wr_spec7_pkg.vhd
@@ -102,6 +102,8 @@ package wr_spec7_pkg is
      sfp_tx_fault_i       : in  std_logic                                        := '0';
      sfp_tx_disable_o     : out std_logic;
      sfp_los_i            : in  std_logic                                        := '0';
+      sit5359_sda          : inout  std_logic;
+      sit5359_scl          : inout  std_logic;
      eeprom_scl           : inout  std_logic;
      eeprom_sda           : inout  std_logic;
      aux_scl              : inout  std_logic;

--- a/hdl/board/xwrc_board_spec7.vhd
+++ b/hdl/board/xwrc_board_spec7.vhd
@@ -150,6 +150,12 @@ entity xwrc_board_spec7 is
    sfp_tx_disable_o     : out std_logic;
    sfp_los_i            : in  std_logic := '0';

+    ---------------------------------------------------------------------------
+    -- I2C SiTime5359 Reference Oscillator
+    ---------------------------------------------------------------------------
+    sit5359_sda : inout std_logic;
+    sit5359_scl : inout std_logic;
+
    ---------------------------------------------------------------------------
    -- I2C EEPROM
    ---------------------------------------------------------------------------
@@ -304,6 +310,8 @@ architecture struct of xwrc_board_spec7 is
  signal dac_dmtd_data        : std_logic_vector(15 downto 0);
  signal dac_refclk_load      : std_logic;
  signal dac_refclk_data      : std_logic_vector(15 downto 0);
+  signal sit5359_scl_pad_oen, sit5359_sda_pad_oen : std_logic;
+  signal sit5359_scl_pad_in, sit5359_sda_pad_in : std_logic;

  -- OneWire
  signal onewire_in           : std_logic_vector(1 downto 0);
@@ -320,25 +328,28 @@ architecture struct of xwrc_board_spec7 is
  signal ext_ref_rst          : std_logic;

  -- wr-cores Aux WB bus to SPEC7 WB Crossbar
-  constant c_cnx_slave_ports  : integer := 1;
-  signal cnx_slave_in         : t_wishbone_slave_in_array(c_cnx_slave_ports-1 downto 0);
-  signal cnx_slave_out        : t_wishbone_slave_out_array(c_cnx_slave_ports-1 downto 0);
+  constant c_wrc_aux_slave_ports  : integer := 1;
+  signal aux_cnx_slave_in     : t_wishbone_slave_in_array(c_wrc_aux_slave_ports-1 downto 0);
+  signal aux_cnx_slave_out    : t_wishbone_slave_out_array(c_wrc_aux_slave_ports-1 downto 0);

  constant c_master_wrpc      : integer := 0;

  -- SPEC7 WB bus
-  constant c_cnx_master_ports : integer := 1;
-  signal cnx_master_in        : t_wishbone_master_in_array(c_cnx_master_ports-1 downto 0);
-  signal cnx_master_out       : t_wishbone_master_out_array(c_cnx_master_ports-1 downto 0);
+  constant c_wrc_aux_master_ports : integer := 2;
+  signal aux_cnx_master_in    : t_wishbone_master_in_array(c_wrc_aux_master_ports-1 downto 0);
+  signal aux_cnx_master_out   : t_wishbone_master_out_array(c_wrc_aux_master_ports-1 downto 0);

-  constant c_slave_gpio       : integer := 0;
+  constant c_wrc_aux_slave_gpio       : integer := 0;
+  constant c_wrc_aux_slave_sit5359    : integer := 1;

-  constant c_cfg_base_addr    : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
-    (c_slave_gpio    => x"00000000"
+  constant c_cfg_base_addr    : t_wishbone_address_array(c_wrc_aux_master_ports-1 downto 0) :=
+    (c_wrc_aux_slave_gpio    => x"00000000",
+     c_wrc_aux_slave_sit5359 => x"00000080"
     );

-  constant c_cfg_base_mask    : t_wishbone_address_array(c_cnx_master_ports-1 downto 0) :=
-    (c_slave_gpio    => x"00000f00"
+  constant c_cfg_base_mask    : t_wishbone_address_array(c_wrc_aux_master_ports-1 downto 0) :=
+    (c_wrc_aux_slave_gpio    => x"00000f80",
+     c_wrc_aux_slave_sit5359 => x"00000f80"
     );

  constant c_num_gpio_pins    : integer := 17;
@@ -606,6 +617,27 @@ begin  -- architecture struct
      dac_sclk_o    => dac_dmtd_sclk_o,
      dac_sdata_o   => dac_dmtd_din_o);

+  cmp_sit5359_wr_interface: entity work.xwr_sit5359_interface
+     generic map (
+       g_simulation => g_simulation)
+     port map (
+       clk_sys_i         => clk_sys_62m5,
+       rst_n_i           => rst_62m5_n,
+       tm_dac_value_i    => dac_refclk_data,
+       tm_dac_value_wr_i => dac_refclk_load,
+       scl_pad_oen_o     => sit5359_scl_pad_oen,
+       sda_pad_oen_o     => sit5359_sda_pad_oen,
+       scl_pad_i         => sit5359_scl_pad_in,
+       sda_pad_i         => sit5359_sda_pad_in,
+       slave_i           => aux_cnx_master_out(c_wrc_aux_slave_sit5359),
+       slave_o           => aux_cnx_master_in(c_wrc_aux_slave_sit5359) );
+
+  -- SiTime5359 Reference Oscillator I2C tri-states
+  sit5359_scl  <= '0' when (sit5359_scl_pad_oen = '0') else 'Z';
+  sit5359_scl_pad_in <= sit5359_scl;
+  sit5359_sda  <= '0' when (sit5359_sda_pad_oen = '0') else 'Z';
+  sit5359_sda_pad_in <= sit5359_sda;
+
  cmp_refclk_dac : gc_serial_dac
    generic map (
      g_num_data_bits => 16,
@@ -694,8 +726,8 @@ begin  -- architecture struct
      owr_i                => onewire_in,
      wb_slave_i           => wb_slave_i,
      wb_slave_o           => wb_slave_o,
-      aux_master_o         => cnx_slave_in(c_master_wrpc),
-      aux_master_i         => cnx_slave_out(c_master_wrpc),
+      aux_master_o         => aux_cnx_slave_in(c_master_wrpc),
+      aux_master_i         => aux_cnx_slave_out(c_master_wrpc),
      wrf_src_o            => wrf_src_o,
      wrf_src_i            => wrf_src_i,
      wrf_snk_o            => wrf_snk_o,
@@ -737,20 +769,20 @@ begin  -- architecture struct
      pps_led_o            => pps_led_o,
      link_ok_o            => link_ok_o);

-  cmp_wb_spec7_con : xwb_crossbar
+  cmp_wrc_aux_crossbar : xwb_crossbar
    generic map (
-      g_num_masters => c_cnx_slave_ports,
-      g_num_slaves  => c_cnx_master_ports,
+      g_num_masters => c_wrc_aux_slave_ports,
+      g_num_slaves  => c_wrc_aux_master_ports,
      g_registered  => true,
      g_address     => c_cfg_base_addr,
      g_mask        => c_cfg_base_mask)
    port map (
      clk_sys_i => clk_sys_62m5,
      rst_n_i   => rst_62m5_n,
-      slave_i   => cnx_slave_in,
-      slave_o   => cnx_slave_out,
-      master_i  => cnx_master_in,
-      master_o  => cnx_master_out);
+      slave_i   => aux_cnx_slave_in,
+      slave_o   => aux_cnx_slave_out,
+      master_i  => aux_cnx_master_in,
+      master_o  => aux_cnx_master_out);

  cmp_spec7_gpio : xwb_gpio_port
    generic map (
@@ -761,8 +793,8 @@ begin  -- architecture struct
    port map (
      clk_sys_i  => clk_sys_62m5,
      rst_n_i    => rst_62m5_n,
-      slave_i    => cnx_master_out(c_slave_gpio),
-      slave_o    => cnx_master_in(c_slave_gpio),
+      slave_i    => aux_cnx_master_out(c_wrc_aux_slave_gpio),
+      slave_o    => aux_cnx_master_in(c_wrc_aux_slave_gpio),
      gpio_out_o => gpio_out,
      gpio_in_i  => gpio_in,
      gpio_oen_o => gpio_oen);

--- a/hdl/sim/sit5359_tst/.gitignore
+++ b/hdl/sim/sit5359_tst/.gitignore
+/spec7.lib
+/*.bram
+/*.mem
+/*.bak
+/*.wlf
+/*.vstf
+/*.lnk
+/*.jou
+/*.log
+/transcript
\ No newline at end of file
--- a/hdl/sim/sit5359_tst/VCom_spec7_wr_ref_top_Functional.tcl
+++ b/hdl/sim/sit5359_tst/VCom_spec7_wr_ref_top_Functional.tcl
+# VCom_Functional.tcl
+# compile for functional simulation
+# From directory vcom -explicit -93 -work work ../../wr-cores/syn/spec7_ref_design
+# hdlmake list-files > proj_file_list.txt
+
+#vcom -explicit -93 -work work ../../top/spec7_ref_design/spec7_wr_ref_top.xdc
+#vcom -explicit -93 -work work ../../top/spec7_ref_design/spec7_wr_hpsec_top.xdc
+
+vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/genram_pkg.vhd
+vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wbgen2/wbgen2_pkg.vhd
+vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wishbone_pkg.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
+
+# Executing Vivado Block Design script:
+# ../../ip/ps_pcie.bd
+# results in many file that are genearted to instantiate this functionality.
+# If a full simulation needs to be done including these Block Designs then Vivado can generate simulation files.
--- a/hdl/sim/sit5359_tst/VSim_Functional.tcl
+++ b/hdl/sim/sit5359_tst/VSim_Functional.tcl
+set Simulation TRUE
+
+if {$Simulation} {
+    puts "Note: Simulation"
+	  set g_simulation 1
+	} else {
+    puts "Note: Synthesis"
+	  set g_simulation 0
+	}
+
+# -novopt is now deprecated
+#vsim -voptargs="+acc" -novopt 
+vsim -voptargs="+acc=lnprv" \
+  -G/xwr_sit5359_interface/g_simulation=$g_simulation \
+   -t ps -L unisim -lib work work.xwr_sit5359_interface
+
+# Depending on what needs to be simultated
+do wave.tcl
+do test.tcl
+
+view signals
+
+#run 100 us
+
+#stop
+
+wave zoom full
+
+#
+# End
+#
--- a/hdl/sim/sit5359_tst/spec7_wr_ref_top.smi
+++ b/hdl/sim/sit5359_tst/spec7_wr_ref_top.smi
+<?xml version="1.0" encoding="UTF-8"?>
+<MemInfoSimulation Version="1" Minor="1">
+  <Processor Endianness="Big" InstPath="lm32_wrpc_memory">
+    <AddressSpace Name="lm32_wrpc_memory_dpram" ECC="NONE" Begin="0" End="131071">
+          <BusBlock>
+        <BitLane MemType="lm32_wrpc_memory_dpram" MemType_DataWidth="32" MemType_AddressDepth="131071">
+          <DataWidth MSB="31" LSB="0"/>
+          <AddressRange Begin="0" End="32767"/>
+          <Parity ON="false" NumBits="0"/>
+          <MemFile Name="lm32_wrpc_memory.mem"/>
+        </BitLane>
+      </BusBlock>
+    </AddressSpace>
+  </Processor>
+  <Config>
+    <Option Name="Part" Val="xc7k160tfbg676-2"/>
+  </Config>
+  <DRC>
+    <Rule Name="RDADDRCHANGE" Val="false"/>
+  </DRC>
+</MemInfoSimulation>
--- a/hdl/sim/sit5359_tst/test.tcl
+++ b/hdl/sim/sit5359_tst/test.tcl
+force /xwr_sit5359_interface/clk_sys_i 0,1 8 ns -rep 16 ns
+force /xwr_sit5359_interface/rst_n_i 0,1 64 ns
+
+force /xwr_sit5359_interface/tm_dac_value_i 32768
+force /xwr_sit5359_interface/tm_dac_value_wr_i 0
+
+force /xwr_sit5359_interface/scl_pad_i H
+force /xwr_sit5359_interface/sda_pad_i H
+
+force /xwr_sit5359_interface/slave_i.cyc 0
+force /xwr_sit5359_interface/slave_i.stb 0
+force /xwr_sit5359_interface/slave_i.adr 0
+force /xwr_sit5359_interface/slave_i.sel 0
+force /xwr_sit5359_interface/slave_i.we 0
+force /xwr_sit5359_interface/slave_i.dat 0
+
+run 128 ns
+
+# WR Adr 0 Control Reg: OSC_OE(1) - SPLL_EN(1) - CLK_DIV(8) - I2C_ADDR(8)
+# I2C_ADDR = 1100010 (A0=0 WR:0xC4, RD:0xC5), 1101010 (A0=1 WR:0xD4, RD:0xD5)
+force /xwr_sit5359_interface/slave_i.cyc 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.stb 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.we  1,0 16 ns
+force /xwr_sit5359_interface/slave_i.adr 0
+force /xwr_sit5359_interface/slave_i.dat 0x104C4
+run 32 ns
+
+# WR Adr 1 RFFREQ Reg
+force /xwr_sit5359_interface/slave_i.cyc 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.stb 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.we  1,0 16 ns
+force /xwr_sit5359_interface/slave_i.adr 4
+force /xwr_sit5359_interface/slave_i.dat 0x55aa
+run 32 ns
+
+# RD Adr 0 Control Reg: OSC_OE(1) - SPLL_EN(1) - CLK_DIV(8) - I2C_ADDR(8)
+force /xwr_sit5359_interface/slave_i.cyc 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.stb 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.we  0
+force /xwr_sit5359_interface/slave_i.adr 0
+force /xwr_sit5359_interface/slave_i.dat 0x0
+run 32 ns
+
+# RD Adr 1  RFFREQ Reg
+force /xwr_sit5359_interface/slave_i.cyc 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.stb 1,0 16 ns
+force /xwr_sit5359_interface/slave_i.we  0
+force /xwr_sit5359_interface/slave_i.adr 4
+force /xwr_sit5359_interface/slave_i.dat 0x0
+run 128 ns
+
+#force /xwr_sit5359_interface/tm_dac_value_i 0xaa12
+#force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+#run 128 ns
+
+# 3000000 (7000000)
+force /xwr_sit5359_interface/tm_dac_value_i 0x0000000
+force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+run 20.48 us
+
+# 1FFFE00 (5FFFE00)
+force /xwr_sit5359_interface/tm_dac_value_i 0x0007fff
+force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+run 20.48 us
+
+# 000000 (4000000)
+force /xwr_sit5359_interface/tm_dac_value_i 0x0008000
+force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+run 20.48 us
+
+# 000200 (4000200)
+force /xwr_sit5359_interface/tm_dac_value_i 0x0008001
+force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+run 20.48 us
+
+# FFFE00 (4FFFE00)
+force /xwr_sit5359_interface/tm_dac_value_i 0x000ffff
+force /xwr_sit5359_interface/tm_dac_value_wr_i 1,0 16 ns
+run 20.48 us
+
+
+run 1024 ns
+
+
+
+
+run 128 ns
+
+
+
--- a/hdl/sim/sit5359_tst/vlog.opt
+++ b/hdl/sim/sit5359_tst/vlog.opt
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_lm32/src
+incdir+../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi
+
+
--- a/hdl/sim/sit5359_tst/wave.tcl
+++ b/hdl/sim/sit5359_tst/wave.tcl
+onerror {resume}
+quietly WaveActivateNextPane {} 0
+add wave -noupdate /xwr_sit5359_interface/g_simulation
+add wave -noupdate /xwr_sit5359_interface/clk_sys_i
+add wave -noupdate /xwr_sit5359_interface/rst_n_i
+add wave -noupdate /xwr_sit5359_interface/tm_dac_value_i
+add wave -noupdate /xwr_sit5359_interface/tm_dac_value_wr_i
+add wave -noupdate /xwr_sit5359_interface/scl_pad_oen_o
+add wave -noupdate /xwr_sit5359_interface/sda_pad_oen_o
+add wave -noupdate /xwr_sit5359_interface/scl_pad_i
+add wave -noupdate /xwr_sit5359_interface/sda_pad_i
+add wave -noupdate /xwr_sit5359_interface/slave_i
+add wave -noupdate /xwr_sit5359_interface/slave_i.dat
+add wave -noupdate /xwr_sit5359_interface/slave_o
+add wave -noupdate /xwr_sit5359_interface/slave_o.dat
+add wave -noupdate -divider regs
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/U_WB_Slave/sit5359_cr_i2c_addr_int
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/U_WB_Slave/sit5359_cr_clk_div_int
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/U_WB_Slave/sit5359_cr_spll_en_int
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/U_WB_Slave/sit5359_cr_osc_oe_int
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/rfreq_new_p
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/rfreq_current
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/rfreq_new
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/i2c_tick
+add wave -noupdate /xwr_sit5359_interface/U_Wrapped_sit5359/rfreq_adj_scaled
+TreeUpdate [SetDefaultTree]
+WaveRestoreCursors {{Cursor 1} {3368000 ps} 1} {{Cursor 2} {6168000 ps} 1} {{Cursor 3} {8968000 ps} 1} {{Cursor 4} {11768000 ps} 1} {{Cursor 5} {14568000 ps} 1} {{Cursor 6} {17368000 ps} 1} {{Cursor 7} {91048000 ps} 0} {{Cursor 8} {352000 ps} 0}
+quietly wave cursor active 7
+configure wave -namecolwidth 469
+configure wave -valuecolwidth 75
+configure wave -justifyvalue left
+configure wave -signalnamewidth 0
+configure wave -snapdistance 10
+configure wave -datasetprefix 0
+configure wave -rowmargin 4
+configure wave -childrowmargin 2
+configure wave -gridoffset 0
+configure wave -gridperiod 1
+configure wave -griddelta 40
+configure wave -timeline 0
+configure wave -timelineunits ps
+update
+WaveRestoreZoom {0 ps} {21749084 ps}
--- a/hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
+++ b/hdl/sim/spec7_ref_design/VCom_spec7_wr_ref_top_Functional.tcl
@@ -33,6 +33,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_crc32_pkg.vh
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/escape_detector.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/escape_inserter.vhd
@@ -60,11 +61,11 @@ vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwrf_loopback/lbk_wi
 vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_sampler.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
-vcom -explicit -93 -work work ../../board/even_odd_det.vhd
 vcom -explicit -93 -work work ../../top/spec7_ref_design/gen_10mhz.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
 vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
@@ -83,6 +84,7 @@ vcom -explicit -93 -work work ../../wr-cores/modules/timing/pulse_stamper_sync.v
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_softpll_ng/spll_aligner.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/dropping_buffer.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
@@ -101,6 +103,7 @@ vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wish
 vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
+vcom -explicit -93 -work work ../../wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
 vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
 vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
 vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd

--- a/hdl/syn/spec7_ref_design/proj_file_list.txt
+++ b/hdl/syn/spec7_ref_design/proj_file_list.txt
@@ -33,6 +33,7 @@
 ../../wr-cores/modules/wr_endpoint/ep_pcs_tbi_mdio_wb.vhd
 ../../wr-cores/modules/wr_endpoint/ep_registers_pkg.vhd
 ../../wr-cores/modules/wr_pps_gen/pps_gen_wb.vhd
+../../wr-cores/modules/wr_sit5359_interface/sit5359_regs_pkg.vhd
 ../../wr-cores/modules/wr_softpll_ng/softpll_pkg.vhd
 ../../wr-cores/modules/wr_streamers/escape_detector.vhd
 ../../wr-cores/modules/wr_streamers/escape_inserter.vhd
@@ -60,11 +61,11 @@
 ../../wr-cores/modules/timing/dmtd_sampler.vhd
 ../../wr-cores/modules/wr_endpoint/ep_wishbone_controller.vhd
 ../../wr-cores/modules/wr_mini_nic/minic_wbgen2_pkg.vhd
+../../wr-cores/modules/wr_sit5359_interface/sit5359_if_wb.vhd
 ../../wr-cores/modules/wr_softpll_ng/spll_wbgen2_pkg.vhd
 ../../wr-cores/modules/wr_streamers/wr_streamers_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_diags_wb.vhd
 ../../wr-cores/modules/wrc_core/wrc_syscon_wb.vhd
-../../board/even_odd_det.vhd
 ../../top/spec7_ref_design/gen_10mhz.vhd
 ../../wr-cores/ip_cores/general-cores/modules/common/gc_async_counter_diff.vhd
 ../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer.vhd
@@ -83,6 +84,7 @@
 ../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
 ../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
 ../../wr-cores/modules/wr_pps_gen/wr_pps_gen.vhd
+../../wr-cores/modules/wr_sit5359_interface/wr_sit5359_interface.vhd
 ../../wr-cores/modules/wr_softpll_ng/spll_aligner.vhd
 ../../wr-cores/modules/wr_streamers/dropping_buffer.vhd
 ../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
@@ -101,6 +103,7 @@
 ../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
 ../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
 ../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
+../../wr-cores/modules/wr_sit5359_interface/xwr_sit5359_interface.vhd
 ../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
 ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
 ../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd

--- a/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
+++ b/hdl/top/spec7_ref_design/spec7_wr_ref_top.vhd
@@ -162,6 +162,12 @@ entity spec7_wr_ref_top is
    -- blink 1-PPS.
    led_pps_o          : out std_logic;

+    ---------------------------------------------------------------------------
+    -- I2C SiTime5359 Reference Oscillator
+    ---------------------------------------------------------------------------
+    -- sit5359_sda : inout std_logic;  -- Temporary routed to XM105 J1 pin 2, fmc_la10_p
+    -- sit5359_scl : inout std_logic;  -- Temporary routed to XM105 J1 pin 4, fmc_la10_n
+
    ---------------------------------------------------------------------------
    -- EEPROM interface
    ---------------------------------------------------------------------------
@@ -586,6 +592,9 @@ AXI2WB : xwb_axi4lite_bridge
      sfp_tx_disable_o    => sfp_tx_disable_o,
      sfp_los_i           => sfp_los_i,

+      sit5359_sda         => fmc_la10_p,  -- sit5359_sda,
+      sit5359_scl         => fmc_la10_n,  -- sit5359_scl,
+
      eeprom_scl          => scl_b,
      eeprom_sda          => sda_b,


--- a/wr-cores @ 55007fa1
+++ b/wr-cores @ 55007fa1
-Subproject commit 06448c066a65d2221c9eefeed22d45b300a0dc25
+Subproject commit 55007fa1f97b70684a2d52cd7cfbb517db42c0a6