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SPEC7
Commit 5d6a0916 authored by Peter Jansweijer's avatar Peter Jansweijer
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Initial spec7_v3 xdc file

parent 71b16f5b
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hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
View file @ 5d6a0916
......@@ -3,9 +3,9 @@
# ---------------------------------------------------------------------------
# -- Local oscillators
# Bank 112 -- 125.000 MHz GTX reference
#set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
#set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
# Bank 111 -- 125.000 MHz GTX reference
#set_property PACKAGE_PIN AA6 [get_ports clk_125m_gtx_p_i]
#set_property PACKAGE_PIN AA5 [get_ports clk_125m_gtx_n_i]
# Bank 111 -- 125.000 MHz GTX reference
set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
......@@ -106,7 +106,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
# Bank 112 (GTX0, GTX1)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
......@@ -128,11 +128,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN V3 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN V4 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN U1 [get_ports sfp_txn_o]
set_property PACKAGE_PIN U2 [get_ports sfp_txp_o]
# Bank 111 (GTX0)
set_property PACKAGE_PIN AD7 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN AD8 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN AF7 [get_ports sfp_txn_o]
set_property PACKAGE_PIN AF8 [get_ports sfp_txp_o]
# Bank 35 (HP) VCCO - 1.8 V
# sfp detect
......@@ -263,10 +263,10 @@ set_property IOSTANDARD LVDS [get_ports be_clk_10m_n_o]
# 125MHz Reference Clock Out
# Bulls-Eye A05, A06 (connected to LTC6950)
# TX Spare GTX Out (Bank 112 GTX3)
# TX Spare GTX Out (Bank 111 GTX1)
# Bulls-Eye A07, A08
#set_property PACKAGE_PIN R2 [get_ports BE_TXP]
#set_property PACKAGE_PIN R1 [get_ports BE_TXN]
#set_property PACKAGE_PIN AF4 [get_ports BE_TXP]
#set_property PACKAGE_PIN AF3 [get_ports BE_TXN]
# ABSCAL_TXTS
# Bulls-Eye A09, A10
......@@ -318,10 +318,10 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ext_10m]
#set_property PACKAGE_PIN W6 [get_ports be_refclk_p]
#set_property PACKAGE_PIN W5 [get_ports be_refclk_n]
# RX Spare GTX Out (Bank 112 GTX3)
# RX Spare GTX Out (Bank 111 GTX1)
# Bulls-Eye B07, B08
#set_property PACKAGE_PIN T4 [get_ports be_rxp]
#set_property PACKAGE_PIN T3 [get_ports be_rxn]
#set_property PACKAGE_PIN AE6 [get_ports be_rxp]
#set_property PACKAGE_PIN AE5 [get_ports be_rxn]
# CLK_DMTD In (Debug purposes only)
# Bulls-Eye B09, B10
......@@ -639,17 +639,18 @@ set_property PACKAGE_PIN AD10 [get_ports fmc_la33_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la33_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la33_n]
# Bank 111 GTX
set_property PACKAGE_PIN AA6 [get_ports fmc_gbtclk0_m2c_p]
set_property PACKAGE_PIN AA5 [get_ports fmc_gbtclk0_m2c_n]
#set_property PACKAGE_PIN AD8 [get_ports fmc_dp0_m2c_p]
#set_property PACKAGE_PIN AD7 [get_ports fmc_dp0_m2c_n]
#set_property PACKAGE_PIN AF8 [get_ports fmc_dp0_c2m_p]
#set_property PACKAGE_PIN AF7 [get_ports fmc_dp0_c2m_n]
#set_property PACKAGE_PIN AE6 [get_ports fmc_dp1_m2c_p]
#set_property PACKAGE_PIN AE5 [get_ports fmc_dp1_m2c_n]
#set_property PACKAGE_PIN AF4 [get_ports fmc_dp1_c2m_p]
#set_property PACKAGE_PIN AF3 [get_ports fmc_dp1_c2m_n]
# Bank 112 GTX2, GTX3
set_property PACKAGE_PIN U6 [get_ports fmc_gbtclk0_m2c_p]
set_property PACKAGE_PIN U5 [get_ports fmc_gbtclk0_m2c_n]
#set_property PACKAGE_PIN V4 [get_ports fmc_dp0_m2c_p]
#set_property PACKAGE_PIN V3 [get_ports fmc_dp0_m2c_n]
#set_property PACKAGE_PIN U2 [get_ports fmc_dp0_c2m_p]
#set_property PACKAGE_PIN U1 [get_ports fmc_dp0_c2m_n]
#set_property PACKAGE_PIN T4 [get_ports fmc_dp1_m2c_p]
#set_property PACKAGE_PIN T3 [get_ports fmc_dp1_m2c_n]
#set_property PACKAGE_PIN R2 [get_ports fmc_dp1_c2m_p]
#set_property PACKAGE_PIN R1 [get_ports fmc_dp1_c2m_n]
# Bank 111 GTX2, GTX3
#set_property PACKAGE_PIN AC6 [get_ports fmc_dp2_m2c_p]
#set_property PACKAGE_PIN AC5 [get_ports fmc_dp2_m2c_n]
#set_property PACKAGE_PIN AE2 [get_ports fmc_dp2_c2m_p]
......
hdl/top/spec7_ref_design/spec7_wr_hpsec_top_v2.xdc 0 → 100644
View file @ 5d6a0916
This diff is collapsed.
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ 5d6a0916
......@@ -3,9 +3,9 @@
# ---------------------------------------------------------------------------
# -- Local oscillators
# Bank 112 -- 125.000 MHz GTX reference
set_property PACKAGE_PIN U6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN U5 [get_ports clk_125m_gtx_n_i]
# Bank 111 -- 125.000 MHz GTX reference
set_property PACKAGE_PIN AA6 [get_ports clk_125m_gtx_p_i]
set_property PACKAGE_PIN AA5 [get_ports clk_125m_gtx_n_i]
# Bank 111 -- 125.000 MHz GTX reference
#set_property PACKAGE_PIN W6 [get_ports clk_125m_gtx_p_i]
#set_property PACKAGE_PIN W5 [get_ports clk_125m_gtx_n_i]
......@@ -106,7 +106,7 @@ set_property IOSTANDARD LVCMOS18 [get_ports {pll_wr_mode_o[1]}]
# ---------------------------------------------------------------------------
# -- PCIe
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
# Bank 112 (GTX0, GTX1)
set_property PACKAGE_PIN AB3 [get_ports {rxn[0]}]
set_property PACKAGE_PIN AB4 [get_ports {rxp[0]}]
set_property PACKAGE_PIN AA1 [get_ports {txn[0]}]
......@@ -128,11 +128,11 @@ set_property IOSTANDARD LVCMOS18 [get_ports perst_n]
# -- SFP I/O for transceiver
# ---------------------------------------------------------------------------
# Bank 112 (GTX2)
set_property PACKAGE_PIN V3 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN V4 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN U1 [get_ports sfp_txn_o]
set_property PACKAGE_PIN U2 [get_ports sfp_txp_o]
# Bank 111 (GTX0)
set_property PACKAGE_PIN AD7 [get_ports sfp_rxn_i]
set_property PACKAGE_PIN AD8 [get_ports sfp_rxp_i]
set_property PACKAGE_PIN AF7 [get_ports sfp_txn_o]
set_property PACKAGE_PIN AF8 [get_ports sfp_txp_o]
# Bank 35 (HP) VCCO - 1.8 V
# sfp detect
......@@ -263,10 +263,10 @@ set_property IOSTANDARD LVDS [get_ports be_clk_10m_n_o]
# 125MHz Reference Clock Out
# Bulls-Eye A05, A06 (connected to LTC6950)
# TX Spare GTX Out (Bank 112 GTX3)
# TX Spare GTX Out (Bank 111 GTX1)
# Bulls-Eye A07, A08
#set_property PACKAGE_PIN R2 [get_ports BE_TXP]
#set_property PACKAGE_PIN R1 [get_ports BE_TXN]
#set_property PACKAGE_PIN AF4 [get_ports BE_TXP]
#set_property PACKAGE_PIN AF3 [get_ports BE_TXN]
# ABSCAL_TXTS
# Bulls-Eye A09, A10
......@@ -313,10 +313,10 @@ set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_ext_10m]
#set_property PACKAGE_PIN W6 [get_ports be_refclk_p]
#set_property PACKAGE_PIN W5 [get_ports be_refclk_n]
# RX Spare GTX Out (Bank 112 GTX3)
# RX Spare GTX Out (Bank 111 GTX1)
# Bulls-Eye B07, B08
#set_property PACKAGE_PIN T4 [get_ports be_rxp]
#set_property PACKAGE_PIN T3 [get_ports be_rxn]
#set_property PACKAGE_PIN AE6 [get_ports be_rxp]
#set_property PACKAGE_PIN AE5 [get_ports be_rxn]
# CLK_DMTD In (Debug purposes only)
# Bulls-Eye B09, B10
......@@ -634,17 +634,18 @@ set_property PACKAGE_PIN AD10 [get_ports fmc_la33_n]
set_property IOSTANDARD LVCMOS25 [get_ports fmc_la33_n]
#set_property DIFF_TERM TRUE [get_ports fmc_la33_n]
# Bank 111 GTX
set_property PACKAGE_PIN AA6 [get_ports fmc_gbtclk0_m2c_p]
set_property PACKAGE_PIN AA5 [get_ports fmc_gbtclk0_m2c_n]
#set_property PACKAGE_PIN AD8 [get_ports fmc_dp0_m2c_p]
#set_property PACKAGE_PIN AD7 [get_ports fmc_dp0_m2c_n]
#set_property PACKAGE_PIN AF8 [get_ports fmc_dp0_c2m_p]
#set_property PACKAGE_PIN AF7 [get_ports fmc_dp0_c2m_n]
#set_property PACKAGE_PIN AE6 [get_ports fmc_dp1_m2c_p]
#set_property PACKAGE_PIN AE5 [get_ports fmc_dp1_m2c_n]
#set_property PACKAGE_PIN AF4 [get_ports fmc_dp1_c2m_p]
#set_property PACKAGE_PIN AF3 [get_ports fmc_dp1_c2m_n]
# Bank 112 GTX2, GTX3
set_property PACKAGE_PIN U6 [get_ports fmc_gbtclk0_m2c_p]
set_property PACKAGE_PIN U5 [get_ports fmc_gbtclk0_m2c_n]
#set_property PACKAGE_PIN V4 [get_ports fmc_dp0_m2c_p]
#set_property PACKAGE_PIN V3 [get_ports fmc_dp0_m2c_n]
#set_property PACKAGE_PIN U2 [get_ports fmc_dp0_c2m_p]
#set_property PACKAGE_PIN U1 [get_ports fmc_dp0_c2m_n]
#set_property PACKAGE_PIN T4 [get_ports fmc_dp1_m2c_p]
#set_property PACKAGE_PIN T3 [get_ports fmc_dp1_m2c_n]
#set_property PACKAGE_PIN R2 [get_ports fmc_dp1_c2m_p]
#set_property PACKAGE_PIN R1 [get_ports fmc_dp1_c2m_n]
# Bank 111 GTX2, GTX3
#set_property PACKAGE_PIN AC6 [get_ports fmc_dp2_m2c_p]
#set_property PACKAGE_PIN AC5 [get_ports fmc_dp2_m2c_n]
#set_property PACKAGE_PIN AE2 [get_ports fmc_dp2_c2m_p]
......
hdl/top/spec7_ref_design/spec7_wr_ref_top_v2.xdc 0 → 100644
View file @ 5d6a0916
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