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SPEC7
Commit 71b16f5b authored by Peter Jansweijer's avatar Peter Jansweijer
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Use ODIV2 instead of a separate div2 FF

parent bba65ed6
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Showing with 143 additions and 149 deletions
hdl/board/xwrc_board_spec7.vhd
View file @ 71b16f5b
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hdl/top/spec7_ref_design/spec7_wr_hpsec_top.xdc
View file @ 71b16f5b
......@@ -23,7 +23,7 @@ create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_port
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_dmtd_reg/Q]
# Set divide by 2 property for generated clk_ref (former platform xilinx: g_phy_lpcalib = TRUE)
create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_clk_ref62m5_buf/O]
#create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_gtx_dedicated_clk/ODIV2]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
......@@ -40,7 +40,7 @@ create_clock -period 100.000 -name be_clk_ext_10m -waveform {0.000 50.000} [get_
set_clock_groups -asynchronous \
-group clk_125m_gtx \
-group clk_ref_62m5_div2 \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
......@@ -49,15 +49,15 @@ set_clock_groups -asynchronous \
-group be_clk_ext_10m \
-group clk_ext_mul
# clk_ref_62m5_div2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
# clk_125m_gtx_odiv2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
# Setup requirement at edge 8, hold requirement at edge 7
# See also:
# https://www.xilinx.com/video/hardware/timing-exception-multicycle-path-constraints.html
# See: "Multicycle Path and Positive phase shift" (due to the clk_ref_62m5_div2 to clk_500 delay through MMCME2_ADV)
set_multicycle_path 2 -setup -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 1 -hold -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
# See: "Multicycle Path and Positive phase shift" (due to the clk_125m_gtx_odiv2 to clk_500 delay through MMCME2_ADV)
set_multicycle_path 2 -setup -from [get_clocks clk_125m_gtx_odiv2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
......
hdl/top/spec7_ref_design/spec7_wr_ref_top.xdc
View file @ 71b16f5b
......@@ -23,7 +23,7 @@ create_clock -period 8.000 -name clk_125m_dmtd -waveform {0.000 4.000} [get_port
create_generated_clock -name clk_125m_dmtd_div2 -source [get_ports clk_125m_dmtd_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/clk_dmtd_reg/Q]
# Set divide by 2 property for generated clk_ref (former platform xilinx: g_phy_lpcalib = TRUE)
create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_clk_ref62m5_buf/O]
#create_generated_clock -name clk_ref_62m5_div2 -source [get_ports clk_125m_gtx_p_i] -divide_by 2 [get_pins cmp_xwrc_board_spec7/cmp_gtx_dedicated_clk/ODIV2]
# Set 10 -> 62.5 MHz (*25 /4) generated clk_ext_mul (former platform xilinx: g_direct_dmtd = TRUE)
#create_generated_clock -name clk_ext_mul -source [get_pins cmp_xwrc_board_spec7/clk_ext_10m] -multiply 25 -divide 4 [get_pins cmp_xwrc_board_spec7/gen_ext_ref_pll.mmcm_adv_inst/CLKOUT0]
......@@ -40,7 +40,7 @@ create_clock -period 100.000 -name be_clk_ext_10m -waveform {0.000 50.000} [get_
set_clock_groups -asynchronous \
-group clk_125m_gtx \
-group clk_ref_62m5_div2 \
-group clk_125m_gtx_odiv2 \
-group clk_125m_dmtd \
-group clk_125m_dmtd_div2 \
-group RXOUTCLK \
......@@ -49,15 +49,15 @@ set_clock_groups -asynchronous \
-group be_clk_ext_10m \
-group clk_ext_mul
# clk_ref_62m5_div2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
# clk_125m_gtx_odiv2 = 16 ns = 8 clock periods of clk_500m which has 2 ns period
# Setup requirement at edge 8, hold requirement at edge 7
# See also:
# https://www.xilinx.com/video/hardware/timing-exception-multicycle-path-constraints.html
# See: "Multicycle Path and Positive phase shift" (due to the clk_ref_62m5_div2 to clk_500 delay through MMCME2_ADV)
set_multicycle_path 2 -setup -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 1 -hold -from [get_clocks clk_ref_62m5_div2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_ref_62m5_div2]
# See: "Multicycle Path and Positive phase shift" (due to the clk_125m_gtx_odiv2 to clk_500 delay through MMCME2_ADV)
set_multicycle_path 2 -setup -from [get_clocks clk_125m_gtx_odiv2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 1 -hold -from [get_clocks clk_125m_gtx_odiv2] -to [get_clocks "*clk_500m*"]
set_multicycle_path 3 -setup -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
set_multicycle_path 2 -hold -start -from [get_clocks "*clk_500m*"] -to [get_clocks clk_125m_gtx_odiv2]
# Set BMM_INFO_DESIGN property to avoid ERROR during "Write Bitstream"
set_property BMM_INFO_DESIGN spec7_wr_ref_top.bmm [current_design]
......
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