# Convert the "mem" to a "bram"(a format used by the White Rabbit "memory_loader_pkg.vhd")
do ../../../sw/scripts/mem2bram.tcl lm32_wrpc_memory 131072
# Now a fresh "lm32_wrpc_memory.bram" is in place for simulation and is loaded into xwb_dpram
# Note that -novopt causes No Optimization (some internal signals might get non-vivible by optimization)
# Note that "-L unisim" is needed to find the primitive "BSCANE2" thta is instantiated in "$LM32_Sources/platform/kintex7/jtag_tap.v "
#suppress warning Warning: (vsim-151) NUMERIC_STD.TO_INTEGER: Value <> is not in bounds of NATURAL.
#suppress warning Warning: (vsim-8684) No drivers exist on out port <blabla>
#vsim -G/spec7_write_top/g_simulation=$g_simulation -G/spec7_write_top/g_dpram_initf=lm32_wrpc_memory.bram -t ps -L unisim -lib work work.spec7_write_top
# -novopt is now deprecated
#vsim -voptargs="+acc" -novopt
# Note that -novopt can cause errors like:
# "Error: (vsim-8346) .../blabla.vhd(516): VHDL component port was not found because Verilog port 'D_ACK_I' was mapped to the extended identifier '\D_ACK_I\'."
# "Error: (vsim-3935) .../blabla.vhd(177): Port 'I_CYC_O' not found in the connected module."
