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Commit dc9c439f authored by Peter Jansweijer's avatar Peter Jansweijer
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Merged reference and write design; now both in a single spec7_ref_design

parent f11846a0
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hdl/spec7_ref_design/sim/VCom_spec7_wr_ref_top_Functional.tcl
View file @ dc9c439f
......@@ -6,6 +6,7 @@
#vcom -explicit -93 -work work ../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_sync.vhd
......@@ -39,10 +40,10 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_diags_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/top/spec7_ref_design/pll_62m5_500m.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/axi/axi4_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
......@@ -79,7 +80,7 @@ vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wish
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwrf_mux.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_sampler.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/pulse_stamper_sync.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
......@@ -89,12 +90,11 @@ vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/dropping_buffe
vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/top/spec7_ref_design/gen_10mhz.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/wb_axi4lite_bridge.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
......@@ -105,14 +105,16 @@ vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genr
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_phase_meas.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
vcom -explicit -93 -work work ../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
vcom -explicit -93 -work work ../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/fabric/xwb_fabric_source.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/timing/dmtd_phase_meas.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
vcom -explicit -93 -work work ../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
......
hdl/spec7_ref_design/sim/modelsim.ini
View file @ dc9c439f
......@@ -13,8 +13,8 @@ INIVersion = "2019.4"
[Library]
others=$VHDLLIBS/v2019.2/modelsim.ini
work = spec7.lib
work = spec7.lib
[DefineOptionset]
; Define optionset entries for the various compilers, vmake, and vsim.
; These option sets can be used with the "-optionset <optionsetname>" syntax.
......
hdl/spec7_ref_design/syn/proj_file_list.txt
View file @ dc9c439f
......@@ -4,6 +4,7 @@
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.xdc
../../wr-cores/ip_cores/general-cores/modules/common/gc_dec_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_edge_detect.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_reset.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_serial_dac.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync.vhd
......@@ -37,10 +38,10 @@
../../wr-cores/modules/wrc_core/wrc_syscon_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/gtx_comma_detect_lp.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/whiterabbit_gtxe2_channel_wrapper_gt_lp.vhd
../../wr-cores/top/spec7_ref_design/pll_62m5_500m.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_hdr_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/axi/axi4_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_crc_gen.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_enc_8b10b.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_extend_pulse.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_pulse_synchronizer2.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_sync_ffs.vhd
......@@ -72,11 +73,12 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/common/inferred_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/memory_loader_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/gc_shiftreg.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/wb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/modules/fabric/xwrf_mux.vhd
../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
../../wr-cores/modules/timing/dmtd_sampler.vhd
../../wr-cores/modules/timing/pulse_stamper_sync.vhd
../../wr-cores/modules/wr_endpoint/endpoint_pkg.vhd
../../wr-cores/modules/wr_mini_nic/minic_wb_slave.vhd
......@@ -86,12 +88,11 @@
../../wr-cores/modules/wr_streamers/fixed_latency_ts_match.vhd
../../wr-cores/modules/wr_streamers/ts_restore_tai.vhd
../../wr-cores/modules/wrc_core/xwrc_diags_wb.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/top/spec7_ref_design/gen_10mhz.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_slave_fsm.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_narrow.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_stream_widen.vhd
../../wr-cores/ip_cores/etherbone-core/hdl/eb_slave_core/eb_tx_mux.vhd
../../wr-cores/ip_cores/general-cores/modules/axi/axi4lite_wb_bridge/wb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/common/gc_frequency_meter.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/common/generic_shiftreg_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
......@@ -102,14 +103,16 @@
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/xwb_sdb_crossbar.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_gpio_port/xwb_gpio_port.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/xwb_onewire_master.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/timing/dmtd_with_deglitcher.vhd
../../wr-cores/modules/wr_endpoint/endpoint_private_pkg.vhd
../../wr-cores/modules/wr_pps_gen/xwr_pps_gen.vhd
../../wr-cores/modules/wrc_core/wrcore_pkg.vhd
../../wr-cores/platform/xilinx/wr_gtp_phy/family7-gtx-lp/wr_gtx_phy_family7_lp.vhd
../../wr-cores/platform/xilinx/wr_xilinx_pkg.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/modules/fabric/xwb_fabric_sink.vhd
../../wr-cores/modules/fabric/xwb_fabric_source.vhd
../../wr-cores/modules/timing/dmtd_phase_meas.vhd
../../wr-cores/modules/wr_endpoint/ep_autonegotiation.vhd
../../wr-cores/modules/wr_endpoint/ep_clock_alignment_fifo.vhd
../../wr-cores/modules/wr_endpoint/ep_leds_controller.vhd
......@@ -186,7 +189,7 @@
# bmm not supported by hdlmake? Need to add it manually...
../../wr-cores/platform/xilinx/wr_pcie/processing_system_pcie.tcl
../../wr-cores/ip_cores/general-cores/modules/pci/xilinx/processing_system_pcie.bd
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
......
hdl/spec7_ref_design/syn/proj_properties.tcl
View file @ dc9c439f
#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_dpram_initf=$lm32_wrpc_initf"
}
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
#
# projetc_properties.tcl
# This file contains the general project properties such as the project name and
# the directory where Vivado is doing it's job
#
# ====================================================
# ====================================================
# SELECT DESIGN TO BUILD:
# ====================================================
# Reference Design (using fmc-dio-5chttla => https://ohwr.org/project/fmc-dio-5chttla/wikis/home)
# WRITE / HPSEC Design (using Bulls-Eye connector)
set spec7_design spec7_ref_top
#set spec7_design spec7_write_top
# ====================================================
# ====================================================
# SELECT DEVICE TO BUILD:
# ====================================================
# SPEC7 equipped with ZYNQ XC7Z035FBG676-1 (speed grade -1 has lowest performance)
set device xc7z035fbg676-1
#set device xc7z030fbg676-1
# ====================================================
# ====================================================
# SELECT PPS SINLGE / DIFFERENTIAL:
# ====================================================
# When Bulls-Eye connector is used as input (WRITE and
# HPSEC).
# Differential: B01/B02 (LVDS)
# Single-ended: B11 (TTL, 5V tolerant)
set pps_in "single"
#set pps_in "diff"
# ====================================================
set proj_name spec7_wr_ref_top
set proj_dir work
set script_dir [pwd]/../../../sw/scripts
set lm32_wrpc_initf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.bram
set lm32_wrpc_elf [pwd]/../../../sw/precompiled/wrps-sw_spec7/wrc.elf
set lm32_wrpc_instpath "lm32_wrpc_memory"
# update revision except when argument "no_update_revison" is passed (as for example by viv_do_programm.tcl)
if {$argc == 0 || $argv != "no_update_revision"} {
source $script_dir/revisiondate.tcl
set generics "g_design=$spec7_design \
g_use_pps_in=$pps_in \
g_dpram_initf=$lm32_wrpc_initf"
}
sw/scripts/viv_do_all.tcl
View file @ dc9c439f
......@@ -30,6 +30,7 @@ create_project -force -part $device $proj_name ./$proj_dir
# work_directory is *full* path project directory.
# Vivado doesn't seem to accept relative paths!?
set work_directory [get_property DIRECTORY [current_project]]
set_property default_lib work [current_project]
# Create a hdl_version.xdc file to set the bitfile USERID to the revision date/version
set revision_log_file "revisiondate_log.txt"
......@@ -91,13 +92,10 @@ foreach line $content {
# Read constraints file if any
# puts "xdc"
read_xdc -verbose $line
} elseif {[string range $line $line_length-4 $line_length] == ".tcl"} {
source $line
# making wrapper, using variable $design_name provided in xilinx TCL scripts.
make_wrapper -files [get_files ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/$design_name.bd] -top
add_files -norecurse ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/hdl/${design_name}_wrapper.vhd
set_property library work [get_files ./$proj_dir/$proj_name.srcs/sources_1/bd/$design_name/hdl/${design_name}_wrapper.vhd]
close_bd_design [get_bd_designs $design_name]
} elseif {[string range $line $line_length-3 $line_length] == ".bd"} {
# puts "xilinx bd"
read_bd $line
make_wrapper -files [get_files $line] -top -import
} elseif {[string range $line $line_length-4 $line_length] == ".bmm"} {
# Set pointer to bmm file if any
# puts "bmm"
......@@ -129,7 +127,7 @@ close_design
# Generate a new name for .bit and .mmi file and copy to project directory.
# Create a senible name including date and time
set bitfile_name ${proj_name}_[string range $device 3 6]_[clock format [clock seconds] -format %y%m%d_%H%M]
set bitfile_name ${spec7_design}_[string range $device 3 6]_[clock format [clock seconds] -format %y%m%d_%H%M]
file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ../${bitfile_name}.bit
file copy ./${proj_name}.mmi ../${bitfile_name}.mmi
......
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