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SPEC7
Commit 00380314 authored by Pascal Bos's avatar Pascal Bos
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Added buildname stamping to elf-included bitfiles, fixed duplicate in proj_file_list 

updated wr-cores
parent a50bdd3b
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Showing with 3 additions and 5 deletions
hdl/spec7_ref_design/syn/proj_file_list.txt
View file @ 00380314
......@@ -80,7 +80,6 @@
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/generic/generic_async_fifo_dual_rst.vhd
../../wr-cores/ip_cores/general-cores/modules/genrams/xilinx/generic_dpram.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_axi4lite_bridge/xwb_axi4lite_bridge.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_crossbar/sdb_rom.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_onewire_master/wb_onewire_master.vhd
../../wr-cores/ip_cores/general-cores/modules/wishbone/wb_spi/wb_spi.vhd
......@@ -189,4 +188,4 @@
../../wr-cores/top/spec7_ref_design/spec7_wr_ref_top.bmm
# include hardware version ID un FPGA USER_ID register:
hdl_version.xdc
\ No newline at end of file
hdl_version.xdc
wr-cores @ 156e8d6b
Subproject commit b7f11baf76b84ea00af1d57763a42d54808dface
Subproject commit 156e8d6b4603cfe42b35e77d7050cae26da0e050
sw/scripts/viv_do_all.tcl
View file @ 00380314
......@@ -134,5 +134,4 @@ set bitfile_name ${proj_name}_[string range $device 3 6]_[clock format [clock se
file copy ./work/${proj_name}.runs/impl_1/${proj_name}.bit ../${bitfile_name}.bit
file copy ./${proj_name}.mmi ../${bitfile_name}.mmi
# ------------------------------------------------------------------------------
exec updatemem -meminfo ./${proj_name}.mmi -data ${lm32_wrpc_elf} -bit ./work/${proj_name}.runs/impl_1/${proj_name}.bit -proc ${lm32_wrpc_instpath} -out ../${bitfile_name}_elf.bit -force
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