Commits · 2953274ce3670eed240ff6d06b8e445bb9fdf1ca · Projects / Simple PCIe FMC carrier SPEC

01 Jul, 2021 5 commits
- update CHANGELOG · 2953274c
  Federico Vaga authored Jul 01, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  2953274c
- bld:ci: add extra build against different Linux versions · 9172eda1
  Federico Vaga authored Jul 01, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  9172eda1
- bld: cheby should be in PATH · caa89d2d
  Federico Vaga authored Jul 01, 2021
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  caa89d2d
- bld:ci: do not clone full history · 2a89b6d4
  Federico Vaga authored Jul 01, 2021
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  2a89b6d4
- bld: use dedicated image to build · 16e417ac
  Federico Vaga authored Jun 30, 2021
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  16e417ac
30 Jun, 2021 3 commits
- bld: check code in specific container · ebdc8a21
  Federico Vaga authored Jun 30, 2021
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  ebdc8a21
- bld: move dependencies cloning to build target · c27911bc
  Federico Vaga authored Jun 30, 2021
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  c27911bc
- doc: build documentation in CI · 1fcfae80
  Federico Vaga authored Jun 30, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  1fcfae80
18 May, 2021 7 commits
- add REUSE badge · 502c6192
  Federico Vaga authored May 18, 2021
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  502c6192
- bld: fix DKMS creation · 8f87b9f3
  Federico Vaga authored May 18, 2021
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  8f87b9f3
- add license to readthedocs file' · df79326b
  Federico Vaga authored May 18, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  df79326b
- add .gitlab-ci.yml · 0b68859a
  Federico Vaga authored Sep 23, 2019
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  0b68859a
- bld: update licenses · 2803dc03
  Federico Vaga authored Nov 10, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  2803dc03
- sw: check that FPGA is programmed before loading devices · aa9df531
  Federico Vaga authored May 18, 2021
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- sw: move GN4124 bit fields descriptions to its header file · f60a9aa2
  Federico Vaga authored May 18, 2021
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  f60a9aa2
26 Nov, 2020 5 commits
- doc: extract version from git · 61fc00f5
  Federico Vaga authored Nov 26, 2020
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  61fc00f5
- doc: get version from conf.py · 0afcb32e
  Federico Vaga authored Nov 26, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  0afcb32e
- doc: show only one version of the fixed fields · 4c57158a
  Federico Vaga authored Nov 26, 2020
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  4c57158a
- doc: change theme to RTD · 9831b3d9
  Federico Vaga authored Nov 26, 2020
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  9831b3d9
- doc: add RTD integration · 9da465f6
  Federico Vaga authored Nov 26, 2020
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  9da465f6
25 Nov, 2020 3 commits
- doc: add python requirement file · 6fd19aae
  Federico Vaga authored Nov 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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- update licenses · fc56f159
  Federico Vaga authored Nov 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  fc56f159
- bld: ignore more files · d370141f
  Federico Vaga authored Nov 25, 2020
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  d370141f
23 Nov, 2020 4 commits

Merge tag 'v2.1.4' into develop · 73be24b8

Federico Vaga authored Nov 23, 2020

2.1.4 - 2020-11-23
==================
Fixed
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- sw: SPEC driver detects the correct FLASH only on drivers reload

73be24b8

Merge branch 'release/v2.1.4' into master · fd485c8b
Federico Vaga authored Nov 23, 2020

fd485c8b
update CHANGELOG · 54c604a0
Federico Vaga authored Nov 23, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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54c604a0

Enable FPGA-FLASH mode to identify SPI Flash chip correctly · e7d43f1f

Mamta Shukla authored Nov 23, 2020

The SPI connection to the FLASH has 3 different configuration: FPGA-FLASH, GENNUM-FLASH, GENNUM-FPGA
to program the FPGA from the FEC ,GENNUM-FGPA mode is needed, but to use the MTD driver
FPGA-FLASH mode is required.
Hence, enforce bootsel(GPIO) to FPGA-FLASH mode after firmware is loaded in GENNUM-FPGA mode and before
initiating SPI communication & initializing the FPGA through spec_fpga_init(spec_gn412x) , to identify
flash chip id from spi-ocores and m25p80 driver.
Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>
Suggested-by: Federico Vaga <federico.vaga@cern.ch>

e7d43f1f

16 Nov, 2020 6 commits
- Merge tag 'v2.1.3' into develop · 00fa08a6
  Federico Vaga authored Nov 16, 2020
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2.1.3 - 2020-11-16
==================
Added
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- sw,drv: module parameter to ignore bitstream version check (for
development
  or debug)
  - sw: the spec-firmware-version tool can dump build-info

Fixed
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- hdl: DMA failures fixed with thight timing constraints
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  00fa08a6
- Merge branch 'release/v2.1.3' into master · c3ffa27d
  Federico Vaga authored Nov 16, 2020
  
  c3ffa27d
- update CHANGELOG · f8c17949
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f8c17949
- sw:tools: fix help message · ad167e31
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  ad167e31
- Merge remote-tracking branch 'ohwr/bugfix/v2.1.3' into develop · 3acff59a
  Federico Vaga authored Nov 16, 2020
  
  3acff59a
- sw:tool: print build information · f24b4863
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f24b4863
13 Nov, 2020 3 commits
- Bump minor version · a2ae2c94
  Tristan Gingold authored Nov 13, 2020
  
  a2ae2c94
- Tighten timing constraints. · 92c202a1
  Tristan Gingold authored Nov 13, 2020
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They were too relaxed, in particular the register sync which is used by
FIFOs.
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  92c202a1
- Update gn4124-core · ac968edf
  Tristan Gingold authored Nov 13, 2020
  
  ac968edf
12 Nov, 2020 4 commits
- sw: format the output for humans and machines · 8e770510
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  8e770510
- sw: add missing cap. in singleline · 09c7e423
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  09c7e423
- sw: fix verbose level · f1c0cdb8
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f1c0cdb8
- sw:drv: add module parameter to ignore the FPGA configuration version · 63beeae3
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  63beeae3