Commit c3ffa27d authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v2.1.3' into master

parents bccad6f3 f8c17949
......@@ -6,6 +6,18 @@
Changelog
=========
2.1.3 - 2020-11-16
==================
Added
-----
- sw,drv: module parameter to ignore bitstream version check (for development
or debug)
- sw: the spec-firmware-version tool can dump build-info
Fixed
-----
- hdl: DMA failures fixed with thight timing constraints
2.1.2 - 2020-11-09
==================
Fixed
......
......@@ -241,6 +241,12 @@ attributes. Here we focus only on those.
Module Parameters
-----------------
``version_ignore`` [R]
When set to 1 (enable) at ``insmod(2)`` time, it forces the driver
to ignore the version declared in the FPGA bitstream. Particularly
usefull during development or debugging across major or minor
version. By default it is set to 0 (disable).
``user_dma_coherent_size`` [RW]
It sets the maximum size for a coherent DMA memory allocation. A
change to this value is applied on ``open(2)``
......
Subproject commit c629364388453726da401909b5154306ab4e6930
Subproject commit 461b30fe1f5e4e0c99f2265cdbf5843d31e31a4b
......@@ -604,7 +604,7 @@ begin -- architecture top
metadata_data <= x"53504543";
when x"2" =>
-- Version (0xVVMMmmmm VV: version, MM: major, mmmm: minor)
metadata_data <= x"02010001";
metadata_data <= x"02010003";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
......@@ -668,8 +668,15 @@ begin -- architecture top
rst_gbl_n <= rst_62m5_sys_n and (not csr_rst_gbl);
-- reset for DDR including soft reset.
-- This is treated as async and will be re-synced by the DDR controller
ddr_rst <= not rst_333m_ddr_n or csr_rst_gbl;
-- Add a FF to ease timing.
process(clk_333m_ddr, rst_333m_ddr_n, csr_rst_gbl)
begin
if rst_333m_ddr_n = '0' or csr_rst_gbl = '1' then
ddr_rst <= '1';
elsif rising_edge (clk_333m_ddr) then
ddr_rst <= not rst_333m_ddr_n or csr_rst_gbl;
end if;
end process;
rst_csr_app_n <= not (csr_rst_gbl or csr_rst_app);
......
......@@ -157,25 +157,12 @@ NET "inst_spec_base/clk_125m_ref" TNM_NET = ref_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/sys_clk" TNM_NET = pci_clk;
NET "*/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/io_clk" TNM_NET = pci_clk;
TIMEGRP "sys_grp" = "sys_clk" "ref_clk";
# Note: sys and ref are always related
TIMEGRP "sys_sync_ffs" = "sync_ffs" EXCEPT "sys_grp";
TIMEGRP "pci_sync_ffs" = "sync_ffs" EXCEPT "pci_clk";
# sys <-> pci
TIMESPEC TS_sys_to_pci = FROM sys_clk TO pci_clk 5 ns DATAPATHONLY;
TIMESPEC TS_pci_to_sys = FROM pci_clk TO sys_clk 5 ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_ffs
NET "*/gc_sync_ffs_in" TNM = FFS "sync_ffs";
TIMESPEC TS_sys_sync_ffs = FROM sys_grp TO "sys_sync_ffs" TIG;
TIMESPEC TS_pci_sync_ffs = FROM pci_clk TO "pci_sync_ffs" TIG;
# Exceptions for crossings via gc_sync_register
NET "*/gc_sync_register_in[*]" TNM = FFS "sync_reg";
TIMEGRP "sys_sync_reg" = "sync_reg" EXCEPT "sys_grp";
TIMEGRP "pci_sync_reg" = "sync_reg" EXCEPT "pci_clk";
TIMESPEC TS_ref_sync_reg = FROM ref_clk TO "sys_sync_reg" 8ns DATAPATHONLY;
TIMESPEC TS_sys_sync_reg = FROM sys_clk TO "sys_sync_reg" 16ns DATAPATHONLY;
TIMESPEC TS_pci_sync_reg = FROM pci_clk TO "pci_sync_reg" 5ns DATAPATHONLY;
# ref <-> pci
TIMESPEC TS_ref_to_pci = FROM ref_clk TO pci_clk 5 ns DATAPATHONLY;
TIMESPEC TS_pci_to_ref = FROM pci_clk TO ref_clk 5 ns DATAPATHONLY;
......@@ -98,6 +98,16 @@ NET "inst_spec_base/clk_333m_ddr" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_infrastructure_inst/mcb_drp_clk_bufg_in" TNM_NET = ddr_clk;
NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk" TNM_NET = ddr_clk;
# Note: ref, sys and ddr are always related
# ddr <-> pci
TIMESPEC TS_ddr_to_pci = FROM ddr_clk TO pci_clk 3 ns DATAPATHONLY;
TIMESPEC TS_pci_to_ddr = FROM pci_clk TO ddr_clk 3 ns DATAPATHONLY;
# ddr <-> sys
TIMESPEC TS_ddr_to_sys = FROM ddr_clk TO sys_clk 3 ns DATAPATHONLY;
TIMESPEC TS_sys_to_ddr = FROM sys_clk TO ddr_clk 3 ns DATAPATHONLY;
# DDR does not use any sync modules
#TIMEGRP "ddr_sync_ffs" = "sync_ffs" EXCEPT "ddr_clk";
......@@ -109,20 +119,3 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
#TIMESPEC TS_ddr_sync_reg = FROM ddr_clk TO "ddr_sync_reg" 3ns DATAPATHONLY;
#TIMESPEC TS_ddr_sync_word = FROM sync_word TO ddr_clk 9ns DATAPATHONLY;
#---------------------------------------
# DMA
#---------------------------------------
NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
# Exceptions for crossings via gc_sync_word_* (3x multicycle)
NET "*/gc_sync_word_data[*]" TNM = FFS "sync_word";
TIMESPEC TS_sys_sync_word = FROM sync_word TO sys_clk 48ns DATAPATHONLY;
TIMESPEC TS_ref_sync_word = FROM sync_word TO ref_clk 24ns DATAPATHONLY;
# no gc_sync_word used in GN4124
#TIMESPEC TS_pci_sync_word = FROM sync_word TO pci_clk 15ns DATAPATHONLY;
......@@ -38,6 +38,16 @@
#define SPEC_META_BOM_VER_MASK 0x0000FFFF
#define SPEC_META_VERSION_MASK 0xFFFF0000
#ifndef BIT
#define BIT(_b) (1 << _b)
#endif
#define SPEC_META_CAP_VIC BIT(0)
#define SPEC_META_CAP_THERM BIT(1)
#define SPEC_META_CAP_SPI BIT(2)
#define SPEC_META_CAP_WR BIT(3)
#define SPEC_META_CAP_BLD BIT(4)
#define SPEC_META_CAP_DMA BIT(5)
/**
* struct spec_meta_id Metadata
*/
......
......@@ -26,6 +26,10 @@
#include "spec.h"
#include "spec-compat.h"
static int version_ignore = 0;
module_param(version_ignore, int, 0644);
MODULE_PARM_DESC(version_ignore,
"Ignore the version declared in the FPGA and force the driver to load all components (default 0)");
static int user_dma_coherent_size = 4 * 1024 * 1024;
module_param(user_dma_coherent_size, int, 0644);
MODULE_PARM_DESC(user_dma_coherent_size,
......@@ -60,16 +64,6 @@ enum spec_fpga_therm_offsets {
SPEC_FPGA_THERM_TEMP = SPEC_BASE_REGS_THERM_ID + 0x8,
};
enum spec_fpga_meta_cap_mask {
SPEC_META_CAP_VIC = BIT(0),
SPEC_META_CAP_THERM = BIT(1),
SPEC_META_CAP_SPI = BIT(2),
SPEC_META_CAP_WR = BIT(3),
SPEC_META_CAP_BLD = BIT(4),
SPEC_META_CAP_DMA = BIT(5),
};
static const struct debugfs_reg32 spec_fpga_debugfs_reg32[] = {
{
.name = "Application offset",
......@@ -1165,7 +1159,8 @@ static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
return false;
}
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_COMPAT) {
if (!version_ignore &&
(meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_COMPAT) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow version: %08x, expected: %08x\n",
meta->version, SPEC_META_VERSION_COMPAT);
......
......@@ -12,6 +12,7 @@
#include <getopt.h>
#include <libgen.h>
#include <errno.h>
#include <inttypes.h>
#include <sys/mman.h>
#include <sys/types.h>
#include <sys/stat.h>
......@@ -33,6 +34,7 @@ static void help(void)
"\t-p <PCIID>\n"
"\t-b print spec-base\n"
"\t-a print spec-application\n"
"\t-B print FPGA build information\n"
"\t-1 print on a single line\n"
"\t-V print version\n"
"\t-h print help\n",
......@@ -66,29 +68,121 @@ static void print_meta_id_one(struct spec_meta_id *rom)
SPEC_META_VERSION_MAJ(rom->version),
SPEC_META_VERSION_MIN(rom->version),
SPEC_META_VERSION_PATCH(rom->version));
if (verbose > 1) {
fprintf(stdout, ",%08x%08x%08x%08x,%s,%08x%08x%08x%08x",
if (verbose > 0) {
fprintf(stdout, "%08x,%08x,%08x%08x%08x%08x,%08x%08x%08x%08x",
rom->cap, rom->bom,
rom->src[0], rom->src[1], rom->src[2], rom->src[3],
bom_to_str(rom->bom),
rom->uuid[0], rom->uuid[1], rom->uuid[2], rom->uuid[3]);
}
fputc('\n', stdout);
}
static void print_meta_vendor(uint32_t vendor)
{
switch(vendor) {
case SPEC_META_VENDOR_ID:
fputs("CERN", stdout);
break;
default:
fprintf(stdout, "unknown (0x%08"PRIx32")", vendor);
break;
}
}
static void print_meta_device(uint32_t device)
{
switch(device) {
case SPEC_META_DEVICE_ID:
fputs("spec-base", stdout);
break;
default:
fprintf(stdout, "unknown (0x%08"PRIx32")", device);
break;
}
}
static const char *capability[] = {
"vic",
"thermometer",
"spi",
"white-rabbit",
"build-info",
"dma-engine",
};
static void print_meta_capabilities(uint32_t cap)
{
bool has_cap = false;
int i;
for (i = 0; i < 32; ++i) {
if (i < 6) { /* known bits */
if (cap & BIT(i)) {
fputs(capability[i], stdout);
fputs(", ", stdout);
has_cap = true;
}
} else {
if (cap & BIT(i))
fprintf(stdout, "unknown BIT(%d), ", i);
}
}
if (has_cap)
fputs("\b\b ", stdout);
}
#define SPEC_BASE_REGS_BUILDINFO 0x200UL
#define SPEC_BASE_REGS_BUILDINFO_SIZE 256
static int print_build_info(int fd)
{
char *bld;
char *bld_c;
bld = mmap(NULL, SPEC_BASE_REGS_BUILDINFO + SPEC_BASE_REGS_BUILDINFO_SIZE,
PROT_READ, MAP_SHARED, fd, 0);
if ((long)bld == -1) {
fputs("Failed while reading SPEC-BASE FPGA BUILD INFO\n",
stderr);
return -1;
}
fputs("build-info : \n ", stdout);
bld_c = bld + SPEC_BASE_REGS_BUILDINFO;
while (*bld_c != 0) {
fputc(*bld_c, stdout);
if (*bld_c == '\n')
fputs(" ", stdout);
bld_c++;
}
fputc('\n', stdout);
munmap(bld, SPEC_BASE_REGS_BUILDINFO + SPEC_BASE_REGS_BUILDINFO_SIZE);
return 0;
}
static void print_meta_id(struct spec_meta_id *rom)
{
fputc('\n', stdout);
fprintf(stdout, " vendor : 0x%08x\n", rom->vendor);
fprintf(stdout, " device : 0x%08x\n", rom->device);
fprintf(stdout, " version : %u.%u.%u\n",
fprintf(stdout, " vendor : ");
print_meta_vendor(rom->vendor);
fputc('\n', stdout);
fprintf(stdout, " device : ");
print_meta_device(rom->device);
fputc('\n', stdout);
fprintf(stdout, " version : %u.%u.%u\n",
SPEC_META_VERSION_MAJ(rom->version),
SPEC_META_VERSION_MIN(rom->version),
SPEC_META_VERSION_PATCH(rom->version));
if (verbose > 1) {
fprintf(stdout, " capabilities : ");
print_meta_capabilities(rom->cap);
fputc('\n', stdout);
if (verbose > 0) {
fprintf(stdout, " byte-order : %s\n", bom_to_str(rom->bom));
fprintf(stdout, " sources : %08x%08x%08x%08x\n",
rom->src[0], rom->src[1], rom->src[2], rom->src[3]);
fprintf(stdout, " capabilities : 0x%08x\n", rom->cap);
fprintf(stdout, " UUID : %08x%08x%08x%08x\n",
rom->uuid[0], rom->uuid[1],
rom->uuid[2], rom->uuid[3]);
......@@ -105,7 +199,7 @@ static int print_base_meta_id(int fd)
fputs("Failed while reading SPEC-BASE FPGA ROM\n", stderr);
return -1;
}
fputs("spec-base: ", stdout);
fputs("base: ", stdout);
if (singleline)
print_meta_id_one(rom);
else
......@@ -149,7 +243,7 @@ static int print_app_meta_id(int fd)
fputs("Failed while reading SPEC-APP FPGA ROM\n", stderr);
return -1;
}
fputs("spec-application: ", stdout);
fputs("application: ", stdout);
if (singleline)
print_meta_id_one(rom);
else
......@@ -162,7 +256,7 @@ static int print_app_meta_id(int fd)
#define PCIID_STR_LEN 16
int main(int argc, char *argv[])
{
bool base = false, app = false;
bool base = false, app = false, buildinfo = false;
int err;
int fd;
char path[128];
......@@ -176,7 +270,7 @@ int main(int argc, char *argv[])
if (err)
exit(EXIT_FAILURE);
while ((opt = getopt(argc, argv, "h?Vvp:ba1")) != -1) {
while ((opt = getopt(argc, argv, "h?Vvp:ba1B")) != -1) {
switch (opt) {
case 'h':
case '?':
......@@ -200,6 +294,9 @@ int main(int argc, char *argv[])
case '1':
singleline = true;
break;
case 'B':
buildinfo = true;
break;
}
}
if (strlen(pciid_str) == 0) {
......@@ -218,6 +315,8 @@ int main(int argc, char *argv[])
err = print_base_meta_id(fd);
if (app)
err = print_app_meta_id(fd);
if (buildinfo)
err = print_build_info(fd);
close(fd);
exit(err ? EXIT_FAILURE : EXIT_SUCCESS);
......
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