Commits · 0afcb32e2ad38aa2298ef9aeaefb5e2460cacf77 · Projects / Simple PCIe FMC carrier SPEC

26 Nov, 2020 4 commits
- doc: get version from conf.py · 0afcb32e
  Federico Vaga authored Nov 26, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  0afcb32e
- doc: show only one version of the fixed fields · 4c57158a
  Federico Vaga authored Nov 26, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  4c57158a
- doc: change theme to RTD · 9831b3d9
  Federico Vaga authored Nov 26, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  9831b3d9
- doc: add RTD integration · 9da465f6
  Federico Vaga authored Nov 26, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  9da465f6
25 Nov, 2020 3 commits
- doc: add python requirement file · 6fd19aae
  Federico Vaga authored Nov 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  6fd19aae
- update licenses · fc56f159
  Federico Vaga authored Nov 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  fc56f159
- bld: ignore more files · d370141f
  Federico Vaga authored Nov 25, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  d370141f
23 Nov, 2020 4 commits

Merge tag 'v2.1.4' into develop · 73be24b8

Federico Vaga authored Nov 23, 2020

2.1.4 - 2020-11-23
==================
Fixed
-----
- sw: SPEC driver detects the correct FLASH only on drivers reload

73be24b8

Merge branch 'release/v2.1.4' into master · fd485c8b
Federico Vaga authored Nov 23, 2020

fd485c8b
update CHANGELOG · 54c604a0
Federico Vaga authored Nov 23, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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54c604a0

Enable FPGA-FLASH mode to identify SPI Flash chip correctly · e7d43f1f

Mamta Shukla authored Nov 23, 2020

The SPI connection to the FLASH has 3 different configuration: FPGA-FLASH, GENNUM-FLASH, GENNUM-FPGA
to program the FPGA from the FEC ,GENNUM-FGPA mode is needed, but to use the MTD driver
FPGA-FLASH mode is required.
Hence, enforce bootsel(GPIO) to FPGA-FLASH mode after firmware is loaded in GENNUM-FPGA mode and before
initiating SPI communication & initializing the FPGA through spec_fpga_init(spec_gn412x) , to identify
flash chip id from spi-ocores and m25p80 driver.
Signed-off-by: Mamta Shukla <mamta.ramendra.shukla@cern.ch>
Suggested-by: Federico Vaga <federico.vaga@cern.ch>

e7d43f1f

16 Nov, 2020 6 commits
- Merge tag 'v2.1.3' into develop · 00fa08a6
  Federico Vaga authored Nov 16, 2020
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2.1.3 - 2020-11-16
==================
Added
-----
- sw,drv: module parameter to ignore bitstream version check (for
development
  or debug)
  - sw: the spec-firmware-version tool can dump build-info

Fixed
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- hdl: DMA failures fixed with thight timing constraints
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  00fa08a6
- Merge branch 'release/v2.1.3' into master · c3ffa27d
  Federico Vaga authored Nov 16, 2020
  
  c3ffa27d
- update CHANGELOG · f8c17949
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f8c17949
- sw:tools: fix help message · ad167e31
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  ad167e31
- Merge remote-tracking branch 'ohwr/bugfix/v2.1.3' into develop · 3acff59a
  Federico Vaga authored Nov 16, 2020
  
  3acff59a
- sw:tool: print build information · f24b4863
  Federico Vaga authored Nov 16, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f24b4863
13 Nov, 2020 3 commits
- Bump minor version · a2ae2c94
  Tristan Gingold authored Nov 13, 2020
  
  a2ae2c94
- Tighten timing constraints. · 92c202a1
  Tristan Gingold authored Nov 13, 2020
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They were too relaxed, in particular the register sync which is used by
FIFOs.
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  92c202a1
- Update gn4124-core · ac968edf
  Tristan Gingold authored Nov 13, 2020
  
  ac968edf
12 Nov, 2020 4 commits
- sw: format the output for humans and machines · 8e770510
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  8e770510
- sw: add missing cap. in singleline · 09c7e423
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  09c7e423
- sw: fix verbose level · f1c0cdb8
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  f1c0cdb8
- sw:drv: add module parameter to ignore the FPGA configuration version · 63beeae3
  Federico Vaga authored Nov 12, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  63beeae3
09 Nov, 2020 16 commits
- Merge tag 'v2.1.2' into develop · f6f34d31
  Federico Vaga authored Nov 09, 2020
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2.1.2 - 2020-11-09
==================
Fixed
-----
- sw: automatize version validation
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  f6f34d31
- Merge branch 'release/v2.1.2' into master · bccad6f3
  Federico Vaga authored Nov 09, 2020
  
  bccad6f3
- update CHANGELOG · 8abbfd3a
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  8abbfd3a
- sw: extract the latest minimum compatible version · 012a5839
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  012a5839
- sw: update SPEC version · 26cb83f6
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  26cb83f6
- Merge tag 'v2.1.1' into develop · 70dbcec5
  Federico Vaga authored Nov 09, 2020
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2.1.1 - 2020-11-09
==================
Fixed
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- hdl: report the correct version in spec-golden design
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  70dbcec5
- Merge branch 'release/v2.1.1' into master · a0f9a0b3
  Federico Vaga authored Nov 09, 2020
  
  a0f9a0b3
- update CHANGELOG · 05ec1669
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  05ec1669
- bld: fix LICENCES · b593ece6
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  b593ece6
- bld: add cppcheck · 1bfe5b06
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  1bfe5b06
- sw: improve portability of pointer math · 98f1bbb8
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  98f1bbb8
- Merge branch 'bugfix/v2.1.1' into develop · f7e143d4
  Federico Vaga authored Nov 09, 2020
  
  f7e143d4
- Set version in metadata to 2.1.1 · 082e54e7
  Tristan Gingold authored Nov 09, 2020
  
  082e54e7
- Merge tag 'v2.1.0' into develop · a446c8e6
  Federico Vaga authored Nov 09, 2020
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2.1.0 - 2020-11-09
==================
Fixed
-----
- hdl: cross-page DMA failure
- sw: DMA pool memory leak
- sw: fix concurrent DMA tasklet

Changed
-------
- tst: keep the DMA interface open while testing to avoid continuos
  memory re-allocation

Added
-----
- sw: tool to firmware version inspection
- sw: FLASH partitions
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  a446c8e6
- Merge branch 'release/v2.1.0' into master · 061bbd7e
  Federico Vaga authored Nov 09, 2020
  
  061bbd7e
- bld:tools: fix clean target · 0c8a72ce
  Federico Vaga authored Nov 09, 2020
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Signed-off-by: Federico Vaga <federico.vaga@cern.ch>
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  0c8a72ce