Commit f78d447e authored by Federico Vaga's avatar Federico Vaga

Merge branch 'release/v2.0.0'

parents 8c641a3b 1e9e50ec
......@@ -15,3 +15,4 @@ GTAGS
GPATH
GRTAGS
Makefile.specific
compile_commands.json
..
SPDX-License-Identifier: CC-0.0
SPDX-FileCopyrightText: 2019 CERN
=========
Changelog
=========
[1.4.15] 2020-06-03
2.0.0 - 2020-07-30
==================
Added
-----
- hdl: new testbench to test the DMA feature (read/write to DDR memory) in the new golden.
- sw: basic Python module to handle DMA and FPGA programming
- sw: user-space DMA interface in debugfs (read/write)
- tst: add integration tests for DMA transfers
Changed
-------
- hdl: Switch to 125MHz (from 62.5MHz before) clock for DMA transfers.
- hdl: Cleanup of top-levels, addition of DMA to the golden.
Fixed
-----
- hdl: DMA misalignment issue due to loss of 32-bit words, caused in turn by inadequate flow control.
- hdl: typo in synthesis constraints.
1.4.15 - 2020-06-03
===================
Added
----
- [hdl] ignore autogenerated files to build metadata (otherwise the repository
-----
- hdl: ignore autogenerated files to build metadata (otherwise the repository
is always marked as dirty)
[1.4.14] 2020-05-28
1.4.14 - 2020-05-28
===================
Added
-----
- [hdl] export DDMTD clock output
- hdl: export DDMTD clock output
[1.4.13] 2020-05-12
1.4.13 - 2020-05-12
===================
Fixed
-----
- [hdl] report correct version in spec-base metadata
- hdl: report correct version in spec-base metadata
[1.4.12] 2020-05-12
1.4.12 - 2020-05-12
===================
Added
-----
- [hdl] metadata source-id automatic assignment
- hdl: metadata source-id automatic assignment
Changed
-----
- [sw] do not double remap memory
-------
- sw: do not double remap memory
[1.4.11] 2020-05-04
1.4.11 - 2020-05-04
===================
Added
-----
- [sw] added DMA engine channel for application to the list of resources
- sw: added DMA engine channel for application to the list of resources
Changed
-----
- [sw] little code improvements
-------
- sw: little code improvements
[1.4.10] 2020-04-24
1.4.10 - 2020-04-24
===================
Changed
-------
- [bld] assign dependencies path based on REPO_PARENT
- [bld] check for missing dependencies
- bld: assign dependencies path based on REPO_PARENT
- bld: check for missing dependencies
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
- sw: fix kernel crash when programming new bitstream
[1.4.9] 2020-03-10
1.4.9 - 2020-03-10
==================
Added
-----
- [sw] support for kernel version more recent than 3.10 (RedHat)
- sw: support for kernel version more recent than 3.10 (RedHat)
Fixed
-----
- [sw] reduce allocation on stack
- sw: reduce allocation on stack
[1.4.8] 2020-02-12
1.4.8 - 2020-02-12
==================
Fixed
-----
- [sw] fix kernel crash when programming new bitstream
- sw: fix kernel crash when programming new bitstream
[1.4.7] 2020-01-15
1.4.7 - 2020-01-15
==================
Fixed
-------
- [doc] sysfs paths were wrong
- [doc] incomplete driver loading list of commands
- doc: sysfs paths were wrong
- doc: incomplete driver loading list of commands
[1.4.6] 2020-01-13
1.4.6 - 2020-01-13
==================
Changed
-------
- [doc] improve documentation
- [sw] better error reporting on I2C errors
- doc: improve documentation
- sw: better error reporting on I2C errors
[1.4.5] 2019-12-17
1.4.5 - 2019-12-17
==================
Something happened while synchronizing different branches and version 1.4.4
could be inconsistent on different repositories. This release increment realign
all repositories
[1.4.4] 2019-12-17
1.4.4 - 2019-12-17
==================
Changed
-----
- [sw] better integration in coht, rename environment variable to FPGA_MGR
-------
- sw: better integration in coht, rename environment variable to FPGA_MGR
Fixed
-----
- [sw] suggested fixed reported by checkpatch and coccicheck
- [hdl] restore lost references to git submodules
- sw: suggested fixed reported by checkpatch and coccicheck
- hdl: restore lost references to git submodules
[1.4.3] - 2019-10-17
====================
1.4.3 - 2019-10-17
==================
Fixed
-----
- [sw] fix SPEC GPIO get_direction
- sw: fix SPEC GPIO get_direction
[1.4.2] - 2019-10-15
====================
1.4.2 - 2019-10-15
==================
Fixed
-----
- [sw] fix SPEC driver dependency with I2C OCores
- sw: fix SPEC driver dependency with I2C OCores
[1.4.1] - 2019-09-23
====================
1.4.1 - 2019-09-23
==================
Changed
-------
- [sw] do not used devm_* operations (it seems to solve problems)
- sw: do not used devm_* operations (it seems to solve problems)
Removed
-------
- [sw] Removed IRQ line assignment to FCL (not used)
- sw: Removed IRQ line assignment to FCL (not used)
Fixed
-----
- [sw] kcalloc usage
- [sw] memcpy(), memset() usage
- [sw] checkpatch style fixes
- sw: kcalloc usage
- sw: memcpy(), memset() usage
- sw: checkpatch style fixes
[1.4.0] 2019-09-11
==================
1.4.0 2019-09-11
================
Added
-----
- [hdl] spec-base IP-core to support SPEC based designs
- [sw] Driver for GN4124 FCL using Linux FPGA manager
- [sw] Driver for GN4124 GPIO using Linux GPIOlib
- [sw] Driver for gn412x-core DMA using Linux DMA engine
- [sw] Support for spec-base IP-core
- [sw] Support for FMC
- hdl: spec-base IP-core to support SPEC based designs
- sw: Driver for GN4124 FCL using Linux FPGA manager
- sw: Driver for GN4124 GPIO using Linux GPIOlib
- sw: Driver for gn412x-core DMA using Linux DMA engine
- sw: Support for spec-base IP-core
- sw: Support for FMC
[0.0.0]
=======
0.0.0
=====
Start the development of a new SPEC driver and SPEC HDL support layer
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2. Waiver. To the greatest extent permitted by, but not in contravention
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partial invalidity or ineffectiveness shall not invalidate the remainder
of the License, and in such case Affirmer hereby affirms that he or she
will not (i) exercise any of his or her remaining Copyright and Related
Rights in the Work or (ii) assert any associated claims and causes of
action with respect to the Work, in either case contrary to Affirmer's
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4. Limitations and Disclaimers.
a. No trademark or patent rights held by Affirmer are waived, abandoned,
surrendered, licensed or otherwise affected by this document.
b. Affirmer offers the Work as-is and makes no representations or
warranties of any kind concerning the Work, express, implied,
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c. Affirmer disclaims responsibility for clearing rights of other persons
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Further, Affirmer disclaims responsibility for obtaining any necessary
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......@@ -12,9 +12,9 @@
# add these directories to sys.path here. If the directory is relative to the
# documentation root, use os.path.abspath to make it absolute, like shown here.
#
# import os
# import sys
# sys.path.insert(0, os.path.abspath('.'))
import os
import sys
sys.path.insert(0, os.path.abspath('../software/PySPEC/PySPEC'))
# -- Project information -----------------------------------------------------
......@@ -39,7 +39,8 @@ release = 'v1.4'
# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
# ones.
extensions = [
]
'sphinx.ext.autodoc'
]
# Add any paths that contain templates here, relative to this directory.
templates_path = ['_templates']
......@@ -171,3 +172,7 @@ epub_title = project
# A list of files that should not be packed into the epub file.
epub_exclude_files = ['search.html']
autodoc_default_options = {
'member-order': 'bysource',
}
......@@ -27,6 +27,7 @@ You can clone the GIT project with the following command::
hdl-spec-base
sw-driver
sw-python
.. _`Open HardWare Repository`: https://ohwr.org/
.. _`SPEC project`: https://ohwr.org/project/spec
......@@ -34,7 +34,7 @@ GN4124 GPIO
GN4124 FCL
This driver provides support for the GN4124 FCL (FPGA Configuration Loader).
It uses the `FPGA manager interface`_ to program the FPGA at runtime.
It uses the `FPGA manager interface`_ to program the FPGA at run-time.
If the SPEC based application is using the :ref:`SPEC
base<spec_hdl_spec_base>` component then it can profit from the
......@@ -220,7 +220,7 @@ attributes. Here we focus only on those.
Miscellaneous information about the card status: IRQ mapping.
``<pci-id>/fpga_firmware`` [W]
It configure the FPGA with a bitstream which name is provided as input.
It configures the FPGA with a bitstream which name is provided as input.
Remember that firmwares are installed in ``/lib/firmware`` and alternatively
you can provide your own path by setting it in
``/sys/module/firmware_class/parameters/path``.
......@@ -231,3 +231,77 @@ attributes. Here we focus only on those.
``<pci-id>/spec-<pci-id>/build_info`` [R]
It shows the FPGA configuration synthesis information
``<pci-id>/spec-<pci-id>/dma`` [RW]
It exports DMA capabilities to user-space. The user can ``open(2)``
and ``close(2)`` to request and release a DMA engine channel. Then,
the user can use ``lseek(2)`` to set the offset in the DDR, and
``read(2)``/``write(2)`` to start the DMA transfer.
Module Parameters
-----------------
``user_dma_coherent_size`` [RW]
It sets the maximum size for a coherent DMA memory allocation. A
change to this value is applied on ``open(2)``
(file ``<pci-id>/spec-<pci-id>/dma``).
``user_dma_max_segment`` [RW]
It sets the maximum size for a DMA transfer in a scatterlist. A
change to this value is applied on the next ``read(2)`` or ``write(2)``
(file ``<pci-id>/spec-<pci-id>/dma``).
DMA
---
On SPEC-Based designs the DMA engine is implemented in HDL. This means
that you can't perform a DMA transfer without a *spec-base* device
on the FPGA.
The SPEC driver(s) implements the dmaengine API for the HDL DMA
engine. To request a dmaengine channel the user must provide a filter
function. The SPEC driver assigns to the application driver a
IORESOURCE_DMA which value is ``dma_device->dev_id << 16 |
channel_number``. Therefore, the user can use the following filter
function.::
static bool filter_function(struct dma_chan *dchan, void *arg)
{
struct dma_device *ddev = dchan->device;
int dev_id = (*((int *)arg) >> 16) & 0xFFFF;
int chan_id = *((int *)arg) & 0xFFFF;
return ddev->dev_id == dev_id && dchan->chan_id == chan_id;
}
void function(void)
{
struct resource *r;
int dma_dev_id;
dma_cap_mask_t dma_mask;
/* ... */
r = platform_get_resource(pdev, IORESOURCE_DMA, TDC_DMA);
dma_dev_id = r->start;
dma_cap_zero(dma_mask);
dma_cap_set(DMA_SLAVE, dma_mask);
dma_cap_set(DMA_PRIVATE, dma_mask);
dchan = dma_request_channel(dma_mask, filter_function,
dma_dev_id);
/* ... */
}
You can get the maximum transfer size by calling ``dma_get_max_seg_size()``.::
dma_get_max_seg_size(dchan->device->dev);
.. warning::
The GN4124 chip has a 4KiB payload. When doing a ``DMA_DEV_TO_MEM``
the HDL DMA engine splits transfers in 4KiB chunks, but for
``DMA_MEM_TO_DEV`` transfers the split should happen in the
driver: it does not happen. The DMA engine implementation
supports ``DMA_MEM_TO_DEV`` manly for testing purposes; to avoid
complications in the driver the 4KiB split is left to users.
..
SPDX-License-Identifier: CC-BY-SA-4.0
SPDX-FileCopyrightText: 2019-2020 CERN
.. _spec_python:
SPEC Python: PySPEC
===================
.. autoclass:: PySPEC.PySPEC
:members:
Subproject commit 1a1293900e6334bc41251ee84d0ae7d19980e584
Subproject commit 70f9de318f155764fdd4b7e1ae7f9c5b77131930
Subproject commit 56d855fc3d97c43e6f21ad669ecfda90971f0982
Subproject commit 258eb8e00f99f795fe9b98840b01ac4a8b92ec94
Subproject commit 91d5eface7608d306991d2c1aa4e6f5210e9305c
Subproject commit e763762405dd5274d342285dbc64683221f1fb15
Subproject commit 25deb51759cf467df4fdeeca3bd10e4e793f71ca
Subproject commit a72a4223e2e1b521ba839f5623ee2857cf4fae10
......@@ -7,8 +7,14 @@ files = [
try:
# Assume this module is in fact a git submodule of a main project that
# is in the same directory as general-cores...
exec(open("../../../" + "/general-cores/tools/gen_sourceid.py").read(),
exec(open("../../../" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
try:
# Otherwise look for the local submodule of general-cores
exec(open("../ip_cores/" + "general-cores/tools/gen_sourceid.py").read(),
None, {'project': 'spec_base'})
except Exception as e:
print("Error: cannot generate source id file")
raise
......@@ -301,7 +301,7 @@ entity spec_base_wr is
-- Addresses 0-0x1fff are not available (used by the carrier).
-- This is a pipelined wishbone with byte granularity.
app_wb_o : out t_wishbone_master_out;
app_wb_i : in t_wishbone_master_in;
app_wb_i : in t_wishbone_master_in := c_DUMMY_WB_MASTER_IN;
sim_wb_i : in t_wishbone_slave_in := cc_dummy_slave_in;
sim_wb_o : out t_wishbone_slave_out
......@@ -431,13 +431,7 @@ begin -- architecture top
g_WBM_TO_WB_FIFO_SIZE => 16,
g_WBM_TO_WB_FIFO_FULL_THRES => 12,
g_WBM_FROM_WB_FIFO_SIZE => 16,
g_WBM_FROM_WB_FIFO_FULL_THRES => 12,
g_P2L_FIFO_SIZE => 256,
g_P2L_FIFO_FULL_THRES => 175,
g_L2P_ADDR_FIFO_FULL_SIZE => 256,
g_L2P_ADDR_FIFO_FULL_THRES => 175,
g_L2P_DATA_FIFO_FULL_SIZE => 256,
g_L2P_DATA_FIFO_FULL_THRES => 175
g_WBM_FROM_WB_FIFO_FULL_THRES => 12
)
port map (
---------------------------------------------------------
......@@ -502,8 +496,8 @@ begin -- architecture top
---------------------------------------------------------
-- L2P DMA Interface (Pipelined Wishbone master)
wb_dma_dat_clk_i => clk_62m5_sys,
wb_dma_dat_rst_n_i => rst_gbl_n,
wb_dma_dat_clk_i => clk_125m_ref,
wb_dma_dat_rst_n_i => rst_125m_ref_n,
wb_dma_dat_o => gn_wb_ddr_out,
wb_dma_dat_i => gn_wb_ddr_in
);
......@@ -610,7 +604,7 @@ begin -- architecture top
metadata_data <= x"53504543";
when x"2" =>
-- Version
metadata_data <= x"0104000d";
metadata_data <= x"02000000";
when x"3" =>
-- BOM
metadata_data <= x"fffe0000";
......@@ -1110,8 +1104,8 @@ begin -- architecture top
p0_wr_underrun_o => open,
p0_wr_error_o => open,
wb1_rst_n_i => rst_gbl_n,
wb1_clk_i => clk_62m5_sys,
wb1_rst_n_i => rst_125m_ref_n,
wb1_clk_i => clk_125m_ref,
wb1_sel_i => gn_wb_ddr_out.sel,
wb1_cyc_i => gn_wb_ddr_out.cyc,
wb1_stb_i => gn_wb_ddr_out.stb,
......
......@@ -114,7 +114,7 @@ NET "inst_spec_base/*cmp_ddr_ctrl_bank3/*/memc3_mcb_raw_wrapper_inst/ioi_drp_clk
# DMA
#---------------------------------------
NET "inst_spec_base/cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
NET "inst_spec_base/gen_with_gennum.cmp_gn4124_core/cmp_wrapped_gn4124/gen_with_dma.cmp_dma_controller/dma_async_*" TNM = FFS "dma_ffs";
TIMESPEC TS_dma_async_ffs = FROM dma_ffs TO pci_clk 15ns DATAPATHONLY;
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_device = "xc6slx100t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden.xise"
syn_project = "spec_golden-100T.xise"
syn_tool = "ise"
syn_top = "spec_golden"
spec_base_ucf = ['onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
spec_base_ucf = ['onewire', 'spi', 'ddr3']
files = [ "buildinfo_pkg.vhd" ]
ctrls = ["bank3_32b_32b" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx45t"
syn_device = "xc6slx150t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_project = "spec_golden-150T.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
syn_top = "spec_golden"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
spec_base_ucf = ['onewire', 'spi', 'ddr3']
files = [ "buildinfo_pkg.vhd" ]
ctrls = ["bank3_32b_32b" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
target = "xilinx"
action = "synthesis"
board = "spec"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
syn_device = "xc6slx150t"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_golden_wr.xise"
syn_project = "spec_golden-45T.xise"
syn_tool = "ise"
syn_top = "spec_golden_wr"
syn_top = "spec_golden"
spec_base_ucf = ['wr', 'onewire', 'spi']
board = "spec"
ctrls = ["bank3_64b_32b" ]
spec_base_ucf = ['onewire', 'spi', 'ddr3']
files = [ "buildinfo_pkg.vhd" ]
ctrls = ["bank3_32b_32b" ]
files = [
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden_wr", "../../syn/common"
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
"../../top/golden",
"../../syn/common",
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
......
*
!.gitignore
!Manifest.py
!*.ucf
!syn_extra_steps.tcl
target = "xilinx"
action = "synthesis"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
board = "spec"
syn_device = "xc6slx45t"
syn_grade = "-3"
syn_package = "fgg484"
syn_project = "spec_full.xise"
syn_project = "spec_base_wr_example.xise"
syn_tool = "ise"
syn_top = "spec_full"
syn_top = "spec_base_wr_example"
spec_base_ucf = ['wr', 'onewire', 'spi', 'ddr3']
board = "spec"
ctrls = ["bank3_64b_32b" ]
ctrls = ["bank3_32b_32b" ]
files = [ "buildinfo_pkg.vhd" ]
modules = {
"local" : [
"../../top/full", "../../syn/common"
"../../top/wr_example",
"../../syn/common",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
......@@ -31,6 +28,10 @@ modules = {
],
}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
# Do not fail during hdlmake fetch
try:
......
Makefile
work/
transcript
vsim.wlf
NullFile
modelsim.ini
buildinfo_pkg.vhd
board = "spec"
sim_tool = "modelsim"
sim_top = "main"
action = "simulation"
target = "xilinx"
syn_device = "xc6slx45t"
vcom_opt = "-93 -mixedsvvh"
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto="../../ip_cores"
include_dirs = [
fetchto + "/gn4124-core/hdl/sim/gn4124_bfm",
fetchto + "/general-cores/sim/",
fetchto + "/ddr3-sp6-core/hdl/sim/",
]
files = [
"main.sv",
"buildinfo_pkg.vhd",
]
modules = {
"local" : [
"../../top/golden",
],
}
# Do not fail during hdlmake fetch
try:
exec(open(fetchto + "/general-cores/tools/gen_buildinfo.py").read())
except:
pass
ctrls = ["bank3_32b_32b" ]
`timescale 1ns/1ps
`include "gn4124_bfm.svh"
`define DMA_BASE 'h00c0
`define VIC_BASE 'h0100
module main;
reg rst_n = 0;
reg clk_125m_pllref = 0;
reg clk_20m_vcxo = 0;
initial begin
repeat(20) @(posedge clk_125m_pllref);
rst_n = 1;
end
IGN4124PCIMaster i_gn4124 ();
wire ddr_cas_n, ddr_ck_p, ddr_ck_n, ddr_cke;
wire [1:0] ddr_dm, ddr_dqs_p, ddr_dqs_n;
wire ddr_odt, ddr_ras_n, ddr_reset_n, ddr_we_n;
wire [15:0] ddr_dq;
wire [13:0] ddr_a;
wire [2:0] ddr_ba;
wire ddr_rzq;
pulldown(ddr_rzq);
// 125Mhz
always #4ns clk_125m_pllref <= ~clk_125m_pllref;
spec_golden
#(
.g_SIMULATION(1)
)
DUT
(
.button1_n_i (rst_n),
.clk_125m_pllref_p_i (clk_125m_pllref),
.clk_125m_pllref_n_i (~clk_125m_pllref),
.gn_rst_n_i (i_gn4124.rst_n),
.gn_p2l_clk_n_i (i_gn4124.p2l_clk_n),
.gn_p2l_clk_p_i (i_gn4124.p2l_clk_p),
.gn_p2l_rdy_o (i_gn4124.p2l_rdy),
.gn_p2l_dframe_i (i_gn4124.p2l_dframe),
.gn_p2l_valid_i (i_gn4124.p2l_valid),
.gn_p2l_data_i (i_gn4124.p2l_data),
.gn_p_wr_req_i (i_gn4124.p_wr_req),
.gn_p_wr_rdy_o (i_gn4124.p_wr_rdy),
.gn_rx_error_o (i_gn4124.rx_error),
.gn_l2p_clk_n_o (i_gn4124.l2p_clk_n),
.gn_l2p_clk_p_o (i_gn4124.l2p_clk_p),
.gn_l2p_dframe_o (i_gn4124.l2p_dframe),
.gn_l2p_valid_o (i_gn4124.l2p_valid),
.gn_l2p_edb_o (i_gn4124.l2p_edb),
.gn_l2p_data_o (i_gn4124.l2p_data),
.gn_l2p_rdy_i (i_gn4124.l2p_rdy),
.gn_l_wr_rdy_i (i_gn4124.l_wr_rdy),
.gn_p_rd_d_rdy_i (i_gn4124.p_rd_d_rdy),
.gn_tx_error_i (i_gn4124.tx_error),
.gn_vc_rdy_i (i_gn4124.vc_rdy),
.gn_gpio_b (),
.ddr_a_o (ddr_a),
.ddr_ba_o (ddr_ba),
.ddr_cas_n_o (ddr_cas_n),
.ddr_ck_n_o (ddr_ck_n),
.ddr_ck_p_o (ddr_ck_p),
.ddr_cke_o (ddr_cke),
.ddr_dq_b (ddr_dq),
.ddr_ldm_o (ddr_dm[0]),
.ddr_ldqs_n_b (ddr_dqs_n[0]),
.ddr_ldqs_p_b (ddr_dqs_p[0]),
.ddr_odt_o (ddr_odt),
.ddr_ras_n_o (ddr_ras_n),
.ddr_reset_n_o (ddr_reset_n),
.ddr_rzq_b (ddr_rzq),
.ddr_udm_o (ddr_dm[1]),
.ddr_udqs_n_b (ddr_dqs_n[1]),
.ddr_udqs_p_b (ddr_dqs_p[1]),
.ddr_we_n_o (ddr_we_n)
);
ddr3 #
(
.DEBUG(0),
.check_strict_timing(0),
.check_strict_mrbits(0)
)
cmp_ddr0
(
.rst_n (ddr_reset_n),
.ck (ddr_ck_p),
.ck_n (ddr_ck_n),
.cke (ddr_cke),
.cs_n (1'b0),
.ras_n (ddr_ras_n),
.cas_n (ddr_cas_n),
.we_n (ddr_we_n),
.dm_tdqs (ddr_dm),
.ba (ddr_ba),
.addr (ddr_a),
.dq (ddr_dq),
.dqs (ddr_dqs_p),
.dqs_n (ddr_dqs_n),
.tdqs_n (),
.odt (ddr_odt)
);
typedef enum bit {RD,WR} dma_dir_t;
task dma_xfer(input CBusAccessor acc,
input uint64_t host_addr,
input uint32_t start_addr,
input uint32_t length,
input dma_dir_t dma_dir,
input int timeout = 1ms);
real timeout_time;
// Configure the VIC
acc.write(`VIC_BASE + 'h8, 'h7f);
acc.write(`VIC_BASE + 'h0, 'h1);
// Setup DMA addresses
acc.write(`DMA_BASE + 'h08, start_addr); // dma start addr
acc.write(`DMA_BASE + 'h0C, host_addr & 'hffffffff); // host addr low
acc.write(`DMA_BASE + 'h10, host_addr >> 32); // host addr high
acc.write(`DMA_BASE + 'h14, length); // length in bytes
acc.write(`DMA_BASE + 'h18, 'h00000000); // next low
acc.write(`DMA_BASE + 'h1C, 'h00000000); // next high
// Setup DMA direction
if (dma_dir == RD)
begin
acc.write(`DMA_BASE + 'h20, 'h00000000); // attrib: pcie -> host
$display("<%t> START DMA READ from 0x%x, %0d bytes",
$realtime, start_addr, length);
end
else
begin
acc.write(`DMA_BASE + 'h20, 'h00000001); // attrib: host -> pcie
$display("<%t> START DMA WRITE to 0x%x, %0d bytes",
$realtime, start_addr, length);
end
// Start transfer
acc.write(`DMA_BASE + 'h00, 'h00000001);
// Check for completion/timeout
timeout_time = $realtime + timeout;
while (timeout_time > $realtime)
begin
if (DUT.inst_spec_base.irqs[2] == 1)
begin
$display("<%t> END DMA", $realtime);
acc.write(`DMA_BASE + 'h04, 'h04);
acc.write(`VIC_BASE + 'h1c, 'h0);
return;
end
#1us;
end
$fatal(1, "<%t> DMA TIMEOUT", $realtime);
endtask // dma_xfer
typedef virtual IGN4124PCIMaster vIGN4124PCIMaster;
task dma_test(vIGN4124PCIMaster i_gn4124,
input uint32_t word_count);
int i;
uint32_t word_addr, word_remain, word_ptr;
uint64_t val, expected, host_addr;
uint64_t data_queue[$];
CBusAccessor acc;
acc = i_gn4124.get_accessor();
acc.set_default_xfer_size(4);
word_addr = $urandom_range(65535 - word_count);
// Prepare host memory
for (i = 0; i < word_count; i++)
begin
val = $urandom();
i_gn4124.host_mem_write(i*4, val);
data_queue.push_back(val);
end
// Write data to device memory
word_ptr = word_addr;
word_remain = word_count;
host_addr = 'h20000000;
while (word_remain != 0)
begin
if (word_remain > 1024)
begin
dma_xfer(acc, host_addr, word_ptr * 4, 4096, WR);
word_remain -= 1024;
word_ptr += 1024;
host_addr += 4096;
end
else
begin
dma_xfer(acc, host_addr, word_ptr * 4, word_remain * 4, WR);
word_ptr += word_remain;
word_remain = 0;
host_addr = 'h20000000;
end
end
// Clear host memory
for (i = 0; i < word_count; i++)
begin
i_gn4124.host_mem_write(i*4, 0);
end
// Read data from device memory
dma_xfer(acc, host_addr, word_addr * 4, word_count * 4, RD);
// Compare against written data
for (i = 0; i < word_count; i++)
begin
i_gn4124.host_mem_read(i*4, val);
expected = data_queue.pop_front();
if (val != expected)
$fatal(1, "<%t> READ-BACK ERROR at host address 0x%x: expected 0x%8x, got 0x%8x",
$realtime, i*4, expected, val);
end
endtask // dma_test
initial begin
int i;
uint64_t val, expected;
vIGN4124PCIMaster vi_gn4124;
vi_gn4124= i_gn4124;
$timeformat (-6, 3, "us", 10);
$display();
$display ("Simulation START");
$display();
#10us;
for (i = 2; i < 13; i++)
begin
#1us;
dma_test(vi_gn4124, 2**i);
end
$display();
$display ("Simulation PASSED");
$display();
$finish;
end
endmodule // main
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -voptargs="+acc" -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
radix -hexadecimal
log -r /*
run -all
vsim -quiet -t 10fs -L unisim work.main -suppress 1270,8617,8683,8684,8822 -sv_seed random
set StdArithNoWarnings 1
set NumericStdNoWarnings 1
run -all
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files = ["spec_golden.vhd"]
modules = {'local': ["../../rtl"]}
# Allow the user to override fetchto using:
# hdlmake -p "fetchto='xxx'"
if locals().get('fetchto', None) is None:
fetchto = "../../ip_cores"
files = [
"spec_golden.vhd",
]
modules = {
"local" : [
"../../rtl",
],
"git" : [
"https://ohwr.org/project/wr-cores.git",
"https://ohwr.org/project/general-cores.git",
"https://ohwr.org/project/gn4124-core.git",
"https://ohwr.org/project/ddr3-sp6-core.git",
],
}
......@@ -9,7 +9,7 @@
-- description: SPEC golden design, without WR.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
......@@ -24,54 +24,46 @@
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use work.wishbone_pkg.all;
entity spec_golden is
generic (
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic; -- 125 MHz PLL reference
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
gn_RST_N_i : in std_logic; -- Reset from GN4124 (RSTOUT18_N)
-- General Purpose Interface
gn_GPIO_b : inout std_logic_vector(1 downto 0); -- GPIO[0] -> GN4124 GPIO8
-- GPIO[1] -> GN4124 GPIO9
-- PCIe to Local [Inbound Data] - RX
gn_P2L_RDY_o : out std_logic; -- Rx Buffer Full Flag
gn_P2L_CLK_n_i : in std_logic; -- Receiver Source Synchronous Clock-
gn_P2L_CLK_p_i : in std_logic; -- Receiver Source Synchronous Clock+
gn_P2L_DATA_i : in std_logic_vector(15 downto 0); -- Parallel receive data
gn_P2L_DFRAME_i : in std_logic; -- Receive Frame
gn_P2L_VALID_i : in std_logic; -- Receive Data Valid
-- Inbound Buffer Request/Status
gn_P_WR_REQ_i : in std_logic_vector(1 downto 0); -- PCIe Write Request
gn_P_WR_RDY_o : out std_logic_vector(1 downto 0); -- PCIe Write Ready
gn_RX_ERROR_o : out std_logic; -- Receive Error
-- Local to Parallel [Outbound Data] - TX
gn_L2P_DATA_o : out std_logic_vector(15 downto 0); -- Parallel transmit data
gn_L2P_DFRAME_o : out std_logic; -- Transmit Data Frame
gn_L2P_VALID_o : out std_logic; -- Transmit Data Valid
gn_L2P_CLK_n_o : out std_logic; -- Transmitter Source Synchronous Clock-
gn_L2P_CLK_p_o : out std_logic; -- Transmitter Source Synchronous Clock+
gn_L2P_EDB_o : out std_logic; -- Packet termination and discard
-- Outbound Buffer Status
gn_L2P_RDY_i : in std_logic; -- Tx Buffer Full Flag
gn_L_WR_RDY_i : in std_logic_vector(1 downto 0); -- Local-to-PCIe Write
gn_P_RD_D_RDY_i : in std_logic_vector(1 downto 0); -- PCIe-to-Local Read Response Data Ready
gn_TX_ERROR_i : in std_logic; -- Transmit Error
gn_VC_RDY_i : in std_logic_vector(1 downto 0); -- Channel ready
-- PCB version
-- GN4124
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
-- PCB version and reset button
pcbrev_i : in std_logic_vector(3 downto 0);
-- Font panel LEDs
-- LED_RED : out std_logic;
-- LED_GREEN : out std_logic;
button1_n_i : in std_logic;
-- I2C to the FMC
......@@ -79,32 +71,53 @@ entity spec_golden is
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i: in std_logic;
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
-- Onewire
onewire_b : inout std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic
);
end spec_golden;
architecture rtl of spec_golden is
signal clk_sys_62m5 : std_logic;
signal rst_sys_62m5_n : std_logic;
architecture arch of spec_golden is
signal gn_wb_out : t_wishbone_master_out;
signal gn_wb_in : t_wishbone_master_in;
begin
inst_spec_base: entity work.spec_base_wr
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => True,
g_WITH_ONEWIRE => True,
g_WITH_SPI => True,
g_WITH_DDR => False,
g_WITH_WR => False,
g_simulation => False
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => TRUE,
g_WITH_SPI => TRUE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => FALSE,
g_SIMULATION => g_SIMULATION
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
......@@ -140,16 +153,25 @@ begin
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
ddr_dma_clk_i => clk_sys_62m5,
ddr_dma_rst_n_i => rst_sys_62m5_n,
clk_62m5_sys_o => clk_sys_62m5,
rst_62m5_sys_n_o => rst_sys_62m5_n,
-- Everything is handled by the carrier.
app_wb_o => gn_wb_out,
app_wb_i => gn_wb_in
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o
);
gn_wb_in <= (ack => '1', err | rty | stall => '0', dat => (others => '0'));
end rtl;
end architecture arch;
files = ["spec_golden_wr.vhd"]
modules = {'local': ["../../rtl"]}
This diff is collapsed.
files = ["spec_full.vhd"]
files = ["spec_base_wr_example.vhd"]
modules = {'local': ["../../rtl"]}
--------------------------------------------------------------------------------
-- CERN BE-CO-HT
-- SPEC
-- https://ohwr.org/projects/spec
--------------------------------------------------------------------------------
--
-- unit name: spec_base_wr_example
--
-- description: Example instantiation of SPEC base with White Rabbit.
--
--------------------------------------------------------------------------------
-- Copyright CERN 2019-2020
--------------------------------------------------------------------------------
-- Copyright and related rights are licensed under the Solderpad Hardware
-- License, Version 2.0 (the "License"); you may not use this file except
-- in compliance with the License. You may obtain a copy of the License at
-- http://solderpad.org/licenses/SHL-2.0.
-- Unless required by applicable law or agreed to in writing, software,
-- hardware and materials distributed under this License is distributed on an
-- "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express
-- or implied. See the License for the specific language governing permissions
-- and limitations under the License.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;
entity spec_base_wr_example is
generic (
g_DPRAM_INITF : string := "../../../../wr-cores/bin/wrpc/wrc_phy8.bram";
-- Simulation-mode enable parameter. Set by default (synthesis) to 0, and
-- changed to non-zero in the instantiation of the top level DUT in the testbench.
-- Its purpose is to reduce some internal counters/timeouts to speed up simulations.
g_SIMULATION : boolean := FALSE
);
port (
-- Global ports
clk_125m_pllref_p_i : in std_logic;
clk_125m_pllref_n_i : in std_logic;
clk_20m_vcxo_i : in std_logic;
clk_125m_gtp_n_i : in std_logic;
clk_125m_gtp_p_i : in std_logic;
-- GN4124
gn_rst_n_i : in std_logic;
gn_p2l_clk_n_i : in std_logic;
gn_p2l_clk_p_i : in std_logic;
gn_p2l_rdy_o : out std_logic;
gn_p2l_dframe_i : in std_logic;
gn_p2l_valid_i : in std_logic;
gn_p2l_data_i : in std_logic_vector(15 downto 0);
gn_p_wr_req_i : in std_logic_vector(1 downto 0);
gn_p_wr_rdy_o : out std_logic_vector(1 downto 0);
gn_rx_error_o : out std_logic;
gn_l2p_clk_n_o : out std_logic;
gn_l2p_clk_p_o : out std_logic;
gn_l2p_dframe_o : out std_logic;
gn_l2p_valid_o : out std_logic;
gn_l2p_edb_o : out std_logic;
gn_l2p_data_o : out std_logic_vector(15 downto 0);
gn_l2p_rdy_i : in std_logic;
gn_l_wr_rdy_i : in std_logic_vector(1 downto 0);
gn_p_rd_d_rdy_i : in std_logic_vector(1 downto 0);
gn_tx_error_i : in std_logic;
gn_vc_rdy_i : in std_logic_vector(1 downto 0);
gn_gpio_b : inout std_logic_vector(1 downto 0);
-- PCB version and reset button
pcbrev_i : in std_logic_vector(3 downto 0);
button1_n_i : in std_logic;
-- I2C to the FMC
fmc0_scl_b : inout std_logic;
fmc0_sda_b : inout std_logic;
-- FMC presence (there is a pull-up)
fmc0_prsnt_m2c_n_i : in std_logic;
-- DDR3
ddr_a_o : out std_logic_vector(13 downto 0);
ddr_ba_o : out std_logic_vector(2 downto 0);
ddr_cas_n_o : out std_logic;
ddr_ck_n_o : out std_logic;
ddr_ck_p_o : out std_logic;
ddr_cke_o : out std_logic;
ddr_dq_b : inout std_logic_vector(15 downto 0);
ddr_ldm_o : out std_logic;
ddr_ldqs_n_b : inout std_logic;
ddr_ldqs_p_b : inout std_logic;
ddr_odt_o : out std_logic;
ddr_ras_n_o : out std_logic;
ddr_reset_n_o : out std_logic;
ddr_rzq_b : inout std_logic;
ddr_udm_o : out std_logic;
ddr_udqs_n_b : inout std_logic;
ddr_udqs_p_b : inout std_logic;
ddr_we_n_o : out std_logic;
-- Onewire
onewire_b : inout std_logic;
-- SPI
spi_sclk_o : out std_logic;
spi_ncs_o : out std_logic;
spi_mosi_o : out std_logic;
spi_miso_i : in std_logic;
-- Red LED next to the SFP: blinking indicates that packets are being
-- transferred.
led_act_o : out std_logic;
-- Green LED next to the SFP: indicates if the link is up.
led_link_o : out std_logic;
-- UART
uart_rxd_i : in std_logic;
uart_txd_o : out std_logic;
-- SPI interface to DACs
plldac_sclk_o : out std_logic;
plldac_din_o : out std_logic;
pll25dac_cs_n_o : out std_logic; --cs1
pll20dac_cs_n_o : out std_logic; --cs2
-- SFP I/O for transceiver
sfp_txp_o : out std_logic;
sfp_txn_o : out std_logic;
sfp_rxp_i : in std_logic;
sfp_rxn_i : in std_logic;
sfp_mod_def0_i : in std_logic; -- sfp detect
sfp_mod_def1_b : inout std_logic; -- scl
sfp_mod_def2_b : inout std_logic; -- sda
sfp_rate_select_o : out std_logic;
sfp_tx_fault_i : in std_logic;
sfp_tx_disable_o : out std_logic;
sfp_los_i : in std_logic
);
end entity spec_base_wr_example;
architecture arch of spec_base_wr_example is
begin
inst_spec_base : entity work.spec_base_wr
generic map (
g_WITH_VIC => TRUE,
g_WITH_ONEWIRE => FALSE,
g_WITH_SPI => FALSE,
g_WITH_DDR => TRUE,
g_DDR_DATA_SIZE => 32,
g_WITH_WR => TRUE,
g_DPRAM_INITF => g_DPRAM_INITF,
g_SIMULATION => g_SIMULATION
)
port map (
clk_125m_pllref_p_i => clk_125m_pllref_p_i,
clk_125m_pllref_n_i => clk_125m_pllref_n_i,
gn_rst_n_i => gn_rst_n_i,
gn_p2l_clk_n_i => gn_p2l_clk_n_i,
gn_p2l_clk_p_i => gn_p2l_clk_p_i,
gn_p2l_rdy_o => gn_p2l_rdy_o,
gn_p2l_dframe_i => gn_p2l_dframe_i,
gn_p2l_valid_i => gn_p2l_valid_i,
gn_p2l_data_i => gn_p2l_data_i,
gn_p_wr_req_i => gn_p_wr_req_i,
gn_p_wr_rdy_o => gn_p_wr_rdy_o,
gn_rx_error_o => gn_rx_error_o,
gn_l2p_clk_n_o => gn_l2p_clk_n_o,
gn_l2p_clk_p_o => gn_l2p_clk_p_o,
gn_l2p_dframe_o => gn_l2p_dframe_o,
gn_l2p_valid_o => gn_l2p_valid_o,
gn_l2p_edb_o => gn_l2p_edb_o,
gn_l2p_data_o => gn_l2p_data_o,
gn_l2p_rdy_i => gn_l2p_rdy_i,
gn_l_wr_rdy_i => gn_l_wr_rdy_i,
gn_p_rd_d_rdy_i => gn_p_rd_d_rdy_i,
gn_tx_error_i => gn_tx_error_i,
gn_vc_rdy_i => gn_vc_rdy_i,
gn_gpio_b => gn_gpio_b,
fmc0_scl_b => fmc0_scl_b,
fmc0_sda_b => fmc0_sda_b,
fmc0_prsnt_m2c_n_i => fmc0_prsnt_m2c_n_i,
onewire_b => onewire_b,
spi_sclk_o => spi_sclk_o,
spi_ncs_o => spi_ncs_o,
spi_mosi_o => spi_mosi_o,
spi_miso_i => spi_miso_i,
pcbrev_i => pcbrev_i,
led_act_o => led_act_o,
led_link_o => led_link_o,
button1_n_i => button1_n_i,
ddr_a_o => ddr_a_o,
ddr_ba_o => ddr_ba_o,
ddr_cas_n_o => ddr_cas_n_o,
ddr_ck_n_o => ddr_ck_n_o,
ddr_ck_p_o => ddr_ck_p_o,
ddr_cke_o => ddr_cke_o,
ddr_dq_b => ddr_dq_b,
ddr_ldm_o => ddr_ldm_o,
ddr_ldqs_n_b => ddr_ldqs_n_b,
ddr_ldqs_p_b => ddr_ldqs_p_b,
ddr_odt_o => ddr_odt_o,
ddr_ras_n_o => ddr_ras_n_o,
ddr_reset_n_o => ddr_reset_n_o,
ddr_rzq_b => ddr_rzq_b,
ddr_udm_o => ddr_udm_o,
ddr_udqs_n_b => ddr_udqs_n_b,
ddr_udqs_p_b => ddr_udqs_p_b,
ddr_we_n_o => ddr_we_n_o,
uart_rxd_i => uart_rxd_i,
uart_txd_o => uart_txd_o,
clk_20m_vcxo_i => clk_20m_vcxo_i,
clk_125m_gtp_n_i => clk_125m_gtp_n_i,
clk_125m_gtp_p_i => clk_125m_gtp_p_i,
plldac_sclk_o => plldac_sclk_o,
plldac_din_o => plldac_din_o,
pll25dac_cs_n_o => pll25dac_cs_n_o,
pll20dac_cs_n_o => pll20dac_cs_n_o,
sfp_txp_o => sfp_txp_o,
sfp_txn_o => sfp_txn_o,
sfp_rxp_i => sfp_rxp_i,
sfp_rxn_i => sfp_rxn_i,
sfp_mod_def0_i => sfp_mod_def0_i,
sfp_mod_def1_b => sfp_mod_def1_b,
sfp_mod_def2_b => sfp_mod_def2_b,
sfp_rate_select_o => sfp_rate_select_o,
sfp_tx_fault_i => sfp_tx_fault_i,
sfp_tx_disable_o => sfp_tx_disable_o,
sfp_los_i => sfp_los_i
);
end architecture arch;
"""
SPDX-License-Identifier: GPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN
"""
import pytest
from PySPEC import PySPEC
@pytest.fixture(scope="function")
def spec():
spec_dev = PySPEC(pytest.pci_id)
yield spec_dev
def pytest_addoption(parser):
parser.addoption("--pci-id",
required=True, help="SPEC PCI Identifier")
parser.addoption("--bitstream",
default=None, help="SPEC bitstream to be tested")
def pytest_configure(config):
pytest.pci_id = config.getoption("--pci-id")
pytest.cfg_bitstream = config.getoption("--bitstream")
if pytest.cfg_bitstream is not None:
spec = PySPEC(pytest.pci_id)
spec.program_fpga(pytest.cfg_bitstream)
del spec
# SPDX-License-Identifier: GPL-3.0-or-later
# SPDX-FileCopyrightText: 2020 CERN
[pytest]
addopts = -v -p no:cacheprovider
\ No newline at end of file
This diff is collapsed.
# SPDX-License-Identifier: CC0-1.0
#
# SPDX-FileCopyrightText: 2020 CERN
*.pyc
MANIFEST
# SPDX-License-Identifier: CC0-1.0
#
# SPDX-FileCopyrightText: 2020 CERN
-include Makefile.specific
all:
clean:
install:
python setup.py install
.PHONY: all clean install
"""
@package docstring
@author: Federico Vaga <federico.vaga@cern.ch>
SPDX-License-Identifier: LGPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN (home.cern)
"""
import os
from contextlib import contextmanager
class PySPEC:
"""
This class gives access to SPEC features.
"""
#: SPEC DDR size
DDR_SIZE = 256 * 1024 * 1024
#: SPEC DDR access alignment
DDR_ALIGN = 4
def __init__(self, pci_id):
self.pci_id = pci_id
self.debugfs = "/sys/kernel/debug/0000:{:s}".format(self.pci_id)
self.debugfs_fpga = os.path.join(self.debugfs, "spec-0000:{:s}".format(self.pci_id))
def program_fpga(self, bitstream):
"""
Program the FPGA with the given bitstream
:var path: path to bitstream
:raise OSError: on failure
"""
with open("/sys/module/firmware_class/parameters/path", "r") as f:
prev = f.read()
with open("/sys/module/firmware_class/parameters/path", "w") as f:
f.write(os.path.dirname(bitstream))
with open(os.path.join(self.debugfs, "fpga_firmware"), "w") as f:
f.write(os.path.basename(bitstream))
with open("/sys/module/firmware_class/parameters/path", "w") as f:
f.write(os.path.dirname(prev))
@contextmanager
def dma(self, dma_coherent_size=None):
"""
Create a DMA context from which users can do DMA
transfers. Within this context the user can use
PySPECDMA.read() and PySPECDMA.write(). Here an example.
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> with spec.dma() as dma:
>>> cnt = dma.write(0, b"\x00" * 16)
>>> buffer = dma.read(0, 16)
Which is equivalent to:
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> spec_dma = PySPEC.PySPECDMA(spec)
>>> spec_dma.open()
>>> cnt = spec_dma.write(0, b"\x00" * 16)
>>> buffer = spec_dma.read(0, 16)
>>> spec_dma.close()
"""
spec_dma = self.PySPECDMA(self)
spec_dma.request(dma_coherent_size)
try:
yield spec_dma
finally:
spec_dma.release()
class PySPECDMA:
"""
This class wraps DMA features in a single object.
The SPEC has
only one DMA channel. On request() the user will get exclusive
access. The user must release() the DMA channel as soon as
possible to let other users or drivers to access it. For this reason,
avoid to use this class directly. Instead, use the DMA context
from the PySPEC class which is less error prone.
>>> from PySPEC import PySPEC
>>> spec = PySPEC("06:00.0")
>>> with spec.dma() as dma:
>>> cnt = dma.write(0, b"\x00" * 16)
>>> buffer = dma.read(0, 16)
>>> print(buffer)
"""
def __init__(self, spec):
"""
Create a new instance
:var spec: a valid PySPEC instance
"""
self.spec = spec
def request(self, dma_coherent_size=None):
"""
Open a DMA file descriptor
:var dma_coherent_size: DMA coherent allocation size (in-kernel).
:raise OSError: if the open(2) or the driver fails
"""
if dma_coherent_size is not None:
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_coherent_size", "w") as f:
f.write(str(dma_coherent_size))
self.dma_file = open(os.path.join(self.spec.debugfs_fpga, "dma"),
"rb+", buffering=0)
def release(self):
"""
Close the DMA file descriptor
:raise OSError: if the close(2) or the driver fails
"""
if hasattr(self, "dma_file"):
self.dma_file.close()
def read(self, offset, size, max_segment=0):
"""
Trigger a *device to memory* DMA transfer
:var offset: offset within the DDR
:var size: number of bytes to be transferred
:var max_segment: maximum size of a single transfer in a
scatterlist. Default is 0, it means to use
the DMA engine's default.
:return: the data transfered as bytes() array
:raise OSError: if the read(2) or the driver fails
"""
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_max_segment", "w") as f:
f.write(str(max_segment))
self.__seek(offset)
data = []
while size - len(data) > 0:
data += self.dma_file.read(size - len(data))
return bytes(data)
def write(self, offset, data, max_segment=0):
"""
Trigger a *memory to device* DMA transfer
:var offset: offset within the DDR
:var size: number of bytes to be transferred
:var max_segment: maximum size of a single transfer in a
scatterlist. Default is 0, it means to use
the DMA engine's default.
:return: the number of transfered bytes
:raise OSError: if the write(2) or the driver fails
"""
with open("/sys/module/spec_fmc_carrier/parameters/user_dma_max_segment", "w") as f:
f.write(str(max_segment))
self.__seek(offset)
start = 0
while len(data) - start > 0:
start += self.dma_file.write(bytes(data[start:]))
return start
def __seek(self, offset):
"""
Change DDR offset
:var offset: offset within the DDR
:raise OSError: if lseek(2) fails or the driver
"""
self.dma_file.seek(offset)
"""
@package docstring
@author: Federico Vaga <federico.vaga@cern.ch>
SPDX-License-Identifier: LGPL-3.0-or-later
SPDX-FileCopyrightText: 2020 CERN (home.cern)
"""
from .PySPEC import PySPEC
__all__ = (
"PySPEC",
)
#!/usr/bin/env python
"""
SPDX-License-Identifier: CC0-1.0
SPDX-FileCopyrightText: 2020 CERN
"""
from distutils.core import setup
setup(name='PySPEC',
version='1.4.14',
description='Python Module to handle SPEC cards',
author='Federico Vaga',
author_email='federico.vaga@cern.ch',
maintainer="Federico Vaga",
maintainer_email="federico.vaga@cern.ch",
url='https://www.ohwr.org/project/spec',
packages=['PySPEC'],
license='LGPL-3.0-or-later',
)
This diff is collapsed.
......@@ -16,10 +16,23 @@
#include <linux/bitops.h>
#include <linux/fmc.h>
#include <linux/delay.h>
#include <linux/completion.h>
#include <linux/jiffies.h>
#include <linux/uaccess.h>
#include <linux/moduleparam.h>
#include "linux/printk.h"
#include "spec.h"
#include "spec-compat.h"
static int user_dma_coherent_size = 4 * 1024 * 1024;
module_param(user_dma_coherent_size, int, 0644);
MODULE_PARM_DESC(user_dma_coherent_size,
"DMA coherent allocation's size in bytes (default 4MiB)");
static size_t user_dma_max_segment;
module_param(user_dma_max_segment, long, 0644);
MODULE_PARM_DESC(user_dma_max_segment,
"Maximum DMA segment size in bytes (default 0, meaning whatever supported by the DMA engine)");
enum spec_fpga_irq_lines {
SPEC_FPGA_IRQ_FMC_I2C = 0,
......@@ -122,6 +135,259 @@ static const struct file_operations spec_fpga_dbg_bld_ops = {
.release = single_release,
};
struct spec_fpga_dbg_dma {
struct spec_fpga *spec_fpga;
struct dma_chan *dchan;
size_t datalen;
void *data;
dma_addr_t datadma;
struct dmaengine_result dma_res;
struct completion compl;
};
struct spec_fmca_dbg_dma_tx_ctxt {
struct dmaengine_result dma_res;
};
static void spec_fmca_dbg_dma_tx_complete(void *arg,
const struct dmaengine_result *result)
{
struct spec_fpga_dbg_dma *dbgdma = arg;
memcpy(&dbgdma->dma_res, result, sizeof(*result));
complete(&dbgdma->compl);
}
static int spec_fpga_dbg_dma_transfer(struct spec_fpga_dbg_dma *dbgdma,
enum dma_transfer_direction dir,
size_t count, loff_t offset)
{
int err;
struct dma_slave_config sconfig;
struct dma_async_tx_descriptor *tx;
dma_cookie_t cookie;
size_t max_segment;
struct sg_table sgt;
struct scatterlist *sg;
int i;
dev_dbg(dbgdma->dchan->device->dev,
"arg: {dir: %d, size: %ld, offset: 0x%08llx}\n",
dir, count, offset);
/*
* The GN4124 chip has a 4KiB payload. For DMA_DEV_TO_MEM this is
* handled by the HDL core. For DMA_MEM_TO_DEV, the split is done here.
*/
if (dir == DMA_DEV_TO_MEM)
max_segment = dma_get_max_seg_size(dbgdma->dchan->device->dev);
else
max_segment = 4096;
if (user_dma_max_segment)
max_segment = min(user_dma_max_segment, max_segment);
err = sg_alloc_table(&sgt,
(count / max_segment) + !!(count % max_segment),
GFP_KERNEL);
if (err)
goto err_sgt;
for_each_sg(sgt.sgl, sg, sgt.nents, i) {
sg_dma_address(sg) = dbgdma->datadma + (i * max_segment);
sg_dma_len(sg) = max_segment;
if (sg_is_last(sg)) {
size_t len = count % max_segment;
if (len)
sg_dma_len(sg) = len;
}
}
memset(&sconfig, 0, sizeof(sconfig));
sconfig.direction = dir;
sconfig.src_addr = offset;
err = dmaengine_slave_config(dbgdma->dchan, &sconfig);
if (err)
goto err_cfg;
tx = dmaengine_prep_slave_sg(dbgdma->dchan, sgt.sgl, sgt.nents,
dir, 0);
if (!tx) {
err = -EINVAL;
goto err_prep;
}
/* Setup the DMA completion callback */
dbgdma->dma_res.result = DMA_TRANS_NOERROR;
dbgdma->dma_res.residue = 0;
tx->callback_result = spec_fmca_dbg_dma_tx_complete;
tx->callback_param = (void *)dbgdma;
cookie = dmaengine_submit(tx);
if (cookie < 0) {
err = cookie;
goto err_sub;
}
dma_async_issue_pending(dbgdma->dchan);
err = wait_for_completion_interruptible_timeout(
&dbgdma->compl, msecs_to_jiffies(60000));
if (err == 0)
err = -ETIMEDOUT;
if (err > 0) {
switch (dbgdma->dma_res.result) {
case DMA_TRANS_NOERROR:
err = 0;
break;
default:
err = -EIO;
break;
}
}
err_sub:
err_prep:
err_cfg:
sg_free_table(&sgt);
err_sgt:
return err;
}
static ssize_t spec_fpga_dbg_dma_read(struct file *file, char __user *buf,
size_t count, loff_t *ppos)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
int err;
if (*ppos >= SPEC_DDR_SIZE)
return -EINVAL;
count = min(dbgdma->datalen, count);
err = spec_fpga_dbg_dma_transfer(file->private_data, DMA_DEV_TO_MEM,
count, *ppos);
if (err)
goto err_trans;
err = copy_to_user(buf, dbgdma->data, count);
if (err)
goto err_cpy;
*ppos += count;
return count;
err_cpy:
err_trans:
return err;
}
static ssize_t spec_fpga_dbg_dma_write(struct file *file,
const char __user *buf, size_t count,
loff_t *ppos)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
int err;
if (*ppos >= SPEC_DDR_SIZE)
return -EINVAL;
count = min(dbgdma->datalen, count);
err = copy_from_user(dbgdma->data, buf, count);
if (err)
goto err_cpy;
err = spec_fpga_dbg_dma_transfer(dbgdma, DMA_MEM_TO_DEV,
count, *ppos);
if (err)
goto err_trans;
*ppos += count;
return count;
err_trans:
err_cpy:
return err;
}
static bool spec_fpga_dbg_dma_filter(struct dma_chan *dchan, void *arg)
{
return dchan->device == arg;
}
static int spec_fpga_dbg_dma_open(struct inode *inode, struct file *file)
{
struct spec_fpga_dbg_dma *dbgdma;
struct spec_fpga *spec_fpga = inode->i_private;
dma_cap_mask_t dma_mask;
int err;
if (!spec_fpga->dma_pdev) {
dev_warn(&spec_fpga->dev,
"Not able to find DMA engine: platform_device missing\n");
return -ENODEV;
}
dbgdma = kzalloc(sizeof(*dbgdma), GFP_KERNEL);
if (!dbgdma)
return -ENOMEM;
init_completion(&dbgdma->compl);
dbgdma->spec_fpga = spec_fpga;
dbgdma->datalen = user_dma_coherent_size;
dbgdma->data = dma_alloc_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, &dbgdma->datadma,
GFP_KERNEL);
if (!dbgdma->data) {
err = -ENOMEM;
goto err_dma_alloc;
}
dma_cap_zero(dma_mask);
dma_cap_set(DMA_SLAVE, dma_mask);
dma_cap_set(DMA_PRIVATE, dma_mask);
dbgdma->dchan = dma_request_channel(dma_mask, spec_fpga_dbg_dma_filter,
platform_get_drvdata(spec_fpga->dma_pdev));
if (!dbgdma->dchan) {
dev_dbg(&spec_fpga->dev,
"DMA transfer Failed: can't request channel\n");
err = -EBUSY;
goto err_req;
}
file->private_data = dbgdma;
return 0;
err_req:
dma_free_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, dbgdma->data, dbgdma->datadma);
err_dma_alloc:
kfree(dbgdma);
return err;
}
static int spec_fpga_dbg_dma_flush(struct file *file, fl_owner_t id)
{
return 0;
}
static int spec_fpga_dbg_dma_release(struct inode *inode, struct file *file)
{
struct spec_fpga_dbg_dma *dbgdma = file->private_data;
dma_free_coherent(dbgdma->spec_fpga->dev.parent,
dbgdma->datalen, dbgdma->data, dbgdma->datadma);
dma_release_channel(dbgdma->dchan);
kfree(dbgdma);
return 0;
}
static const struct file_operations spec_fpga_dbg_dma_ops = {
.owner = THIS_MODULE,
.llseek = default_llseek,
.read = spec_fpga_dbg_dma_read,
.write = spec_fpga_dbg_dma_write,
.open = spec_fpga_dbg_dma_open,
.flush = spec_fpga_dbg_dma_flush,
.release = spec_fpga_dbg_dma_release,
};
static int spec_fpga_dbg_init(struct spec_fpga *spec_fpga)
{
struct pci_dev *pdev = to_pci_dev(spec_fpga->dev.parent);
......@@ -165,6 +431,19 @@ static int spec_fpga_dbg_init(struct spec_fpga *spec_fpga)
goto err;
}
spec_fpga->dbg_dma = debugfs_create_file(SPEC_DBG_DMA_NAME,
0444,
spec_fpga->dbg_dir_fpga,
spec_fpga,
&spec_fpga_dbg_dma_ops);
if (IS_ERR_OR_NULL(spec_fpga->dbg_dma)) {
err = PTR_ERR(spec_fpga->dbg_dma);
dev_err(&spec_fpga->dev,
"Cannot create debugfs file \"%s\" (%d)\n",
SPEC_DBG_DMA_NAME, err);
goto err;
}
return 0;
err:
debugfs_remove_recursive(spec_fpga->dbg_dir_fpga);
......@@ -849,6 +1128,7 @@ static void spec_fpga_app_exit(struct spec_fpga *spec_fpga)
static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
struct spec_meta_id *meta)
{
if ((meta->bom & SPEC_META_BOM_END_MASK) != SPEC_META_BOM_LE) {
dev_err(&spec_gn412x->pdev->dev,
"Expected Little Endian devices BOM: 0x%x\n",
......@@ -871,7 +1151,7 @@ static bool spec_fpga_is_valid(struct spec_gn412x *spec_gn412x,
return false;
}
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_1_4) {
if ((meta->version & SPEC_META_VERSION_MASK) != SPEC_META_VERSION_2_0) {
dev_err(&spec_gn412x->pdev->dev,
"Unknow version: %08x\n", meta->version);
return false;
......
......@@ -144,6 +144,10 @@ enum gn412x_dma_state {
};
#define GN412X_DMA_STAT_ACK BIT(2)
#define GN412X_DMA_DDR_ALIGN 4
#define GN412X_DMA_DDR_SIZE (256 * 1024 * 1024)
#define GN412X_DMA_MAX_SEG_R GN412X_DMA_DDR_SIZE
#define GN412X_DMA_MAX_SEG_W 0x1000
/**
* Transfer descriptor an hardware transfer
......@@ -349,7 +353,6 @@ static int gn412x_dma_alloc_chan_resources(struct dma_chan *dchan)
struct gn412x_dma_chan *chan = to_gn412x_dma_chan(dchan);
memset(&chan->sconfig, 0, sizeof(struct dma_slave_config));
chan->sconfig.direction = DMA_DEV_TO_MEM;
return 0;
}
......@@ -389,8 +392,8 @@ static void gn412x_dma_prep_fixup(struct gn412x_dma_tx_hw *tx_hw,
}
static void gn412x_dma_prep(struct gn412x_dma_tx_hw *tx_hw,
struct scatterlist *sg,
dma_addr_t start_addr)
struct scatterlist *sg, dma_addr_t start_addr,
enum dma_transfer_direction direction)
{
tx_hw->start_addr = start_addr & 0xFFFFFFFF;
tx_hw->dma_addr_l = sg_dma_address(sg);
......@@ -401,8 +404,10 @@ static void gn412x_dma_prep(struct gn412x_dma_tx_hw *tx_hw,
tx_hw->next_addr_l = 0x00000000;
tx_hw->next_addr_h = 0x00000000;
tx_hw->attribute = 0x0;
if (direction == DMA_MEM_TO_DEV)
tx_hw->attribute |= GN412X_DMA_ATTR_DIR_MEM_TO_DEV;
if (!sg_is_last(sg))
tx_hw->attribute = GN412X_DMA_ATTR_CHAIN;
tx_hw->attribute |= GN412X_DMA_ATTR_CHAIN;
}
static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
......@@ -417,12 +422,6 @@ static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
dma_addr_t src_addr;
int i;
if (unlikely(direction != DMA_DEV_TO_MEM)) {
dev_err(&chan->dev->device,
"Support only DEV -> MEM transfers\n");
goto err;
}
if (unlikely(sconfig->direction != direction)) {
dev_err(&chan->dev->device,
"Transfer and slave configuration disagree on DMA direction\n");
......@@ -455,10 +454,23 @@ static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
for_each_sg(sgl, sg, sg_len, i) {
dma_addr_t phys;
if (sg_dma_len(sg) > dma_get_max_seg_size(chan->device->dev)) {
if (direction == DMA_MEM_TO_DEV &&
sg_dma_len(sg) > GN412X_DMA_MAX_SEG_W) {
dev_err(&chan->dev->device,
"Maximum write transfer size %d, got %d on transfer %d\n",
GN412X_DMA_MAX_SEG_W, sg_dma_len(sg), i);
goto err_alloc_pool;
} else if (sg_dma_len(sg) > dma_get_max_seg_size(chan->device->dev)) {
dev_err(&chan->dev->device,
"Maximum transfer size %d, got %d on transfer %d\n",
0x3FFF, sg_dma_len(sg), i);
"Maximum read transfer size %d, got %d on transfer %d\n",
dma_get_max_seg_size(chan->device->dev),
sg_dma_len(sg), i);
goto err_alloc_pool;
}
if (sg_dma_len(sg) & (GN412X_DMA_DDR_ALIGN - 1)) {
dev_err(&chan->dev->device,
"Transfer size must be aligne to %d Bytes, got %d Bytes\n",
GN412X_DMA_DDR_ALIGN, sg_dma_len(sg));
goto err_alloc_pool;
}
gn412x_dma_tx->sgl_hw[i] = dma_pool_alloc(gn412x_dma->pool,
......@@ -478,7 +490,8 @@ static struct dma_async_tx_descriptor *gn412x_dma_prep_slave_sg(
} else {
gn412x_dma_tx->tx.phys = phys;
}
gn412x_dma_prep(gn412x_dma_tx->sgl_hw[i], sg, src_addr);
gn412x_dma_prep(gn412x_dma_tx->sgl_hw[i], sg, src_addr,
direction);
src_addr += sg_dma_len(sg);
}
......@@ -588,12 +601,16 @@ static int gn412x_dma_slave_config(struct dma_chan *chan,
sizeof(struct dma_slave_config));
spin_unlock_irqrestore(&gn412x_dma_chan->lock, flags);
if (gn412x_dma_chan->sconfig.src_addr & (GN412X_DMA_DDR_ALIGN - 1))
return -EINVAL;
return 0;
}
static int gn412x_dma_terminate_all(struct dma_chan *chan)
{
struct gn412x_dma_device *gn412x_dma;
struct gn412x_dma_tx *tx;
gn412x_dma = to_gn412x_dma_device(chan->device);
gn412x_dma_ctrl_abort(gn412x_dma);
......@@ -604,6 +621,15 @@ static int gn412x_dma_terminate_all(struct dma_chan *chan)
return -EINVAL;
}
tx = to_gn412x_dma_chan(chan)->tx_curr;
if (tx && tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_ABORTED,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
}
return 0;
}
......@@ -642,6 +668,15 @@ static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
/* FIXME check for spurious - need HDL fix */
gn412x_dma_irq_ack(gn412x_dma);
if (unlikely(chan->sconfig.direction == DMA_MEM_TO_DEV)) {
/*
* There is a bug in the HDL core, write path.
* The IRQ line is asserted before the actual end of transfer.
* A delay of 5us is the best compromise (empirical tests)
*/
ndelay(5000);
}
spin_lock_irqsave(&chan->lock, flags);
tx = chan->tx_curr;
chan->tx_curr = NULL;
......@@ -651,12 +686,27 @@ static irqreturn_t gn412x_dma_irq_handler(int irq, void *arg)
switch (state) {
case GN412X_DMA_STAT_IDLE:
dma_cookie_complete(&tx->tx);
if (tx->tx.callback)
if (tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_NOERROR,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
} else if (tx->tx.callback) {
tx->tx.callback(tx->tx.callback_param);
}
break;
case GN412X_DMA_STAT_ERROR:
dev_err(&gn412x_dma->pdev->dev,
"DMA transfer failed: error\n");
if (tx->tx.callback_result) {
const struct dmaengine_result result = {
.result = DMA_TRANS_READ_FAILED,
.residue = 0,
};
tx->tx.callback_result(tx->tx.callback_param, &result);
}
dev_err(&gn412x_dma->pdev->dev, "DMA transfer failed: error\n");
break;
default:
dev_err(&gn412x_dma->pdev->dev,
......@@ -770,7 +820,7 @@ static int gn412x_dma_engine_init(struct gn412x_dma_device *gn412x_dma,
tasklet_init(&gn412x_dma->chan.task, gn412x_dma_start_task,
(unsigned long)&gn412x_dma->chan);
dma_set_max_seg_size(dma->dev, 0x7FFF);
dma_set_max_seg_size(dma->dev, GN412X_DMA_DDR_SIZE);
gn412x_dma->pool = dma_pool_create(dev_name(dma->dev), dma->dev,
sizeof(struct gn412x_dma_tx_hw),
......
......@@ -39,6 +39,8 @@
#define GN4124_GPIO_SCL 5
#define GN4124_GPIO_SDA 4
#define SPEC_DDR_SIZE (256 * 1024 * 1024)
/**
* @SPEC_FPGA_SELECT_FPGA_FLASH: (default) the FPGA is an SPI master that can
* access the flash (at boot it takes its
......@@ -83,7 +85,7 @@ enum {
#define SPEC_META_BOM_END_MASK 0xFFFF0000
#define SPEC_META_BOM_VER_MASK 0x0000FFFF
#define SPEC_META_VERSION_MASK 0xFFFF0000
#define SPEC_META_VERSION_1_4 0x01040000
#define SPEC_META_VERSION_2_0 0x02000000
/**
* struct spec_meta_id Metadata
......@@ -125,6 +127,8 @@ struct spec_fpga {
struct debugfs_regset32 dbg_csr_reg;
#define SPEC_DBG_BLD_INFO_NAME "build_info"
struct dentry *dbg_bld;
#define SPEC_DBG_DMA_NAME "dma"
struct dentry *dbg_dma;
};
/**
......
#!/usr/bin/python3
import os
import re
import argparse
import math
from matplotlib import pyplot
from PySPEC import PySPEC
def dma_time_get(trace):
start = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_start_task", trace, re.MULTILINE)
assert start is not None, trace
assert len(start.groups()) == 1
end = re.search(r"([0-9]+\.[0-9]{6}): gn412x_dma_irq_handler", trace, re.MULTILINE)
assert end is not None, trace
assert len(end.groups()) == 1
return round(float(end.group(1)) - float(start.group(1)), 6)
def main():
parser = argparse.ArgumentParser(description='DMA Throughput')
parser.add_argument('--pci-id', dest='pciid', required=True,
help='SPEC PCI ID to use')
parser.add_argument('--min', default=4 * 1024, type=int,
help='Minimum transfer size in Bytes (default: 4096 Bytes). It is rounded to the lower power of 2.')
parser.add_argument('--max', default=4 * 1024 * 1024, type=int,
help='Maximum transfer size in Bytes (default: 4194304 Bytes). It is rounded to the lower power of 2.')
parser.add_argument('--seg', default=0, type=int,
help='Overwrite scatterlist segment size.')
args = parser.parse_args()
tracing_path = "/sys/kernel/debug/tracing"
with open(os.path.join(tracing_path, "current_tracer"), "w") as f:
f.write("function")
with open(os.path.join(tracing_path, "set_ftrace_filter"), "w") as f:
f.write("gn412x_dma_irq_handler\ngn412x_dma_start_task")
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
spec = PySPEC(args.pciid)
throughput = []
sizes = [2**x for x in range(int(math.log2(args.min)), int(math.log2(args.max)) + 1)]
for size in sizes:
with open(os.path.join(tracing_path, "trace"), "w") as f:
f.write("")
with spec.dma(size) as dma:
dma.read(0, size, args.seg)
with open(os.path.join(tracing_path, "trace"), "r") as f:
throughput.append((float(size) / 1024 / 1024) / dma_time_get(f.read()))
print("{:d} Bytes -> {:f} MBps".format(size, throughput[-1]))
pyplot.title("DMA throughput at different block sizes")
pyplot.xlabel("DMA Size in Bytes")
pyplot.ylabel("Throughput in MBps")
pyplot.plot(sizes,throughput)
pyplot.show()
if __name__ == "__main__":
main()
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