Commits · master · Projects / VHDL macro libraries for Microsemi ProASIC3 · Open Hardware Repository

25 Jun, 2019 2 commits
- Fixed some bugs in the newly-introduced smartfusion2 memory models · 7055c055
  Christos Gentsos authored Jun 25, 2019
  
  7055c055
- Added some more models to the smartfusion2 library · 104f3b9d
  Christos Gentsos authored Jun 25, 2019
  
  104f3b9d
14 May, 2019 10 commits
- Moved LICENSE · 175f2391
  Christos Gentsos authored May 14, 2019
  
  175f2391
- Updated README · 04e5f3b7
  Christos Gentsos authored May 14, 2019
  
  04e5f3b7
- Slightly renamed macro directories · dfbef9c1
  Christos Gentsos authored May 14, 2019
  
  dfbef9c1
- Added SmartFusion2 / Igloo 2 macro libraries · 0f18869d
  Christos Gentsos authored May 06, 2019
  
  0f18869d
- When the design had no registers sim would segfault · f13ca8c6
  Christos Gentsos authored May 06, 2019
  
  f13ca8c6
- Added some ProASIC3 I/O buffers · f1ca9159
  Christos Gentsos authored May 06, 2019
  
  f1ca9159
- Improved reg flipping, reg flip verbosity, package to disable C bind · 7a4de665
  Christos Gentsos authored Apr 24, 2019
  
  7a4de665
- Toggle A3P library registers to test TMR implementation · a323236f
  Christos Gentsos authored Apr 24, 2019
  
  a323236f
- Added two more gates to the A3P macro library · ca04bc26
  Christos Gentsos authored Apr 24, 2019
  
  ca04bc26
- Added ProASIC3 libraries, post-synthesis sim now runs with GHDL · cdea6aad
  Christos Gentsos authored Apr 11, 2019
  
  cdea6aad
08 May, 2019 1 commit
- Initial commit · 63ef3b3b
  Erik van der Bij authored May 08, 2019
  
  63ef3b3b