Added two more gates to the A3P macro library

ca04bc26 · Christos Gentsos · cdea6aad · ca04bc26 · ca04bc26
Commit ca04bc26 authored Apr 24, 2019 by Christos Gentsos
Hide whitespace changes
Inline Side-by-side

Showing with 42 additions and 0 deletions

gate_XAI1.vhdl proasic3_my/gate_XAI1.vhdl +21 -0

gate_XAI1A.vhdl proasic3_my/gate_XAI1A.vhdl +21 -0

No files found.
--- a/proasic3_my/gate_XAI1.vhdl
+++ b/proasic3_my/gate_XAI1.vhdl
+-- proasic3/gate_XAI1.vhdl
+-- created mer. oct. 17 04:16:21 CEST 2018 by Yann Guidon (whygee@f-cpu.org)
+-- Released under the GNU AGPLv3 license (see the license/ directory)
+-- Just a little replacement for the Actel ProASIC3 gates/macros library
+--  to help simulate optimised source code.
+
+Library ieee;
+    use ieee.std_logic_1164.all;
+
+Library delay;
+    use delay.generic_delay.all;
+
+entity XAI1 is
+  port( A, B, C : in std_logic;
+              Y : out std_logic );
+end XAI1;
+
+architecture rtl of XAI1 is
+begin
+  Y <= not ((A xor B) and C) after gate_delay;
+end rtl;
--- a/proasic3_my/gate_XAI1A.vhdl
+++ b/proasic3_my/gate_XAI1A.vhdl
+-- proasic3/gate_XAI1A.vhdl
+-- created mer. oct. 17 04:16:21 CEST 2018 by Yann Guidon (whygee@f-cpu.org)
+-- Released under the GNU AGPLv3 license (see the license/ directory)
+-- Just a little replacement for the Actel ProASIC3 gates/macros library
+--  to help simulate optimised source code.
+
+Library ieee;
+    use ieee.std_logic_1164.all;
+
+Library delay;
+    use delay.generic_delay.all;
+
+entity XAI1A is
+  port( A, B, C : in std_logic;
+              Y : out std_logic );
+end XAI1A;
+
+architecture rtl of XAI1A is
+begin
+  Y <= not ((not (A xor B)) and C) after gate_delay;
+end rtl;