Fixed some bugs in the newly-introduced smartfusion2 memory models

7055c055 · Christos Gentsos · 104f3b9d · 7055c055
Commit 7055c055 authored Jun 25, 2019 by Christos Gentsos
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Showing with 14 additions and 8 deletions

smartfusion2.vhd smartfusion2/smartfusion2.vhd +14 -8

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--- a/smartfusion2/smartfusion2.vhd
+++ b/smartfusion2/smartfusion2.vhd
@@ -1863,6 +1863,9 @@ architecture rtl of RAM1K18 is
  signal A_DIN_r : std_logic_vector(17 downto 0);
  signal B_DIN_r : std_logic_vector(17 downto 0);

+  signal A_WMODE_r : std_logic;
+  signal B_WMODE_r : std_logic;
+
  signal dout_a_toreg : std_logic_vector(17 downto 0);
  signal dout_b_toreg : std_logic_vector(17 downto 0);

@@ -1881,9 +1884,6 @@ begin  -- architecture rtl
  width_a <= return_width(A_WIDTH);
  width_b <= return_width(B_WIDTH);

-  wen_a <= return_wen(A_WEN);
-  wen_b <= return_wen(B_WEN);
-
  -- purpose: main memory process (both ports)
  main_proc: process (A_CLK, B_CLK) is
    variable mem_addr : integer;
@@ -1892,8 +1892,11 @@ begin  -- architecture rtl
  begin

    if rising_edge(A_CLK) then          -- rising clock edge
-      A_ADDR_r <= A_ADDR;
-      A_DIN_r <= A_DIN;
+      A_ADDR_r  <= A_ADDR;
+      A_DIN_r   <= A_DIN;
+      A_WMODE_r <= A_WMODE;
+
+      wen_a <= return_wen(A_WEN);

      mem_addr := to_integer(unsigned(A_ADDR_r(13 downto 4)));

@@ -1928,8 +1931,11 @@ begin  -- architecture rtl
    end if;

    if rising_edge(B_CLK) then          -- rising clock edge
-      B_ADDR_r <= B_ADDR;
-      B_DIN_r <= B_DIN;
+      B_ADDR_r  <= B_ADDR;
+      B_DIN_r   <= B_DIN;
+      B_WMODE_r <= B_WMODE;
+
+      wen_b <= return_wen(B_WEN);

      mem_addr := to_integer(unsigned(B_ADDR_r(13 downto 4)));

@@ -1957,7 +1963,7 @@ begin  -- architecture rtl
      if wen_b = MEM_READ then
        dout_b_toreg <= mem18b_to_dout(width_b, B_ADDR_r, mem(mem_addr));
      else
-        if B_WMODE = '1' then
+        if B_WMODE_r = '1' then
          dout_b_toreg <= B_DIN_r;
        end if;
      end if;