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Hdlmake
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75dbfdde359ba138b8487c9bac8dcf27568ee1ad
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hdl-make
tests
counter
top
brevia2_dk
verilog
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Simple 8-bit counter test for syn/sim, VHDL/Verilog
· cc56877a
garcialasheras
authored
Sep 16, 2014
cc56877a
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Manifest.py
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brevia2_top.v
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