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Hdlmake
Commits
cc56877a
Commit
cc56877a
authored
Sep 16, 2014
by
garcialasheras
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Simple 8-bit counter test for syn/sim, VHDL/Verilog
parent
1d66eb8b
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85 changed files
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991 additions
and
1882 deletions
+991
-1882
Manifest.py
tests/counter/modules/counter/verilog/Manifest.py
+4
-0
counter.v
tests/counter/modules/counter/verilog/counter.v
+30
-0
Manifest.py
tests/counter/modules/counter/vhdl/Manifest.py
+4
-0
counter.vhd
tests/counter/modules/counter/vhdl/counter.vhd
+45
-0
play_sim.do
tests/counter/sim/aldec/play_sim.do
+5
-0
Manifest.py
tests/counter/sim/aldec/verilog/Manifest.py
+10
-0
Manifest.py
tests/counter/sim/aldec/vhdl/Manifest.py
+10
-0
Manifest.py
tests/counter/sim/ghdl/vhdl/Manifest.py
+9
-0
isim_cmd
tests/counter/sim/isim/isim_cmd
+5
-0
Manifest.py
tests/counter/sim/isim/verilog/Manifest.py
+12
-0
Manifest.py
tests/counter/sim/isim/vhdl/Manifest.py
+12
-0
Manifest.py
tests/counter/sim/iverilog/verilog/Manifest.py
+10
-0
Manifest.py
tests/counter/sim/modelsim/verilog/Manifest.py
+9
-0
Manifest.py
tests/counter/sim/modelsim/vhdl/Manifest.py
+9
-0
vsim.do
tests/counter/sim/modelsim/vsim.do
+6
-0
Manifest.py
tests/counter/syn/brevia2_dk_diamond/verilog/Manifest.py
+14
-0
Manifest.py
tests/counter/syn/brevia2_dk_diamond/vhdl/Manifest.py
+14
-0
Manifest.py
tests/counter/syn/cyclone3_sk_quartus/verilog/Manifest.py
+17
-0
Manifest.py
tests/counter/syn/cyclone3_sk_quartus/vhdl/Manifest.py
+17
-0
Manifest.py
tests/counter/syn/proasic3_sk_libero/verilog/Manifest.py
+15
-0
Manifest.py
tests/counter/syn/proasic3_sk_libero/vhdl/Manifest.py
+15
-0
Manifest.py
tests/counter/syn/spec_v4_ise/verilog/Manifest.py
+14
-0
Manifest.py
tests/counter/syn/spec_v4_ise/vhdl/Manifest.py
+5
-3
Manifest.py
tests/counter/syn/spec_v4_planahead/verilog/Manifest.py
+14
-0
Manifest.py
tests/counter/syn/spec_v4_planahead/vhdl/Manifest.py
+14
-0
Manifest.py
tests/counter/testbench/counter_tb/verilog/Manifest.py
+7
-0
counter_tb.v
tests/counter/testbench/counter_tb/verilog/counter_tb.v
+41
-0
Manifest.py
tests/counter/testbench/counter_tb/vhdl/Manifest.py
+7
-0
counter_tb.vhd
tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
+60
-0
brevia2_top.lpf
tests/counter/top/brevia2_dk/brevia2_top.lpf
+15
-0
Manifest.py
tests/counter/top/brevia2_dk/verilog/Manifest.py
+8
-0
brevia2_top.v
tests/counter/top/brevia2_dk/verilog/brevia2_top.v
+34
-0
Manifest.py
tests/counter/top/brevia2_dk/vhdl/Manifest.py
+8
-0
brevia2_top.vhd
tests/counter/top/brevia2_dk/vhdl/brevia2_top.vhd
+57
-0
module.tcl
tests/counter/top/cyclone3_sk/module.tcl
+36
-0
pinout.tcl
tests/counter/top/cyclone3_sk/pinout.tcl
+20
-0
Manifest.py
tests/counter/top/cyclone3_sk/verilog/Manifest.py
+7
-0
cyclone3_top.v
tests/counter/top/cyclone3_sk/verilog/cyclone3_top.v
+31
-0
Manifest.py
tests/counter/top/cyclone3_sk/vhdl/Manifest.py
+7
-0
cyclone3_top.vhd
tests/counter/top/cyclone3_sk/vhdl/cyclone3_top.vhd
+56
-0
proasic3_top.pdc
tests/counter/top/proasic3_sk/proasic3_top.pdc
+31
-0
proasic3_top.sdc
tests/counter/top/proasic3_sk/proasic3_top.sdc
+24
-0
Manifest.py
tests/counter/top/proasic3_sk/verilog/Manifest.py
+9
-0
proasic3_top.v
tests/counter/top/proasic3_sk/verilog/proasic3_top.v
+31
-0
Manifest.py
tests/counter/top/proasic3_sk/vhdl/Manifest.py
+9
-0
proasic3_top.vhd
tests/counter/top/proasic3_sk/vhdl/proasic3_top.vhd
+55
-0
spec_top.ucf
tests/counter/top/spec_v4/spec_top.ucf
+19
-0
Manifest.py
tests/counter/top/spec_v4/verilog/Manifest.py
+5
-0
spec_top.v
tests/counter/top/spec_v4/verilog/spec_top.v
+31
-0
Manifest.py
tests/counter/top/spec_v4/vhdl/Manifest.py
+5
-0
spec_top.vhd
tests/counter/top/spec_v4/vhdl/spec_top.vhd
+59
-0
half2.v
tests/filter/modules/filtdec/half2.v
+0
-59
half2_tb.v
tests/filter/modules/filtdec/half2_tb.v
+0
-66
half3.v
tests/filter/modules/filtdec/half3.v
+0
-63
half3_tb.v
tests/filter/modules/filtdec/half3_tb.v
+0
-69
reg_delay.v
tests/filter/modules/filtdec/reg_delay.v
+0
-27
myfilter.vhd
tests/filter/modules/fir/myfilter.vhd
+0
-111
tb_myfilter.vhd
tests/filter/modules/fir/tb_myfilter.vhd
+0
-1049
Manifest.py
tests/filter/sim/verilog/simulation_isim/Manifest.py
+0
-11
isim_cmd
tests/filter/sim/verilog/simulation_isim/isim_cmd
+0
-4
run.sh
tests/filter/sim/verilog/simulation_isim/run.sh
+0
-6
Manifest.py
tests/filter/sim/verilog/simulation_modelsim/Manifest.py
+0
-11
run.sh
tests/filter/sim/verilog/simulation_modelsim/run.sh
+0
-8
vsim.do
tests/filter/sim/verilog/simulation_modelsim/vsim.do
+0
-4
Manifest.py
tests/filter/sim/vhdl/simulation_isim/Manifest.py
+0
-10
isim_cmd
tests/filter/sim/vhdl/simulation_isim/isim_cmd
+0
-4
run.sh
tests/filter/sim/vhdl/simulation_isim/run.sh
+0
-6
Manifest.py
tests/filter/sim/vhdl/simulation_modelsim/Manifest.py
+0
-10
run.sh
tests/filter/sim/vhdl/simulation_modelsim/run.sh
+0
-8
vsim.do
tests/filter/sim/vhdl/simulation_modelsim/vsim.do
+0
-4
Manifest.py
tests/filter/syn/verilog/synthesis_altera/Manifest.py
+0
-17
run.sh
tests/filter/syn/verilog/synthesis_altera/run.sh
+0
-7
run_local.sh
tests/filter/syn/verilog/synthesis_xilinx/run_local.sh
+0
-5
run_remote.sh
tests/filter/syn/verilog/synthesis_xilinx/run_remote.sh
+0
-13
Manifest.py
tests/filter/syn/vhdl/synthesis_altera/Manifest.py
+0
-14
run.sh
tests/filter/syn/vhdl/synthesis_altera/run.sh
+0
-7
run_local.sh
tests/filter/syn/vhdl/synthesis_xilinx/run_local.sh
+0
-5
run_remote.sh
tests/filter/syn/vhdl/synthesis_xilinx/run_remote.sh
+0
-13
.gitignore
tests/lr_test/.gitignore
+0
-1
Manifest.py
tests/lr_test/Manifest.py
+0
-6
isim_cmd
tests/lr_test/isim_cmd
+0
-1
run.sh
tests/lr_test/run.sh
+0
-10
top_module.vhd
tests/lr_test/top_module.vhd
+0
-76
top_module_tb.vhd
tests/lr_test/top_module_tb.vhd
+0
-96
wave.wcfg
tests/lr_test/wave.wcfg
+0
-78
No files found.
tests/counter/modules/counter/verilog/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"counter.v"
,
]
tests/counter/modules/counter/verilog/counter.v
0 → 100644
View file @
cc56877a
//-----------------------------------------------------
// Design : Simple 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//-----------------------------------------------------
module
counter
(
clock
,
clear
,
count
,
Q
)
;
//--------- Output Ports ------------------------------
output
[
7
:
0
]
Q
;
//--------- Input Ports -------------------------------
input
clock
,
clear
,
count
;
//--------- Internal Variables ------------------------
reg
[
7
:
0
]
Q
;
//--------- Code Starts Here --------------------------
always
@
(
posedge
clock
)
if
(
clear
)
begin
Q
<=
8'b0
;
end
else
if
(
count
)
begin
Q
<=
Q
+
1
;
end
endmodule
tests/counter/modules/counter/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"counter.vhd"
,
]
tests/counter/modules/counter/vhdl/counter.vhd
0 → 100644
View file @
cc56877a
-------------------------------------------------------
-- Design : Simple 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
-------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
numeric_std
.
all
;
-------------------------------------------------------
entity
counter
is
port
(
clock
:
in
std_logic
;
clear
:
in
std_logic
;
count
:
in
std_logic
;
Q
:
out
std_logic_vector
(
7
downto
0
)
);
end
counter
;
-------------------------------------------------------
architecture
behv
of
counter
is
signal
Pre_Q
:
unsigned
(
7
downto
0
);
begin
process
(
clock
,
count
,
clear
)
begin
if
clear
=
'1'
then
Pre_Q
<=
"00000000"
;
elsif
(
clock
=
'1'
and
clock
'event
)
then
if
count
=
'1'
then
Pre_Q
<=
Pre_Q
+
1
;
end
if
;
end
if
;
end
process
;
Q
<=
std_logic_vector
(
Pre_Q
);
end
behv
;
-------------------------------------------------------
tests/counter/sim/aldec/play_sim.do
0 → 100644
View file @
cc56877a
asim +access +r counter_tb
trace -rec *
run 6 us
endsim
quit
tests/counter/sim/aldec/verilog/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"aldec"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
tests/counter/sim/aldec/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"aldec"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsimsa -do ../play_sim.do; avhdl wave.asdb"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/vhdl"
],
}
tests/counter/sim/ghdl/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"ghdl"
top_module
=
"counter_tb"
sim_post_cmd
=
"ghdl -r counter_tb --stop-time=6us --vcd=counter_tb.vcd; gtkwave counter_tb.vcd"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/vhdl"
],
}
tests/counter/sim/isim/isim_cmd
0 → 100644
View file @
cc56877a
wave add /
vcd dumpfile counter_tb.vcd
vcd dumpvars -m counter_tb -l 1
run 6000 ns
#exit
tests/counter/sim/isim/verilog/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
target
=
"xilinx"
sim_tool
=
"isim"
top_module
=
"counter_tb"
sim_post_cmd
=
"./isim_proj -gui -tclbatch ../isim_cmd"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
tests/counter/sim/isim/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
target
=
"xilinx"
sim_tool
=
"isim"
top_module
=
"counter_tb"
sim_post_cmd
=
"./isim_proj -gui -tclbatch ../isim_cmd"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/vhdl"
],
}
tests/counter/sim/iverilog/verilog/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"iverilog"
top_module
=
"counter_tb"
sim_post_cmd
=
"vvp counter_tb.vvp; gtkwave counter_tb.vcd"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
tests/counter/sim/modelsim/verilog/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsim -do ../vsim.do -i counter_tb"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/verilog"
],
}
tests/counter/sim/modelsim/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
action
=
"simulation"
sim_tool
=
"modelsim"
top_module
=
"counter_tb"
sim_post_cmd
=
"vsim -do ../vsim.do -i counter_tb"
modules
=
{
"local"
:
[
"../../../testbench/counter_tb/vhdl"
],
}
tests/counter/sim/modelsim/vsim.do
0 → 100644
View file @
cc56877a
vcd file counter_tb.vcd;
vcd add -r /*;
add wave *
run 6000ns;
view wave;
tests/counter/syn/brevia2_dk_diamond/verilog/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"lattice"
action
=
"synthesis"
syn_device
=
"lfxp2-5e"
syn_grade
=
"-6"
syn_package
=
"tn144c"
syn_top
=
"brevia2_top"
syn_project
=
"demo"
syn_tool
=
"diamond"
modules
=
{
"local"
:
[
"../../../top/brevia2_dk/verilog"
],
}
tests/counter/syn/brevia2_dk_diamond/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"lattice"
action
=
"synthesis"
syn_device
=
"lfxp2-5e"
syn_grade
=
"-6"
syn_package
=
"tn144c"
syn_top
=
"brevia2_top"
syn_project
=
"demo"
syn_tool
=
"diamond"
modules
=
{
"local"
:
[
"../../../top/brevia2_dk/vhdl"
],
}
tests/counter/syn/cyclone3_sk_quartus/verilog/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"altera"
action
=
"synthesis"
syn_device
=
"ep3c25"
syn_grade
=
"c6"
syn_package
=
"f324"
syn_top
=
"cyclone3_top"
syn_project
=
"demo"
syn_tool
=
"quartus"
quartus_preflow
=
"../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule
=
"../../../top/cyclone3_sk/module.tcl"
modules
=
{
"local"
:
[
"../../../top/cyclone3_sk/verilog"
],
}
tests/counter/syn/cyclone3_sk_quartus/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"altera"
action
=
"synthesis"
syn_device
=
"ep3c25"
syn_grade
=
"c6"
syn_package
=
"f324"
syn_top
=
"cyclone3_top"
syn_project
=
"demo"
syn_tool
=
"quartus"
quartus_preflow
=
"../../../top/cyclone3_sk/pinout.tcl"
quartus_postmodule
=
"../../../top/cyclone3_sk/module.tcl"
modules
=
{
"local"
:
[
"../../../top/cyclone3_sk/vhdl"
],
}
tests/counter/syn/proasic3_sk_libero/verilog/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"microsemi"
action
=
"synthesis"
syn_device
=
"a3p250"
syn_grade
=
"-2"
syn_package
=
"208 pqfp"
syn_top
=
"proasic3_top"
syn_project
=
"demo"
syn_tool
=
"libero"
modules
=
{
"local"
:
[
"../../../top/proasic3_sk/verilog"
],
}
tests/counter/syn/proasic3_sk_libero/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"microsemi"
action
=
"synthesis"
syn_device
=
"a3p250"
syn_grade
=
"-2"
syn_package
=
"208 pqfp"
syn_top
=
"proasic3_top"
syn_project
=
"demo"
syn_tool
=
"libero"
modules
=
{
"local"
:
[
"../../../top/proasic3_sk/vhdl"
],
}
tests/
filter/syn/verilog/synthesis_xilinx
/Manifest.py
→
tests/
counter/syn/spec_v4_ise/verilog
/Manifest.py
View file @
cc56877a
...
...
@@ -4,12 +4,11 @@ action = "synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"
half2
"
syn_project
=
"
half2
.xise"
syn_top
=
"
spec_top
"
syn_project
=
"
demo
.xise"
syn_tool
=
"ise"
files
=
[
"../../../modules/filtdec/half2.v"
,
"../../../modules/filtdec/reg_delay.v"
]
modules
=
{
"local"
:
[
"../../../top/spec_v4/verilog"
],
}
tests/
filter/syn/vhdl/synthesis_xilinx
/Manifest.py
→
tests/
counter/syn/spec_v4_ise/vhdl
/Manifest.py
View file @
cc56877a
...
...
@@ -4,9 +4,11 @@ action = "synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"
myfilter
"
syn_project
=
"
myfilter
.xise"
syn_top
=
"
spec_top
"
syn_project
=
"
demo
.xise"
syn_tool
=
"ise"
files
=
[
"../../../modules/fir/myfilter.vhd"
]
modules
=
{
"local"
:
[
"../../../top/spec_v4/vhdl"
],
}
tests/counter/syn/spec_v4_planahead/verilog/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_top"
syn_project
=
"demo"
syn_tool
=
"planahead"
modules
=
{
"local"
:
[
"../../../top/spec_v4/verilog"
],
}
tests/counter/syn/spec_v4_planahead/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
target
=
"xilinx"
action
=
"synthesis"
syn_device
=
"xc6slx45t"
syn_grade
=
"-3"
syn_package
=
"fgg484"
syn_top
=
"spec_top"
syn_project
=
"demo"
syn_tool
=
"planahead"
modules
=
{
"local"
:
[
"../../../top/spec_v4/vhdl"
],
}
tests/counter/testbench/counter_tb/verilog/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"counter_tb.v"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/verilog"
],
}
tests/counter/testbench/counter_tb/verilog/counter_tb.v
0 → 100644
View file @
cc56877a
//--------------------------------------------------------
// Design : Simple testbench for an 8-bit verilog counter
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module
counter_tb
()
;
// Declare inputs as regs and outputs as wires
reg
clock
,
clear
,
count
;
wire
[
7
:
0
]
Q
;
// Initialize all variables
initial
begin
$
dumpfile
(
"counter_tb.vcd"
)
;
$
dumpvars
(
0
,
counter_tb
)
;
$
display
(
"time
\t
clock clear count Q"
)
;
$
monitor
(
"%g
\t
%b %b %b %b"
,
$
time
,
clock
,
clear
,
count
,
Q
)
;
clock
=
1
;
// initial value of clock
clear
=
0
;
// initial value of clear
count
=
0
;
// initial value of count enable
#
5
clear
=
1
;
// Assert the clear signal
#
10
clear
=
0
;
// De-assert clear signal
#
10
count
=
1
;
// Start count
#
2000
count
=
0
;
// De-assert count enable
#
5
$
finish
;
// Terminate simulation
end
// Clock generator
always
begin
#
5
clock
=
~
clock
;
// Toggle clock every 5 ticks
end
// Connect DUT to test bench
counter
U_counter
(
clock
,
clear
,
count
,
Q
)
;
endmodule
tests/counter/testbench/counter_tb/vhdl/Manifest.py
0 → 100644
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cc56877a
files
=
[
"counter_tb.vhd"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/vhdl"
],
}
tests/counter/testbench/counter_tb/vhdl/counter_tb.vhd
0 → 100644
View file @
cc56877a
----------------------------------------------------------
-- Design : Simple testbench for an 8-bit VHDL counter
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
entity
counter_tb
is
-- entity declaration
end
counter_tb
;
-----------------------------------------------------------------------
architecture
testbench
of
counter_tb
is
component
counter
port
(
clock
:
in
std_logic
;
clear
:
in
std_logic
;
count
:
in
std_logic
;
Q
:
out
std_logic_vector
(
7
downto
0
)
);
end
component
;
signal
t_clock
:
std_logic
;
signal
t_clear
:
std_logic
;
signal
t_count
:
std_logic
;
signal
t_Q
:
std_logic_vector
(
7
downto
0
);
begin
U_counter
:
counter
port
map
(
t_clock
,
t_clear
,
t_count
,
t_Q
);
process
begin
t_clock
<=
'0'
;
-- clock cycle is 10 ns
wait
for
5
ns
;
t_clock
<=
'1'
;
wait
for
5
ns
;
end
process
;
process
begin
t_clear
<=
'1'
;
-- start counting
t_count
<=
'1'
;
wait
for
50
ns
;
t_clear
<=
'0'
;
-- clear output
wait
for
1000
ns
;
report
"Testbench of Adder completed successfully!"
severity
note
;
wait
;
end
process
;
end
testbench
;
----------------------------------------------------------------
tests/counter/top/brevia2_dk/brevia2_top.lpf
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View file @
cc56877a
BLOCK RESETPATHS ;
BLOCK ASYNCPATHS ;
LOCATE COMP "led_o_0" SITE "46" ;
LOCATE COMP "led_o_1" SITE "45" ;
LOCATE COMP "led_o_2" SITE "44" ;
LOCATE COMP "led_o_3" SITE "43" ;
LOCATE COMP "led_o_4" SITE "40" ;
LOCATE COMP "led_o_5" SITE "39" ;
LOCATE COMP "led_o_6" SITE "38" ;
LOCATE COMP "led_o_7" SITE "37" ;
LOCATE COMP "clear_i" SITE "50" ;
LOCATE COMP "count_i" SITE "53" ;
LOCATE COMP "clock_i" SITE "21" ;
LOCATE COMP "clken_o" SITE "22" ;
tests/counter/top/brevia2_dk/verilog/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"brevia2_top.v"
,
"../brevia2_top.lpf"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/verilog"
],
}
tests/counter/top/brevia2_dk/verilog/brevia2_top.v
0 → 100644
View file @
cc56877a
//--------------------------------------------------------
// Design : Counter verilog top module, Lattice Brevia2
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------
module
brevia2_top
(
clear_i
,
count_i
,
clock_i
,
clken_o
,
led_o
)
;
input
clear_i
,
count_i
,
clock_i
;
output
clken_o
;
output
[
7
:
0
]
led_o
;
wire
s_clock
,
s_clear
,
s_count
;
wire
[
7
:
0
]
s_Q
;
counter
u1
(
.
clock
(
s_clock
)
,
.
clear
(
s_clear
)
,
.
count
(
s_count
)
,
.
Q
(
s_Q
)
)
;
assign
s_clock
=
clock_i
;
assign
clken_o
=
1
;
assign
s_clear
=
~
clear_i
;
assign
s_count
=
~
count_i
;
assign
led_o
[
7
:
0
]
=
~
s_Q
[
7
:
0
]
;
endmodule
tests/counter/top/brevia2_dk/vhdl/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"brevia2_top.vhd"
,
"../brevia2_top.lpf"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/vhdl"
],
}
tests/counter/top/brevia2_dk/vhdl/brevia2_top.vhd
0 → 100644
View file @
cc56877a
----------------------------------------------------------
-- Design : Counter VHDL top module, Lattice Brevia2
-- Author : Javier D. Garcia-Lasheras
----------------------------------------------------------
library
ieee
;
use
ieee
.
std_logic_1164
.
all
;
use
ieee
.
std_logic_unsigned
.
all
;
use
ieee
.
std_logic_arith
.
all
;
entity
brevia2_top
is
port
(
clear_i
:
in
std_logic
;
count_i
:
in
std_logic
;
clock_i
:
in
std_logic
;
clken_o
:
out
std_logic
;
led_o
:
out
std_logic_vector
(
7
downto
0
)
);
end
brevia2_top
;
----------------------------------------------------------
architecture
structure
of
brevia2_top
is
component
counter
port
(
clock
:
in
std_logic
;
clear
:
in
std_logic
;
count
:
in
std_logic
;
Q
:
out
std_logic_vector
(
7
downto
0
)
);
end
component
;
signal
s_clock
:
std_logic
;
signal
s_clear
:
std_logic
;
signal
s_count
:
std_logic
;
signal
s_Q
:
std_logic_vector
(
7
downto
0
);
begin
U_counter
:
counter
port
map
(
clock
=>
s_clock
,
clear
=>
s_clear
,
count
=>
s_count
,
Q
=>
s_Q
);
s_clock
<=
clock_i
;
clken_o
<=
'1'
;
s_clear
<=
not
clear_i
;
s_count
<=
not
count_i
;
led_o
<=
not
s_Q
;
end
architecture
structure
;
----------------------------------------------------------------
tests/counter/top/cyclone3_sk/module.tcl
0 → 100644
View file @
cc56877a
set
module
[
lindex
$quartus
(
args
)
0
]
if
[
string
match
"quartus_map"
$module
]
{
# Include commands here that are run
# after analysis and synthesis
post_message
"Running after analysis & synthesis"
}
if
[
string
match
"quartus_fit"
$module
]
{
# Include commands here that are run
# after fitter
(
Place & Route
)
post_message
"Running after place & route"
}
if
[
string
match
"quartus_asm"
$module
]
{
# Include commands here that are run
# after assembler
(
Generate programming files
)
post_message
"Running after timing analysis"
}
if
[
string
match
"quartus_tan"
$module
]
{
# Include commands here that are run
# after timing analysis
post_message
"Running after timing analysis"
}
tests/counter/top/cyclone3_sk/pinout.tcl
0 → 100644
View file @
cc56877a
post_message
"Assigning pinout"
# Load Quartus II Tcl Project package
package
require ::quartus::project
project_open -revision demo demo
set_location_assignment PIN_F1 -to clear_i
set_location_assignment PIN_F2 -to count_i
set_location_assignment PIN_B9 -to clock_i
set_location_assignment PIN_N9 -to led_o
[
3
]
set_location_assignment PIN_N12 -to led_o
[
2
]
set_location_assignment PIN_P12 -to led_o
[
1
]
set_location_assignment PIN_P13 -to led_o
[
0
]
# Commit assignments
export_assignments
project_close
tests/counter/top/cyclone3_sk/verilog/Manifest.py
0 → 100644
View file @
cc56877a
files
=
[
"cyclone3_top.v"
,
]
modules
=
{
"local"
:
[
"../../../modules/counter/verilog"
],
}
tests/counter/top/cyclone3_sk/verilog/cyclone3_top.v
0 → 100644
View file @
cc56877a
//--------------------------------------------------------------------
// Design : Counter verilog top module, Altera CycloneIII Starter Kit
// Author : Javier D. Garcia-Lasheras
//--------------------------------------------------------------------
module
cyclone3_top
(
clear_i
,
count_i
,
clock_i
,