Skip to content
Projects
Groups
Snippets
Help
Loading...
Sign in
Toggle navigation
H
Hdlmake
Project
Project
Details
Activity
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Issues
15
Issues
15
List
Board
Labels
Milestones
Merge Requests
4
Merge Requests
4
Wiki
Wiki
image/svg+xml
Discourse
Discourse
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Create a new issue
Commits
Issue Boards
Open sidebar
Projects
Hdlmake
Issues
Open
7
Closed
34
All
41
New issue
Recent searches
Press Enter or click to search
{{hint}}
{{tag}}
{{name}}
@{{username}}
No Assignee
{{name}}
@{{username}}
No Milestone
Upcoming
Started
{{title}}
No Label
{{title}}
{{name}}
Yes
No
Created date
Priority
Created date
Last updated
Milestone
Due date
Popularity
Label priority
[Vivado] Source files generated from IP customization files (xci) not included in library 'work'
#112
· opened
Jun 29, 2021
by
Augusto Fraga Giachero
bug
CLOSED
1
updated
Jun 30, 2021
--sufix command is a typo => rename to --suffix for proper english
#90
· opened
Apr 30, 2019
by
Nicolas Chevillot
bug
CLOSED
1
0
updated
Jun 03, 2019
VHDL parser: instantiations with archietecture selection
#2
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
VHDL parser: split entity and architecture
#3
· opened
Mar 21, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Feb 12, 2019
pip installation
#4
· opened
Mar 20, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Mar 30, 2019
Hdlmake vsim & xsim targets compile verilog headers as separate files.
#8
· opened
Feb 03, 2018
by
Tomasz Wlostowski
bug
CLOSED
2
updated
Mar 29, 2019
[SV + UVM]: modelsim and +incdir+
#9
· opened
Jan 30, 2018
by
Adrian Fiergolski
bug
CLOSED
2
updated
Mar 30, 2019
[SV + UVM]: Could not find a top level file
#10
· opened
Jan 26, 2018
by
Adrian Fiergolski
bug
CLOSED
1
updated
Mar 30, 2019
Do not fetch submodules recursively
#15
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Flatten option for Fetch doesn't work
#16
· opened
Jul 22, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Quit upon error should generate an error code different than 0
#21
· opened
May 31, 2016
by
Nicolas Chevillot
bug
CLOSED
1
updated
Mar 30, 2019
List-files doesn't generate the parsed dependency-driven fileset
#26
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
2
updated
Mar 29, 2019
Hdlmake includes the target file when generating a simulation Makefile
#27
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
The information about "circular[...] dependency dropped" is neither error nor warning
#28
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
parser fails to find includes from SV files
#29
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
The parser doesn't work with VHD records
#31
· opened
May 29, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Mar 29, 2019
Add legacy support for Altera tools
#33
· opened
Apr 14, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
pop from empty list when processing specific Verilog File
#35
· opened
Apr 13, 2016
by
Andreas Bergmann (Consult)
bug
CLOSED
3
updated
Apr 09, 2019
Hdlmake now depends on the networkx package
#39
· opened
Mar 30, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Wrong version for ISE project in generated .xise files
#41
· opened
Mar 24, 2016
by
Javier D. Garcia-Lasheras
bug
CLOSED
1
updated
Feb 12, 2019
Prev
1
2
Next