No need to compile all sources if you know you don't need them to satify the dependencies.

Overwrites the file list in an Altera Qsys component hardware TCL description file.

Builds the limited set of files that is required to satisfy the dependencies of the top level entity/module. 

For use when you don't need one - like when just listing files in dependency order.

Previous implelmentaiton only worked for a single level tree of dependencies.
This implementations recursively determines the number of levels below a dep_file and uses this value as the key to sort by. The 'dependendency level is cached in the dep_file object to reduce the number of recursive calls.
Will not handle circular dependencies well.

Add architecture to vhdl parser, so that dependencies are generated between the architecture and the entity which may be in different files.
Causes problem in new_dep_solver when entity and architecture are in the same file because now a file will depends on itself (which it technically does). When re-expressing the VHDL dependencies as file dependencies we avoid creating the circular dependency to itself.

Add missing import logging.

No need to compile all sources if you know you don't need them to satify the dependencies.

Overwrites the file list in an Altera Qsys component hardware TCL description file.

Builds the limited set of files that is required to satisfy the dependencies of the top level entity/module. 

For use when you don't need one - like when just listing files in dependency order.

Previous implelmentaiton only worked for a single level tree of dependencies.
This implementations recursively determines the number of levels below a dep_file and uses this value as the key to sort by. The 'dependendency level is cached in the dep_file object to reduce the number of recursive calls.
Will not handle circular dependencies well.

Add architecture to vhdl parser, so that dependencies are generated between the architecture and the entity which may be in different files.
Causes problem in new_dep_solver when entity and architecture are in the same file because now a file will depends on itself (which it technically does). When re-expressing the VHDL dependencies as file dependencies we avoid creating the circular dependency to itself.

Add missing import logging.

Better granularity for ISE remote synthesis. New targets: remote_synthesize, remote_translate, remote_map, remote_par, remote_bitstream

Improved granularity for the Makefile driven local ISE synthesis process. New targets are: synthesize, translate, map, par, bitstream