Commits · 5c7c8e07acfc942b0d9a6e311cca854dbe33212b · Projects / Hdlmake · Open Hardware Repository

13 Mar, 2017 10 commits
- Handle hdl as a dictionay in Aldec Active-HDL · 5c7c8e07
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  5c7c8e07
- Handle hdl and supported files as a dictionay in Lattice Diamond · b18e9fbc
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  b18e9fbc
- Add a new Verilog test for Vivado simulation · d983c430
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  d983c430
- Handle hdl files as a dictionay in Modelsim and Riviera · 583bd9e0
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  583bd9e0
- Handle hdl files as a dictionay in ISim · d9fb59f2
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  d9fb59f2
- Handle hdl files as a dictionay in GHDL · 526d4af3
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  526d4af3
- Handle hdl files as a dictionay in IVerilog · 6b10d73a
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  6b10d73a
- Handle hdl and supported files as a dictionay and test it on PlanAhead · 4db27266
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  4db27266
- Handle hdl and supported files as a dictionay and test it on Vivado · 42600066
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  42600066
- Handle hdl and supportedfiles as a dictionay and test it on Quartus · d255ef82
  Javier D. Garcia-Lasheras authored Mar 13, 2017
  
  d255ef82
12 Mar, 2017 8 commits
- Don't print anything when the file dictionary entry points to None · 01122f43
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  01122f43
- Handle hdl and supportedfiles as a dictionay and test it on ISE · 594750f9
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  594750f9
- Handle hdl_files as a dictionay and test it on IceStorm · 434c9f5e
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  434c9f5e
- Refactor Vivado and PlanAhead so that they support the new project stage · 414f5740
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  414f5740
- Refactor Quartus so that it supports the new project stage · c3d259de
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  c3d259de
- Refactor ISE so that it supports the new project stage · 600dc408
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  600dc408
- IceStorm doesn't use a project, so move the stuff to synthesize · e73d287a
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  e73d287a
- Add project as an optional synthesis stage in the Makefile · 9d12aab0
  Javier D. Garcia-Lasheras authored Mar 12, 2017
  
  9d12aab0
11 Mar, 2017 5 commits
- Clean-up on the IceStorm makefile generator · d659370c
  Javier D. Garcia-Lasheras authored Mar 11, 2017
  
  d659370c
- Attribute 'manifest_dict' defined outside __init__ · c384ef83
  Javier D. Garcia-Lasheras authored Mar 11, 2017
  
  c384ef83
- Minor fixes on make synthesis file · 503a6d49
  Javier D. Garcia-Lasheras authored Mar 11, 2017
  
  503a6d49
- Refactor how the combined project manifest is calculated · 1428cb08
  Javier D. Garcia-Lasheras authored Mar 11, 2017
  
  1428cb08
- Update the help messages for fetch and list-files commands · 212d24b3
  Javier D. Garcia-Lasheras authored Mar 11, 2017
  
  212d24b3
10 Mar, 2017 3 commits
- Use generics in VHDL counter test to select sim and syn dividers · 03047436
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  03047436
- Update the VHDL counter test · 7feedf4d
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  7feedf4d
- Update Verilog counter test: counter + shifter · feff4994
  Javier D. Garcia-Lasheras authored Mar 10, 2017
  
  feff4994
09 Mar, 2017 3 commits
- Add the counter test for IceStorm synthesis · 1879e826
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  1879e826
- Initial support for IceStorm synthesis · 852c1f43
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  852c1f43
- Refactor the TCL section generation code · a257c698
  Javier D. Garcia-Lasheras authored Mar 09, 2017
  
  a257c698
08 Mar, 2017 3 commits
- More elegant TCL code on the Xilinx ISE Makefile section for files · 0735b9a0
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  0735b9a0
- Support for syn_properties variable in Xilinx ISE · 7de23880
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  7de23880
- Read the commit id from the Git submodule if available · 81f8c750
  Javier D. Garcia-Lasheras authored Mar 08, 2017
  
  81f8c750
06 Mar, 2017 4 commits
- Purge the unused synthesis stages for each of the supported tools · 3427cf5f
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  3427cf5f
- Remove blank line from Xilinx TCL error checking · 754e247d
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  754e247d
- Add error checking in synthesis for Xilinx PlanAhead and Vivado · 91c3b301
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  91c3b301
- Only add the ip_repo_paths property if the dir list is not empty · f6a02063
  Javier D. Garcia-Lasheras authored Mar 06, 2017
  
  f6a02063
05 Mar, 2017 4 commits
- HDLMake creates a Makefile, not a project: fix message · c7cc50b5
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  c7cc50b5
- Delete extension from project name if provided at the Manifest.py -- fix indentation · eaf8c8ce
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  eaf8c8ce
- Delete extension from project name if provided at the Manifest.py · 071810dc
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  071810dc
- Add error checking on the ISE synthesis TCL scripts · b1192242
  Javier D. Garcia-Lasheras authored Mar 05, 2017
  
  b1192242